高速线性反馈移位寄存器的实现

线性反馈移位寄存器（ＬＦＳＲ）被广泛用于扩频通信，内建自测试和数字加密等许多领域。文中针对这一类电路的物理实现，提出了利用动态双边沿触发器实现高速线性反馈移位寄存器的一种新型结构。在不增加电路代价的前提下，获得了两倍于传统主－从铁速度，在此基础上，提出双相并行结构，从理论上分析，可得到最高的移位速度。     

一种可重构线性反馈移位寄存器设计

提出了一种可重构线性反馈移位寄存器的设计。在设计中,针对Fibonacci和Galois两种类型的反馈结构分别采用了可重构的设计,并且支持混合反馈结构,线性反馈移位寄存器反馈抽头和插入点可选,长度可变并且可以通过链接支持超长线性反馈移位寄存器。在XC5VLX30器件上实现延时为4.808ns,LUT和触发器的个数为2279和1575。能够用于伪随机序列生成等应用。     

基于模代数的三值维持阻塞触发器及其应用

本文给出了基于模代数理论的三值维持阻塞触发器,并将其应用到时序逻辑电路设计中。由于多值模代数中的两个基本运算和运算结果均为多值信号,所以它的应用避免了以往在采用基于Ｐｏｓｔ代数的三值触发器时,由于输入、输出信号不匹配而必须增加附加编码电路的问题。设计实例表明,该触发器具有更强的逻辑功能,它使得移位寄存器类的时序电路设计得以显著简化。     

电路穷尽测试的线性反馈移位寄存器系列

本文介绍了在Ｇａｌｏｉｓ域ＧＦ（２）上线性反馈移位寄存器的链接原理，并给出了一种高级数的线性反馈移位寄存器如何由低级数线性反馈移位寄存器构成的方法，以满足对具有不同输入端数目电路测试的要求。初步的实验结果表明，从８至２４级的线性反馈移位寄存器都可以由１至７级的线性反馈移位寄存器链接构成。     

内建自测试(BIST)简介上篇 原理(续)

附录线性反馈移位寄存器(LFSR)理论由于线性反馈移位寄存器在结构上简单而且相当规则,其移位性质容易与串行扫描结合起来,而且能够生成穷举和/或伪随机测试向量,所以在BIST中广泛应用。LFSR的典型元件是D触发器和XOR(异或)门。这里只涉及LFSR作为测试生成器和响应分析器时的性质。图A列出了两个典型LFSR。两者都用D触发器和线性逻辑元件(XOR门)。它们的基本区别是图A1电路在触发器之间用XOR而图     

有限域上一种新的求逆电路

求逆运算在编码理论和密码学中有着广泛的应用,因此设计简洁高效的求逆电路具有重要的现实意义。基于线性反馈移位寄存器和逻辑门,采用比特串行搜索方法,设计了一种新的应用于有限域上的求逆电路。该电路与用ROM查表法或纯组合逻辑电路实现求逆相比可节省芯片资源,且易于实现,具有广阔的应用前景。     

低功耗四边沿触发器设计

根据在保持电路原有性能的前提下可通过降低时钟频率来降低系统功耗的原理和双边沿触发器的设计思想,本文将多值信号信息量大的优点应用于时钟网络上设计了基于三值时钟的四边沿触发器,消除了三值时钟的冗余跳变,从而通过降低时钟频率的方式达到降低功耗的目的。本文设计的四边沿触发器电路结构简单,既可以用于二值时序电路中也可以用于多值时序电路中。模拟结果表明,本文设计的四边沿触发器具有正确的逻辑功能且能有效地降低系统功耗。     

一种用于SAR A/D转换器的高速移位寄存器

基于65 nm标准 CMOS工艺,提出了一种单次触发的动态D型触发器。基于这种D型触发器,设计了一种用于逐次逼近型(SAR)A/D转换器的高速移位寄存器。在传统的SAR A/D转换器转换过程中,比较器每比较1次,逻辑模块就进行1次移位和1次锁存,每1次移位延迟约为2个D触发器的工作时间,因此,限制了整个系统的转换速度。相比于传统的移位寄存器,本文设计的高速移位寄存器兼具移位和锁存的特点,仅需要传统结构一半数量的D触发器就能实现输出移位和锁存功能。这种寄存器结构能够将A/D转换器的转换速度提升45%,且功耗更小。     

基于门控时钟技术的低功耗三值D型触发器设计

本文在三值D型触发器的基础上提出了一种低功耗三值门控时钟D型触发器的设计.该设计通过抑制触发器的冗余触发来降低功耗,PSPICE模拟验证了该触发器具有正确的逻辑功能.与三值D触发器相比,该触发器在输入信号开关活动性较低的情况下具有更低的功耗.同时该电路结构可以推广到基值更高的低功耗多值触发器的设计中.     

有限域与线性反馈移位寄存器

研究了有限域与线性反馈移位寄存器之间的内在联系，简捷地证明了产生线性反馈移位寄存器序列几种方法的等价性以及产生m序列的条件，这对产生、掌握、运用P值m序列很有益处。     

High-speed testing of Josephson logic circuits by an on-chip signal-pattern generator

We have developed an on-chip signal-pattern generator (SPG) for high-speed testing of latching-type Josephson logic circuits. The basis of the SPG is using a feedback shift register, in which the complement output of the last-stage LATCH gate (a D flip-flop) is fed back to the first-stage LATCH gate. Since the SPG consists of only LATCH gates and requires no external input signal, the design and high-speed operation are greatly simplified. We performed a high-speed measurement of the 1-bit SPG and found that the SPG has the potential to operate at a speed of more than 4.6 GHz. We also demonstrated a high-speed testing of a 2-bit logic circuit with the 2-bit SPG up to a clock frequency of 1 GHz.     

高斯噪声源电路的设计与实现

为了实现占用资源少、精度高的高斯噪声源电路,设计了一种新的高斯噪声产生方案,该方案在FPGA上通过线性反馈移位寄存器产生高速均匀分布伪随机数,接着利用均匀分布与高斯分布之间的映射关系生成高斯噪声,并创新地采用非均匀划分的折线逼近映射曲线,同时设计寻址电路,从而减少噪声源占用的资源,改善噪声精度。在XILINX Virtex5 XC5VLX50T上的实现结果表明,该方案仅使用了2%的可配置SLICE和1块片上BRAM,实现了±4σ(σ为标准偏差)的高斯噪声源。时序分析表明其最高频率可达131 MHz。     

Cyclic code weight spectra and BIST aliasing

In built-in self-test for logic circuits, test data reduction can be achieved using a linear feedback shift register. The probability that this data reduction will allow a faulty circuit to be declared good is the probability of aliasing. Based on the independent bit-error model, we show that the code spectra for the cyclic code generated by the feedback polynomial can be used to obtain an exact expression for the aliasing probability of a multiple input signature register when the test length is a multiple of the cycle length. Several cases are examined and, as expected, primitive feedback polynomials provide the best performance. Some suggestions to avoid peaks in the aliasing probability are given.     

Gated-Clock Design of Linear-Feedback Shift Registers

In this paper, we will present a method to reduce the power consumption of the popular linear feedback shift register. The proposed scheme is based on the gated clock design approach and it can offer a significant power reduction, depending on technological characteristics of the employed gates. Moreover, the analytical condition that must be satisfied to achieve a power reduction of the gated-clock circuit has been found. Theoretical analysis was validated through many transistor-level SPECTRE simulations in CADENCE environment by using the 0.35- mum digital standard cells technology supplied by AMS. Simulation results have shown a power reduction of about 10% with a mean error of about 3% with respect to theoretical derivations.     

Aliasing properties of circular MISRs

In built-in self-test for logic circuits, test data reduction can be achieved using a linear feedback shift register. The probability of this data reduction allowing a faulty circuit to be declared good is the probability of aliasing. This article examines aliasing in circular multiple-input shift-registers (MISRs), under the independent bit error model. We present an exact closed form expression for aliasing probability without assuming equiprobable bit error probabilities. We show that the aliasing probability can be much larger than its asymptotic value. Irrespective of the register length we prove that for a circular MISR, when two inputs are used for testing out ofm possible inputs, high minimum spatial separations between inputs result in low aliasing probabilities. We also show that for equiprobable errors an m-bit circular MISR can be replaced with a set ofm single-bit MISRs without affecting aliasing probability or adding any additional logic, to reduce the propagation delay due to feedback path. The above features can be used as criteria for the MISR design.     

Pseudorandom bit generator based on dynamic linear feedbacktopology

A novel pseudorandom bit generator is presented. It is based on a shift register with a dynamic linear feedback, which, compared to the linear feedback, improves its inviolability property. The proposed circuit exhibits statistical characteristics similar to a linear feedback pseudorandom bit generator with equivalent length. Moreover, the proposed topology, evaluated with the most common randomness tests, gives excellent results     

ON SHORTENING TEST SEQUENCE LENGTH FOR SIGNATURE ANALYZER

Based on the built-in self-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register. The test length for the worst faults can be obtained by analyzing compressed signature . Finally, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.     

一种基于FPGA的分布式FIR数字滤波器设计

在宽带中频软件无线电台收发系统中,由于FIR滤波器具有良好的线性相位特性及实现的灵活性,通常将它作为数字上下变频中的整形低通滤波器.本设计采用altera公司的CycloneⅡ系列中的EP2C20Q240C8芯片,以一个8阶分布式算法的FIR低通数字滤波器电路为例,其主要通过LUT、加法器和移位寄存器实现.最后对该分布式算法进行了仿真验证.结果表明,该优化结构高效合理地利用FPGA硬件资源,可有效应用于高性能中频数字电台的信号处理模块.     

移位寄存器的Multisim仿真

介绍用Multisim仿真软件分析移位寄存器逻辑功能的方法,验证了4-D触发器构成的移位寄存器的逻辑功能。用Multisim仿真软件中的字组产生器产生的信号作为移位寄存器的时钟脉冲和输入数据,字组内容反映移位寄存器的输入信号和控制信号,用Multisim中的逻辑分析仪多踪同步显示各输入信号、控制信号和输出信号波形,直观地描述移位寄存器的工作过程。所述方法创新地解决了移位寄存器工作过程无法用实验仪器验证的问题。