A fast quarter-pixel motion estimation algorithm for H.264/AVC

A fast quarter-pixel motion estimation algorithm is proposed in this paper. The proposed algorithm based on mathematical models of the motion compensated prediction errors. Unlike conventional quarter-pixel accurate motion estimation algorithm, proposed algorithm can avoid fractional-pixel interpolation and subsequent fracfional-pixel search after integer-precision motion estimation. Experiments show that the proposed algorithm greatly reduces the computational complexity of quarterpixel motion estimation, while keeping the nearly equal quality of the image     

H.264/AVC中快速1/4像素运动估计算法

提出了一种快速1/4像素的运动估计算法.该算法基于运动补偿预测误差模型,与传统的1/4像素的分层运动估计算法不同,仅通过一步计算就能直接得到1/4像素精度的运动矢量,而且完全避免了运算量很大的分数像素内插运算和整像素搜索完成后的分数像素搜索.实验结果表明,该算法在保持图像质量的前提下极大地减少了1/4像素运动估计的运算量.     

Fast multi-frame motion estimation for H264/AVC system

Advanced video compression standard, H264/AVC, with multi-frame motion estimation, can offer better motion-compensation than the previous coding standards. However, the implementation of real-time multi-frame estimation for an H264/AVC system is difficult due to heavy computations. In this paper, a fast algorithm is proposed in an effort to reduce the searching computation for motion estimation with five reference frames. The fast multi-frame motion estimation consists of the adaptive full-search, three-step search, and diamond search methods using the content adaptive control process. Efficient control flow is proposed to select the searching algorithm dependent on video features. The adaptive algorithm can achieve better rate-distortion and lower computation for H264/AVC coding. The experiments indicate that the speed-up is 6–15 times compared with the full search method, while the image quality slightly degrades.     

H.264/AVC运动估计算法的硬件结构研究

运动估计是H.264/AVC编码器的重要组成部分,其运算量占据了整个编码器计算时间的60%~90%。对H.264/AVC运动估计的几种快速搜索算法进行分析比较,并在此基础上提出先进的六边形搜索算法。给出运动估计快速搜索算法的一般硬件结构,并在此基础上提出具有流水线并行处理能力的先进六边形搜索算法的硬件结构。实验结果表明：该硬件结构系统工作频率能够达到109.06 MHz,完全能够满足高清视频实时应用的要求。     

Fast variable-size block motion estimation for efficient H.264/AVC encoding

In this paper, an efficient algorithm is proposed to reduce the computational complexity of variable-size block-matching motion estimation. We first investigate features of multiple candidate search centers, adaptive initial-blocksizes, search patterns, and search step-sizes, to match different motion characteristics and block-sizes. To avoid being trapped in local minima, the proposed algorithm uses multiple candidate motion vectors, which are obtained from different block-sizes. To further reduce the computation cost, a threshold-based early stop strategy according to the quantization parameter is suggested. With adaptive initial block-sizes, a merge-or-skip strategy is also proposed to reduce the computation for the final block-size decision. For the H.264/AVC encoder, simulations show that the proposed algorithms can speed up about 2.6–3.9 times of the original JM v6.1d encoder, which uses fast full-search for all block-sizes, and still maintain a comparable rate-distortion performance.     

H.264/AVC中基于全零块检测的运动估计快速算法

全零块检测是面向低比特率的视频编码器常用优化方法之一.特别是与运动估计相结合,可以有效的减少编码器的计算复杂性.本文根据H.264/AVC中整数变换的特点,给出了相应的全零块检测门限,提出了一种基于全零块检测的运动搜索提前中止准则.针对H.264/AVC多编码模式的特点,进一步将全零块检测用于H.264/AVC中多种编码模式的选择,有效的提高了运动估计的效率.利用这种方法,在有效减少编码器的计算复杂性,提高H.264/AVC软件编码器编码效率的同时,可以保持比特率和图像质量基本不变.     

Hardware implementation and validation of the fast variable block size motion estimation architecture for H.264/AVC

Block matching motion estimation is the heart of video coding system. It leads to a high compression ratio, whereas it is time consuming and calculation intensive. Many fast search block matching motion estimation algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose an efficient hardware architecture of the fast line diamond parallel search (LDPS) algorithm with variable block size motion estimation (VBSME) for H.264/AVC video coding system. The design is described in VHDL language, synthesized to Altera Stratix III FPGA and to TSMC 0.18 μm standard-cells. The throughput of the hardware architecture reaches a processing rate up to 78 millions of pixels per second at 83.5 MHz frequency clock and uses only 28 kgates when mapped to standard-cells. Finally, a system on a programmable chip (SoPC) implementation and validation of the proposed design as an IP core is presented using the embedded video system.     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

一种基于H.264/AVC帧内预测模式选择的快速算法

依据宏块的空间相关性,并从概率的角度考虑,提出了一种新的快速模式选择算法,该方法减少了对Intra4×4和Intra16×16的预测模式率失真的计算,降低了帧内预测编码的复杂度.与参考软件JM11.0中模式选择算法相比,在PSNR基本保持不变的情况下,新算法的编码时间缩短了大约30%,而比特率仅提高了1%左右.     

Parallel fast inter mode decision for H.264/AVC encoding

For H.264/AVC encoding, the mode selection process consumes a large proportion of the overall computation. To reduce this burden, various fast mode decision algorithms have been proposed. The current fast mode decision algorithms usually exploit the relationship among the coding modes and use the context-based approach to reduce the number of modes to be checked for both intra coding and inter coding. The parallel capacity of hardware architectures are also taken into consideration. However, almost all the parallel fast mode decision designs are focusing on intra coding. In this paper, a hardware friendly parallel fast inter mode decision method is proposed. With the proposed method, the inter mode decision can be conducted efficiently in one pass and significant encoding speedup can be achieved with negligible coding efficiency loss. Moreover, the proposed method can be easily mapped to hardware architecture which can be used for the real-time video encoding.     

A fast rate-distortion optimization algorithm for H.264/AVC codec

Rate-distortion optimization (RDO) selects the mode that achieves the highest coding performance at the minimum cost after all coding modes have been computed. Unfortunately, the extreme complexity of RDO operations can severely impact real-time applications. To save coding time, we propose intra-mode-ignored decision and early skip mode prediction procedures. The former is based on the inter-coding results, such that the intra-mode may be disregarded for predictive frame coding. In the latter, a simple criterion can determine whether skip mode should be employed before performing the intra- and inter-mode procedures. Experimental results show that these two methods can significantly reduce the encoding time, by an average approximately 24 and 15%, respectively. A hybrid of the two methods could save an additional 36%, while maintaining an optimum RD.     

Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC

Bidirectional motion estimation (ME) significantly enhances video coding efficiency, whereas its huge complexity is also a critical problem for implementation. This paper presents alternating asymmetric search range assignment (AASRA) schemes to reduce the complexity by switching the use of a large and a small search ranges (SR.L and SR.S). A temporal AASRA (T-AASRA) scheme performs search range switching between past and future reference directions. A temporal-spatial AASRA (TS-AASRA) scheme performs more aggressive switching on the two dimensions of reference direction and MB/CTB index. T-AASRA and TS-AASRA achieve 43.5% and 65.2% complexity reduction, respectively, with small coding efficiency drop. Even after removing the factor of coding efficiency drop, the two schemes still show 38.4% and 54.7% equivalent complexity reduction. AASRA can also be combined with existing fast algorithms for further complexity saving, which has been demonstrated on hierarchical ME and dynamic search range selection algorithms.     

基于H.264运动估计算法的改进与优化

在H.264视频编码标准中,运动估计是最重要也是最耗时的过程,目前H.264标准中采用UMHexagons算法,本文结合H.264的验证模型在JM8.6的源代码上对UMHexagons进行分析,利用视频图像序列运动矢量的分布规律以及当前块像素之间运动估计代价的相关性,对搜索模板和搜索步长进行改进,从而提前结束搜索,减少运动估计时间,实验结果表明:改进后的算法在保证性噪比(PSNR)变化不大的前提下,运动估计时间降低10%以上。     

Fast motion estimation for H.264

Several specific features have been incorporated into Motion estimation (ME) in H.264 coding standard to improve its coding efficiency. However, they result in very high computational load. In this paper, a fast ME algorithm is proposed to reduce the computational complexity. First, a mode discriminant method is used to free the encoder from checking the small block size modes in homogeneous regions. Second, a condensed hierarchical block matching method and a spatial neighbor searching scheme are employed to find the best full-pixel motion vector. Finally, direction-based selection rule is utilized to reduce the searching range in sub-pixel ME process. Experimental results on commonly used QCIF and CIF format test sequences have shown that the proposed algorithm achieves a reduction of 88% ME process time on average, while incurring only 0.033 dB loss in PSNR and 0.50% increment on the total bit rate compared with that of exhaustive ME process, which is a default approach adopted in the JM reference software.     

An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVC

Motion estimation (ME) is the most critical component of a video coding standard. H.264/AVC adopts the variable block size motion estimation (VBSME) to obtain excellent coding efficiency, but the high computational complexity makes design difficult. This paper presents an effective processor chip for integer motion estimation (IME) in H264/AVC based on the full-search block-matching algorithm (FSBMA). It uses architecture with a configurable 2D systolic array to obtain a high data reuse of search area. This systolic array supports a three-direction scan format in which only one row of pixels is changed between the two adjacent subblocks, thus reducing the memory accesses and saving clock cycles. A computing array of 64 PEs calculates the SAD of basic 4×4 subblocks and a modified Lagrangian cost is used as matching criterion to find the best 41 variable-size blocks by means of a tree pipeline parallel architecture. Finally, a mode decision module uses serial data flow to find the best mode by comparing the total minimum Lagrangian costs. The IME processor chip was designed in UMC 0.18 μm technology resulting in a circuit with only 32.3 k gates and 6 RAMs (total 59kBits on-chip memory). In typical working conditions (25 °C, 1.8 V), a clock frequency of 300 MHz can be estimated with a processing capacity for HDTV (1920×1088 @ 30 fps) and a search range of 32×32.     

一种新的H.264多参考帧快速搜索算法

H.264/AVC是目前最新的视频编码国际标准.在H.264/AVC中,由于采用了多参考帧,运动估计部分的复杂度大大增加了.虽然JVT采用的快速运动估计(FME)提案能极大地提高搜索速度,但只是加快了一帧的搜索速度.本文在FME基础上提出了一种新的多参考帧快速搜索算法(FMRSA),它利用当前块周围的块信息来预测将要搜索的参考帧的范围,并在具体搜索过程中运用提前中断的方法加快整个搜索过程.实验证明本算法比标准快速搜索法搜索5个参考帧能在PSNR降低不超过0.05dB、码率增加不超过2.32%的情况下节省至少56.5%的时间.     

Hardware design of motion data decoding process for H.264/AVC

In H.264/AVC, motion data can be basically derived by the following two schemes: one is a typical spatial prediction scheme based on the DPCM and the other is a sophisticated spatiotemporal prediction scheme for the skipped motion data, formally referred to as a direct mode. We verified through instruction level profiling that when these schemes are combined with various H.264/AVC coding techniques, the computational burden to derive the motion data could be considerably aggravated. Specifically, its computational complexity amounts to maximally 55% of that of the overall syntax parsing process. In this paper, we aim at an efficient hardware design of the motion data decoding process for H.264/AVC, for which all the key design considerations are addressed in detail and respective rational answers are presented. As comparing the resulting hardware design with the processor-based solution, its effectiveness was clearly demonstrated. The proposed design was implemented with 43.2 K logic gates and three on-chip memories of 3584 bits using Samsung Semiconductor’s Standard Cell Library in 65 nm L6LP process technology (SS65LP), and was capable of operating the H.264/AVC high-profile video bitstream of 1080p@60fps at 100 MHz consuming 843 μW.     

基于H.264/AVC的视频信息隐藏算法

在H.264/AVC的帧内预测环节,调制H.264/AVC编码中I帧4×4亮度块的帧内预测模式实现信息隐藏.这种调制基于该模式与待隐藏比特之间的映射规则进行.宿主4×4块的具体位置由各块自身特点结合密钥所指定的嵌入位置模板确定.信息的提取过程不需要原始视频内容,也不需完全解码,而只要对码流中的帧内预测模式进行解码即可.     

一种适宜于H.264/AVC的帧间快速编码算法

针对新一代视频编码技术H.264/AVC编码计算复杂 度较高,为提高其编码速度,提出了一种新的适宜于H.264/AVC 的帧间快速编码算法。首先利用运 动和纹理预测可能的编码模式,排除可能性较小的模式;然后利用时间和空间相关性预测各 种编码模式的 可能性大小和编码顺序,并结合相关性和量化参数利用率失真和残差系数提前终止。实验结 果表明,本文算法编码速度能提高72%左右,同时对编码效率影响很小。     

General Architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC Intra Frame Transcoding

The latest international video-coding standard H.264/AVC significantly achieves better coding performance compared to prior video coding standards such as MPEG-2 and H.263, which have been widely used in today’s digital video applications. To provide the interoperability between different coding standards, this paper proposes an efficient architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC intra frame transcoding, using the original information such as discrete cosine transform (DCT) coefficients and coded mode type. Low-frequency components of DCT coefficients and a novel rate distortion cost function are used to select a set of candidate modes for rate distortion optimization (RDO) decision. For H.263 and H.264/AVC, a mode refinement scheme is utilized to eliminate unlikely modes before RDO mode decision, based on coded mode information. The experimental results, conducted on JM12.2 with fast C8MB mode decision, reveal that average 58%, 59% and 60% of computation (re-encoding) time can be saved for MPEG-2, H.263, H.264/AVC to H.264/AVC intra frame transcodings respectively, while preserving good coding performance when compared with complex cascaded pixel domain transcoding (CCPDT); or average 88% (a speed up factor of 8) when compared with CCPDT without considering fast C8MB. The proposed algorithm for H.264/AVC homogeneous transcoding is also compared to the simple cascaded pixel domain transcoding (with original mode reuse). The results of this comparison indicate that the proposed algorithm significantly outperforms the mode reuse algorithm in coding performance, with only slightly higher computation.