一种单芯片无线收发系统设计

为了使无线收发系统能方便地应用于无线传感器网络、蓝牙技术与无限局域网（WLAN）等领域,采用了片上系统设计方法,将无线收发系统设计在一块单芯片上,使其最小化。给出了单芯片无线电的基本结构及电路实现的若干组成部分（混频器,低噪音放大器,功率放大器等）的解决方案。电路具有体积小,低功耗,成本低,可靠性高的特点。     

Realistic end-to-end simulation of the optoelectronic links andcomparison with the electrical interconnections for system-on-chipapplications

A detailed comparison of optoelectronic versus electrical interconnections for system-on-chip applications is performed in terms of signal latency and power consumption. Realistic end-to-end models of both interconnection schemes are employed in order to evaluate critical performance parameters. A variety of electrical and optoelectronic interconnection configurations are implemented and simulated using accurate optical device and electronic circuit models integrated under an integrated circuit (IC) design computer-aided design tool. Two commercial complementary metal-oxide-semiconductor (CMOS) technologies (0.8 μm and 0.25 μm) are used for the estimation of the signal latency and the power consumption as a function of the interconnection length for the different link configurations. It was found that optoelectronic interconnects outperform their electrical counterparts, under certain conditions, especially for relatively long lines and multichannel data links     

Narrow-band low-noise amplifier synthesis for high-performance system-on-chip design

In this paper, we present a systematic synthesis methodology for fully integrated narrow-band CMOS low-noise amplifiers (LNAs) in high-performance system-on-chip (SoC) designs. The methodology is based on deterministic gradient-based numerical nonlinear optimization and the normal boundary intersection (NBI) method for Pareto optimization. We simultaneously optimize transistor widths, bias voltages, and input and output matching network passive components, which yields integrated inductor values that are more than one order of magnitude less than those generated by several existing equation-based LNA design techniques. By generating significantly smaller inductor values, we enable the SoC integration of the complete LNA. When the synthesized LNAs are characterized using circuit-level simulation, our methodology yields up to 35% and 58% improvement in noise figure and gain, respectively.     

一种基于HDTV信源集成解码芯片的RTOS的设计与实现

随着系统集成芯片（SOC）设计复杂度和上市时间等要求的提高，实时操作系统已成为SOC设计中的重要组成部分。HDTV信源集成解码芯片中的实时操作系统负责对进出芯片的数据进行管理，芯片上实现多个实时任务的同步和调度。本文介绍一个以较小内核实现的多任务实时操作系统Iota，它将总线的调度部分的转移到硬件实现，并针对解码芯片设计并实现了多任务混合调度算法。为提高系统的健壮性，Iota还具有一个简单的存储保护策略。     

HotSpot: a dynamic compact thermal model at the processor-architecture level

This paper describes a thermal-modeling approach that is easy to use and computationally efficient for modeling thermal effects and thermal-management techniques at the processor architecture level. Our approach is based on modeling thermal behavior of the microprocessor die and its package as a circuit of thermal resistances and capacitances that correspond to functional blocks at the architecture level. This yields a simple compact model, yet heat dissipation within all major functional blocks and the heat flow among blocks and through the package are accounted for. The model is parameterized, boundary- and initial-conditions independent, and is derived by a structure assembly approach. The architecture community has demonstrated growing interest in thermal management, but currently lacks a way to model on-chip temperatures in a tractable way. Our model can be used for initial exploration of the design space at the architecture level. The model can easily be integrated into popular power/performance simulators, can be used to determine how thermal stress is correlated to the architecture, and how architecture-level design decisions influence thermal behavior and related effects.     

A programmable thermal management interface circuit for PowerPC systems

A programmable thermal management interface circuit for PowerPC systems has been designed, implemented, and tested for the Integrated Thermal Management (ITEM) System [1]. Instead of worst-case design, the ITEM system approach is to target nominal power dissipation and have the system actively monitor its thermal activity and control cooling mechanisms to ensure operation within specification. Using a suitable combination of hardware and software, the interface design yields intricate control and optimal management with little system overhead and minimum hardware requirements, as well as provides the flexibility to support different management algorithms. This interface circuit was fabricated in the HP 0.5 μm single-poly 3-metal process through MOSIS.     

电力电子系统以热阻为基础的热设计探讨

随着半导体集成技术的演进,电力电子系统中的热管理问题已愈来愈受到重视。本文旨在探讨热管理在电力电子系统设计中日益重视的原因及所面对的挑战,文中提出电力电子系统巨观的热阻模式,并分别用桌上型计算机电源供应器、直直流变换器模块等作实例解说,最后从热阻的观点分享实务经验,并说明克服挑战需具备的条件。     

电力电子系统以热阻为基础的热设计探讨

随着半导体集成技术的演进,电力电子系统中的热管理问题已愈来愈受到重视。本文旨在探讨热管理在电力电子系统设计中日益重视的原因及所面对的挑战,文中提出电力电子系统巨观的热阻模式,并分别用桌上型计算机电源供应器、直直流变换器模块等作实例解说,最后从热阻的观点分享实务经验,并说明克服挑战需具备的条件。     

Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications

The nine papers in this special section are devoted to system-on-chip integration - its major challenges and implications for integrated circuit design.     

Application-Specific MPSoC Reliability Optimization

This paper presents modeling and estimation techniques permitting the temperature-aware optimization of application-specific multiprocessor system-on-chip (MPSoC) reliability. Technology scaling and increasing power densities make MPSoC lifetime reliability problems more severe. MPSoC reliability strongly depends on system-level MPSoC architecture, redundancy, and thermal profile during operation. We propose an efficient temperature-aware MPSoC reliability analysis and prediction technique that enables MPSoC reliability optimization via redundancy and temperature-aware design planning. Reliability, performance, and area are concurrently optimized. Simulation results indicate that the proposed approach has the potential to substantially improve MPSoC system mean time to failure with small area overhead.     

A new successive approximation architecture for low-power low-cost CMOS A/D converter

A new 6-bit 250 MS/s analog-to-digital converter (ADC) is proposed for low-power low-cost CMOS integrated systems. This design is based on an improved successive approximation ADC with a mixed-mode subtracter that minimizes the overall power consumption and system complexity. The experimental results indicate that this ADC works up to 250 MS/s with power consumption less than 30 mW at 3.3 V. Moreover, the operating voltage is scaled down to 0.8 V using a slight adjustment. The ADC occupies only 0.1 mm/sup 2/ with the TSMC 0.35-/spl mu/m single poly quadruple metal (SPQM) CMOS technology. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SoC) circuit designs.     

天基激光器的排热方案研究

天基激光器运行过程中产生的大量废热需要排散,采用传统的热泵、单相或两相流体排热回路以及消耗性冷却剂等热控技术会使整个热管理系统质量、体积或功耗过大。以系统的轻量化和紧凑性为指标,对辐射冷却-冰蓄冷组合排热方案用于天基激光器的可行性进行了研究,结果表明,该方案能满足激光器废热排放要求,可大大减轻热控系统的质量和体积,说明它在未来天基激光器热管理中具有相当的应用潜力。     

浅析电力通信综合网管系统设计

随着电力技术迅速的发展,通信网络、电力配置和应用日趋复杂,在这样的背景下,建立相应的电力通信综合网管系统显得尤为重要。文中简单介绍了通信综合网管系统的设计原则,分析了综合网管的功能目标与系统设计模式,从四个方面论述了综合网管系统各功能域的设计,包括故障管理功能、网络预警功能、维护管理功能以及性能管理功能设计。     

Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-μm CMOS process

A novel design of high-voltage-tolerant stimulus driver for epileptic seizure suppression with low power design and adaptive loading consideration is proposed in this work. The proposed design can deliver the required stimulus current within a specific range of loading impedance. Besides, this design in 0.18-μm low-voltage CMOS process can be operated with high supply voltage (V_CC) of 5–10 V without using the high-voltage transistors, and the process steps of high-voltage transistors can be reduced. The proposed design can be further integrated for an electronic epilepsy prosthetic system-on-chip.     

Design techniques for reducing the impact of component variations on narrow-band low noise amplifiers

Given the increasing demand for integrated wireless systems in system-on-chip technology, narrow-band low noise amplifier (LNA) designs must be robust against variations in device parameters and passive component values to improve manufacturing yield for high volume applications. In this paper, we develop two design techniques for reducing the impact of component variations on narrow-band LNA performance. The results demonstrate that by increasing the bandwidth of the narrow-band LNA and applying more conservative design constraints, we can mitigate the reliability implications of process variations on impedance matching, gain, and power consumption.     

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter, digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7×8 mm² and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.     

基于物联网的锂动力电池智能综合管理系统

锂动力电池是一种应用非水电解质溶液，并由锂合金或锂金属作为负极材料的电池，具有绿色环保、轻便、高能量密度、使用寿命长等特点。近年来，锂动力电池被广泛应用于电动工具、电动自行车等领域，并逐步应用到电动车辆与混合动力车领域。但是，原有的锂动力电池监控方法局限于电池组节点保护层面，无法保证将信息传输至监控平台。为提高电动汽车的电池智能综合管理系统的智能化与实时性水平，文中提出以物联网技术为基础，设计了一款基于物联网的锂动力电池智能综合管理系统，其以全面感知、获取锂动力电池的实时数据，并通过智能综合管理系统对相关数据的计算与分析，实现对锂动力电池的智能化控制。文中以构建物联网背景下的锂动力电池智能综合管理系统为目标，首先分析了锂动力电池智能综合管理系统的基本结构，然后从系统物理层、系统网络层、系统应用层等层面出发，研究了锂动力电池智能综合管理系统的相关设计。     

ATM业务量管理及其对ATM交换机设计的影响

ＡＴＭ网络允诺为各种通信业务在同一个通信网络中提供满足各自服务质量的要求的服务。为此，ＡＴＭ网络体系应能提供业务量管理（ｕｔａｆｆｉｃ ｍａｎａｇｅｍｅｎｔ）功能以支持网络业务千差万别的服务质量要求。本文首先阐述了ＡＴＭ论坛（ＡＴＭ Ｆｏｒｍ）中所定义的ＡＴＭ业务种类，它们各自的服务质量要求，以及为保证服务质量所应采用的管理策略。ＡＴＭ交换机是网络中的关键部件，其不同的设计思想对网络中不同业务服务     

Compact model development for a new nonvolatile memory cell architecture

To facilitate the development of system-on-chip designs, accurate models are required for each of the new elements being included. In this paper, a new model for a novel low power flash memory device, the top floating gate cell, which can be integrated into CMOS processes with minimal disruption to the standard process is described.     

电力信息系统综合安全管理

随着近年来与外界接口的增加,网上电力服务、三网融合、数据大集中,应用、内部各系统间的互联互通等需求的发展,电力系统的安全问题开始跨越网络出现。网络内外的恶意流量,特别是处于应用层的恶意流量,已经成为电力系统网络不可忽视的威胁来源。文中列举了电力信息系统现有安全管理方法存在的瓶颈和制约点,针对这些特点提出了将综合安全管理方法应用于电力信息系统的设计思路,并具体论述了综合安全管理平台的建立方式与技术支撑。