A novel technique to decouple electrical and thermal effects in SOA limitation of power LDMOSFET

This letter reports a novel technique to isolate thermal and electrical failure mechanisms in a power LDMOSFET device by deactivating the parasitic bipolar transistor while maintaining the MOS gate control. It is shown that the energy capability of the device remains constant as a function of the drain voltage in the event of a purely thermal failure, whereas the standard device shows a decrease in energy capability indicating electrothermal coupling. Nevertheless, the standard device energy capability is close to that obtained in the case of pure thermal failure, indicating that the thermal phenomenon dominates in determining the device failure and that electrical effects, though present, only minutely influence the device failure.     

Measurement of junction temperature of an AlGaAs/GaAsheterojunction bipolar transistor operating at large powerdensities

An electrical method to determine the junction temperature of a power bipolar transistor is presented. The success of this method does not rely on the constancy of thermal resistance over the wide range of operating temperatures. It is hence suitable for transistors operating at high power densities where conventional measurement techniques would not apply. Using this method, we establish that the junction temperature can be 40°C higher than the product of the low temperature thermal resistance and the power dissipation     

Thermalelectro-feedback model for multi-emitter finger power heterojunction bipolar transistor. Part I: Temperature profile

Poor thermal conductivity of GaAs, a self-heating phenomenon which results in the rapid rise of device temperature, is the major factor that limits and even degrades the electrical performance of GaAs-based heterojunction bipolar transistor (HBT) operated at high power densities. On the basis of this consideration, a numerical model is presented to study the interaction mechanism between the thermal and electrical behavior of AlGaAs/GaAs HBT with multiple-emitter fingers. The model mainly comprises a numerical model applicable for multi-finger HBT that solves the three-dimensional heat transfer equation. The device design parameters that influence the temperature profile and current distribution of the device are identified, and optimization concerning the device performance is made.     

Fully integrated gate drive supply Around Power switches

Main power switches such as metal oxide semiconductor field effect transistors or insulated gate bipolar transistors have reached very high performances from an electrical point of view. If their electrical characteristics are getting closer to physical limits, there is still a lot to do to improve their functionalities. The paper presents the monolithic integration of a gate drive power supply with the power switch to be driven. The operating principle is discussed to demonstrate that all needed components for this function can be integrated with the power switch. It is also demonstrated that the solution does not require any main power switch technological process modification-leading to a cost effective solution. Modeling and analysis comments are provided in order to clarify and to present operating principles and possible design constraints. Finally, the realization itself is presented. Prototypes are used to highlight the interest of such function.     

Second breakdown of vertical power MOSFET's

It is shown that a phenomenon of second breakdown similar to that in bipolar transistors can occur in vertical power MOSFET's. A model for the phenomenon of second breakdown involving the avalanche multiplication of the channel current, the parasitic bipolar transistor, and base resistance is proposed. After presenting the theory, this model is compared with experiments on four-terminal V-groove test devices in which the substrate can be accessed independently. Good agreement is achieved between calculated and measured boundaries of the safe operating area. The model should be applicable to DMOS devices as well.     

Thermal networks for electro-thermal analysis of power devices

This work presents a derivation of the equivalent thermal network associated to the distributed heat diffusion process which takes place in an electrical circuit. Precise definition of temperature and dissipated power density for the elementary electrical element are presented. It is shown that these definitions lead to an equivalent thermal network that preserves the physical properties of the original distributed phenomenon. Using these results an accurate electro-thermal network model of a power DMOS is derived.     

A General Photo-Electro-Thermal Theory for Light Emitting Diode (LED) Systems

The photometric, electrical, and thermal features of LED systems are highly dependent on one another. By considering all these factors together, it is possible to optimize the design of LED systems. This paper presents a general theory that links the photometric, electrical, and thermal behaviors of an LED system together. The theory shows that the thermal design is an indispensable part of the electrical circuit design and will strongly influence the peak luminous output of LED systems. It can be used to explain why the optimal operating power, at which maximum luminous flux is generated, may not occur at the rated power of the LEDs. This theory can be used to determine the optimal operating point for an LED system so that the maximum luminous flux can be achieved for a given thermal design. The general theory has been verified favorably by experiments using high-brightness LEDs.      

耗散功率与环境温度对功率VDMOS热阻的影响分析

运用电学测试法,以两款不同封装类型功率VDMOS为实验对象,考察了耗散功率和环境温度对器件稳态热阻值的影响。结果表明：器件热阻值不是一个恒定不变的常量,由于电流拥挤效应,材料导热系数等条件的改变,它会随耗散功率及环境温度的增大而增大。该研究加深了对功率器件热阻理论的认识,为功率VDMOS的热特性评估提供了可靠的依据。     

AlGaAs/GaAs heterojunction bipolar transistors for power applications: issues of thermal effect and reliability

AlGaAs/GaAs heterojunction bipolar transistor (HBT) has the advantages of superior switching speed, wide linearity, and high current handling capability. As a result, the device has gained popularity in designing power amplifiers for RF and microwave applications. However, the high power in the HBT, together with the poor thermal conductivity of GaAs, gives rise to significant thermal effect and reduced reliability in such a device. This paper presents an overview on the simulation, modeling, and reliability of AlGaAs/GaAs HBTs. Emphasis will be placed on the effects of thermal–electrical interacting behavior on the dc and ac performance of the HBT. The thermal-induced degradation process in the HBT will also be addressed and analyzed.     

Dynamics of power MOSFET switching under unclamped inductiveloading conditions

The parasitic bipolar transistor inherent in a vertical power DMOSFET structure can have a significant impact on its reliability. Unclamped Inductive Switching (UIS) tests were used to examine the reliability of DMOSFET's in extremely harsh switching conditions. The reliability of a power DMOSFET under UIS conditions is directly related to the amount of avalanche energy the device can survive. A number of DMOSFET structures were critically examined under UIS conditions to determine the impact of bipolar transistor parameters on device reliability. The UIS dynamics were studied based on the results obtained from an advanced mixed device and circuit simulator in which the internal carrier dynamics were evaluated under boundary conditions imposed by the circuit operation. It is shown that premature open base bipolar transistor breakdown can occur when the p-base sheet resistance is high. A device structure with a shallow self-aligned p⁺ region is shown to prevent the parasitic bipolar turn-on and avoid premature UIS breakdown without compromising the power-switching efficiency. The simulation results are shown to be in excellent agreement with the measured data under a wide range of inductive loading conditions     

A self-consistent model for temperature and current distribution in abrupt heterojunction bipolar transistors

The thermal behavior of abrupt heterojunction bipolar transistors (HBTs) has been studied by coupling the thermionic-field-emission injection mechanism at the emitter-base heterojunction with the thermal-electric feedback phenomenon. The exact quantum mechanical injection mechanism rather than the semiclassical WKB approximation is used in the present calculation to self-consistently calculate the thermionic and tunneling components of current. Moreover, the total current and temperature are self-consistently evaluated by testing the convergence on both current and temperature. The calculation shows correctly that the degree of the partitioning between the thermionic and tunneling components are bias- as well as temperature-dependent. It is shown that even a single emitter finger can have a highly nonuniform temperature and current distribution across it, leading to the current collapse phenomenon. At high power levels, this may give rise to a current collapse phenomenon similar to that observed for the multifinger HBTs.     

Thermal properties of very fast transistors

Recent predictions that thermal effects will limit future transistor speed improvement motivated an interest in predicting and measuring these effects. A mathematical model of the three-dimensional transient heat flow problem is presented which takes into account the physical structure of the device and the actual region of power dissipation. At any point within the device, the model predicts the time-dependent temperature response to a change in power dissipation. A new method of measuring the local time-dependent thermal behavior of small bipolar transistors is described and used to verify the model. It was found that the thermal spreading resistance becomes important in silicon transistors when the emitter stripe dimensions approach 1 µ. Furthermore, the thermal response is much slower than the electrical response. Also, it was confirmed that adjacent devices in integrated circuits are essentially thermally isolated as far as thermal spreading resistance is concerned.     

Base current reversal phenomenon in a CMOS compatible high gainn-p-n gated lateral bipolar transistor

Base current reversal phenomenon is newly observed in a CMOS compatible high gain n-p-n gated lateral bipolar transistor. We attribute this phenomenon to avalanche generation as verified experimentally and by two-dimensional device simulation. Detailed investigation reveals that: (i) the multiplication ratio increases exponentially with the collector voltage or equivalently the peak field at the surface collector corner; and (ii) the multiplication ratio is independent of not only the low level base-emitter forward biases applied but also the base width of the transistors fabricated by the same process. Design guideline for suppression of the base current reversal has been established such as to fully realize the potential of the gated lateral bipolar transistors, i.e., a very high current gain of 11,600 can be maintained as long as the power supply voltage is less than the critical value of 1.78 V. On the other hand, new application directly employing this phenomenon has been suggested. Comparisons between the base current reversal phenomenon in the gated lateral bipolar transistor and that in the vertical bipolar transistor have also been performed and significant differences between the two have been drawn and have been adequately explained     

Dislocation dynamics in heterojunction bipolar transistor under current induced thermal stress

Dislocation generation and multiplication in heterojunction bipolar transistors (HBTs) under electrical bias was studied using a finite element model. This model was developed to solve a physical viscoplastic solid mechanics problem using a time-dependent constitutive equation relating the dislocation dynamics to plastic deformation. The dislocations in HBTs are generated by the excessive stresses including thermal stress generated by the temperature change in the device during operation. It was found that the dislocation generation rate at the early stage and the stationary dislocation densities depend strongly on the current density.     

Emitter ballasting resistor design for, and current handlingcapability of AlGaAs/GaAs power heterojunction bipolar transistors

A systematic investigation of the emitter ballasting resistor for power heterojunction bipolar transistors (HBTs) is presented. The current handling capability of power HBTs is found to improve with ballasting resistance. An equation for the optimal ballasting resistance is presented, where the effects of thermal conductivity of the substrate material and the temperature coefficient of the ballasting resistor are taken into account. Current levels of 400 to 800 mA/mm of emitter periphery at case temperatures of 25 to -80°C for power AlGaAs/GaAs HBTs have been obtained using an on-chip lightly doped GaAs emitter ballasting resistor. Device temperature has been measured using both an infrared microradiometer and temperature-sensitive electrical parameters. Steady-state and transient thermal modeling are also performed. Although the measured temperature is spatially nonuniform, the modeling results show that such nonuniformities would occur for a uniform current distribution, as would be expected for an HBT with emitter ballasting resistors     

The effects of BJT self-heating on circuit behavior

This study demonstrates the circuit and device conditions under which self-heating can significantly affect bipolar junction transistor (BJT) circuit behavior. Simple quantitative measures are supplied that allow estimation of thermally induced errors in BJT small-signal parameters, based on knowledge of the transistor geometry and its Early voltage. It is shown that errors in output admittance and reverse transadmittance can be significant without much power dissipation, especially when the base and emitter driving impedances are small. Other small-signal parameters are less affected unless the power dissipation becomes significant. Thermal effects in large-signal DC analysis can be significant in precision analog circuits that depend on close transistor matching; such circuits can also exhibit long settling-time tails due to long thermal time constants. ECL (emitter-coupled logic) delay is shown to be insensitive to self-heating. These effects are demonstrated through simulations of a variety of circuits using versions of SPICE modified to include physics-based models for thermal impedance     

Fast thermal profiling of power semiconductor devices using Fourier techniques

Accurate prediction of temperature variation of power semiconductor devices in power electronic circuits is important to obtain optimum designs and estimate reliability levels. Temperature estimation of power electronic devices has generally been performed using transient thermal equivalent circuits. In the presence of varying load cycles, it has been typical to resort to a time-domain electrical simulation tool such as P-Spice or SABER to obtain a time series of the temperature profiles. However, for complex and periodic load cycles, time-series simulation is time consuming. In this paper, a fast Fourier analysis-based approach is presented for obtaining temperature profiles for power semiconductors. The model can be implemented readily into a spreadsheet or simple mathematical algebraic calculation software. The technique can be used for predicting lifetime and reliability level of power circuits easily. Details of the analytical approach and illustrative examples are presented in this paper.     

Power bipolar transistors with a fast recovery integrated diode

We have integrated a fast recovery diode in the structure of a power bipolar transistor. This integral diode is physically connected between the emitter and the collector of the transistor and can be used as a free-wheeling diode in power switches. Selective reduction of the minority carrier lifetime in the region of the diode was realized by Pt implantation in the diode area followed by an optimized thermal process that limits the lateral diffusion of the metal atoms. Using this metal doping a reduction by a factor of 10 of the reverse recovery charges of the integrated diode is obtained without affecting significantly the current carrying capability of the transistor     

Study of RF N LDMOS critical electrical parameter drifts after a thermal and electrical ageing in pulsed RF

An innovative reliability test bench dedicated to RF power devices is currently implemented. This bench allows to apply both electric and thermal stress for lifetime test under radar pulsed RF conditions. This paper presents the first investigation findings of critical electrical parameter degradations after thermal and electrical ageing. It shows that the tracking of a set of parameters (drain–source current, on-state resistance, threshold voltage, feedback capacitance and transconductance) can give insight into the hot carrier injection phenomenon for a RF n⁻ channel lateral DMOS (N⁻ LDMOS) working under pulsed conditions.     

New latchup mechanism in complementary bipolar power ICs triggered by backside die attach Glue

It is shown that in complementary bipolar power ICs latchup can be caused by a thyristor formed by the V-PNP power transistor at the frontside of the die and a Ag-filled glue die attach at the backside of the die (used to provide a good thermal contact between the die and the Cu-heatsink. The thyristor is triggered by saturation of the V-PNP power transistors or by forward biasing the backside diode between Ag-filled glue and p-type silicon. The effect is strongly temperature dependent. It can be eliminated by either leaving the backside floating or by applying backside metallization. Consequences for latchup qualification testing are discussed.