Recent results from the LHC inner triplet quadrupole developmentprogram at Fermilab

Fermilab, in collaboration With LBNL and BNL, is in the process of developing a focusing quadrupole for installation in the interaction region inner triplets of the LHC. This magnet is required to have an operating gradient of 215 T/m across a 70 mm coil bore, and operates in superfluid helium at 1.9 K. The design is based on a two layer cos (20) coil, mechanically supported by standalone steel collars. The collared coil assembly is surrounded by a iron yoke for flux return, and the assembly enclosed by a stainless steel shell. The development program has addressed mechanical, magnetic, quench protection, and thermal issues, through a series of model magnets constructed at Fermilab. This paper summarizes results from the recent model tests, and the status of the program     

New covering codes from an ADS-like construction

A covering code construction is presented. Using this construction it is shown that t[52,39]=3, t[36,21]=4, t[58,32]=7, K(32,2)/spl les/62/spl middot/2/sup 18/, and K(62,5)/spl les/31/spl middot/2/sup 37/, where t[n,k] is the minimum covering radius among all binary [n,k] codes and K(n,R) is the minimum cardinality of a binary code of length n and covering radius R. Four new linear codes found by computer search are also given. These include a [23,9]5 code, a [32,8]10 code, a [51,41]2 code, and a [45,20]8 code.     

Performance of polysilicon gate HfO/sub 2/ MOSFETs on [100] and [111] silicon substrates

Mobility dependence on Si substrate orientations was investigated for HfO/sub 2/ MOSFETs for the first time. High-temperature (600 /spl deg/C) forming gas (FG) annealing (HT-FGA) was applied on the devices on both [100] and [111] substrates to evaluate the mobility for optimal interfacial quality. Using HT-FGA, D/sub it/ of the [111] devices was reduced down below 1 /spl times/ 10/sup 12/ cm/sup -2/V/sup -1/. Similar to SiO/sub 2/ devices, NMOS mobility of the [111] devices was lower than that of the [100] devices at higher effective fields, while it was reversed for PMOSFETs.     

High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

We report investigations of Si face 4H-SiC MOSFETs with aluminum (Al) ion-implanted gate channels. High-quality SiO/sub 2/-SiC interfaces are obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion-implanted regions. A peak field-effect mobility of 170 cm/sup 2//V/spl middot/s is extracted from transistors with epitaxially grown channel region of doping 5/spl times/10/sup 15/ cm/sup -3/. Transistors with implanted gate channels with an Al concentration of 1/spl times/10/sup 17/ cm/sup -3/ exhibit peak field-effect mobility of 100 cm/sup 2//V/spl middot/s, while the mobility is 51 cm/sup 2//V/spl middot/s for an Al concentration of 5/spl times/10/sup 17/ cm/sup -3/. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.     

Sub-500/spl deg/C solid-phase epitaxy of ultra-abrupt p/sup +/-silicon elevated contacts and diodes

A well-controlled low-temperature process, demonstrated from 350/spl deg/C to 500/spl deg/C, has been developed for epitaxially growing elevated contacts and near-ideal diode junctions of Al-doped Si in contact windows to the Si substrate. A physical-vapor-deposited (PVD) amorphous silicon layer is converted to monocrystalline silicon selectively in the contact windows by using a PVD aluminum layer as a transport medium. This is a solid-phase-epitaxy (SPE) process by which the grown Si is Al-doped to at least 10/sup 18/ cm/sup -3/. Contact resistivity below 10/sup -7/ /spl Omega//spl middot/cm/sup 2/ is achieved to both p/sup -/ and p/sup +/ bulk-silicon regions. The elevated contacts have also been employed to fabricate p/sup +/-n diodes and p/sup +/-n-p bipolar transistors, the electrical characterization of which indicates a practically defect-free epitaxy at the interface.     

Results of 3-dimensional structural FE-modeling of the coilend-regions of the LHC main dipoles

The transition region between the straight part and the ends of the coils of the LHC model and prototype dipole magnets are often identified as the origin of training quenches. In order to study how the discontinuities in the material properties of these regions affect coil pre-stress and possibly gain more insight in the quench behavior, a program was set up at CERN to analyze by 3D-FEM these particular regions. The ACCEL team, who performed a similar analysis for the main quadrupoles of the Superconducting Supercollider SSC, is entrusted with this program. In this paper we report on the results of 3D-modeling and analysis of the coil return end region, including the complete coil mass, of a 1-m single bore model magnet. This magnet represents all relevant features of the “two-in-one” LHC main dipole design concerning the winding configuration, the collar pack, the yoke, and the outer shell representing the He-vessel. The transition region between coil ends and straight section is modeled by slicing the magnet down to individual collar laminations per elementary level. The two-layer winding pack is represented with all individual conductor blocks, wedges, end spacers, and the interlayer spacer. Results will be presented for load cases with pre-stress after assembly at room temperature, after cool-down, and under operation at maximum current. Critical stress locations were identified in the transition into the pole free section of the magnet and in the bent part. Shimming of the coils, as well as impact from material choices and suitable alternatives are discussed     

Measuring thermal and mechanical stresses on optical fiber in a DC module using fiber Bragg gratings

Fiber Bragg gratings (FBGs) can be used as sensors to monitor stress and test temperature during the processing and handling of optical fiber. As the FBG experiences a combination of mechanical and thermal loading, the return Bragg wavelength will shift proportionately to the magnitude of the load. This paper discusses the use of these sensors in quantifying induced stress on fiber during the packaging of a dispersion-compensating module (DCM) and the ensuing environmental exposure. There are two potential fiber-failure modes for fiber wound in DCMs, namely microbend-induced attenuation and fiber failure from fatigue. The ability to quantify fiber stress provides a useful feedback tool in the design phase of these modules that can aid in reducing the risk of mechanical and optical failure modes. A practical characterization process was developed to decouple thermal and stress effects on FBGs based on results from current literature and from this study. Uncoated Bragg sensors were found to respond linearly between -40 to 80/spl deg/C. Gratings with a protective polymer recoat departed from the linear behavior of the uncoated gratings below -5/spl deg/C. It was determined that the recoat material places less than 25 MPa (3.6 klbf/in/sup 2/) of axial compression on the fiber at -40/spl deg/C. Four gratings with different Bragg wavelengths were spliced into 10 km of fiber and wound into a DCM. The wind-induced stress on all four gratings quickly relaxed. The module was then thermal cycled between -40 and +75/spl deg/C. The overall stress on each grating was acceptably low for reliability purposes. The maximum stress of 17 MPa (2.5 klbf/in/sup 2/) was observed at the lowest temperature.     

Development of liquid cooling techniques for flip chip ball grid array packages with High Heat flux dissipations

In this paper, development of single-phase liquid cooling techniques for flip chip ball grid array packages (FBGAs) with high flux heat dissipations is reported. Two thermal test chips with different footprints, 12 mm/spl times/ 12 mm and 10 mm /spl times/10 mm, respectively, were used for high heat flux characterizations. A liquid-cooled aluminum heat sink with an area of 15 mm (L) /spl times/12.2 mm (W) populated by microchannels was designed and fabricated. The microchannel heat sink was assembled onto the chip, using a thermal interface material to reduce the contact thermal resistance at the interface. A variable speed pump was used to provide the pressure head for the liquid cooling loop. The measured thermal resistance results ranged from 0.44 to 0.32/spl deg/C/W for the 12-mm chip case and from 0.59 to 0.44/spl deg/C/W for the 10-mm chip case, both under flowrates ranging from 1.67/spl times/10/sup -6/ m/sup 3//s to 1.67/spl times/10/sup -5/ m/sup 3//s. An analytical model of the flow and heat transfer in microchannel heat sinks is also presented. Computational predictions agree with the measurements for pressure drop within 15% and thermal resistances within 6%. The analytical results indicate that thermal interface resistance becomes a key limitation to maximizing heat removal rate from electronic packages.     

Precise, wide-range approximations to arc sine function suitable for analog implementation in sensors and instrumentation applications

This paper presents four newly developed algebraic approximations of the inverse sine function, defined for the full [-1,+1] input range. These approximations contain few terms, and have numerical coefficients with low number of significant figures. The maximum absolute errors of the formulas range between 4.07/spl times/10/sup -4%/ and 5.64/spl times/10/sup -2%/ of the maximum value (i.e., /spl pi//2) returned by the arc sine function. These approximations are particularly suited to the determination of mechanical and electrical angles in sensors and instrumentation applications. One of the proposed expressions has been implemented using analog electronic circuitry. The converter built was successfully tested and characterized using both a PC-based test rig, and a commercial resolver. The theory, computer simulation and some experimental results are given.     

Full characterization of packaged Er-Yb-codoped phosphate glass waveguides

We present a procedure for the characterization of packaged Er-Yb-codoped phosphate glass waveguides. The procedure is based on precise measurements of the output optical powers when the waveguide is diode-laser pumped at 980 nm. The dependence of these optical powers on the input pump power is then fitted to the results from a numerical model that describes in detail the propagation of the optical powers inside the waveguide. The best fit is obtained for the following parameters: the signal wavelength scattering losses are /spl alpha/(1534)=8.3/spl times/10/sup -2/ dB/cm, the Yb/sup 3+/ absorption and emission cross sections (/spl ap/980 nm) are 5.4/spl times/10/sup -25/ m/sup 2/ and 7.0/spl times/10/sup -25/ m/sup 2/, the Er/sup 3+/ absorption and emission cross sections (/spl ap/980 nm) are 1.6/spl times/10/sup -25/ m/sup 2/ and 1.2/spl times/10/sup -25/ m/sup 2/, the Yb/sup 3+/--Er/sup 3+/ energy-transfer coefficient is 1.8/spl times/10/sup -23/ m/sup 3//s and the cooperative-upconversion coefficient is 8/spl times/10/sup -25/ m/sup 3//s. An approximate method is introduced that allows the determination of the absorption and emission cross section distributions for the erbium /sup 4/I/sub 13/2//spl hArr//sup 4/I/sub 15/2/ transition from the amplified spontaneous emission power spectrum.     

Hybrid neural network modeling of anion exchange at the interfaces of mixed anion III-V heterostructures grown by molecular beam epitaxy

A hybrid neural network model is constructed by characterizing the growth of GaAs/sub 1-y/P/sub y/-GaAs superlattices (SLs) grown on [001] GaAs substrates by molecular beam epitaxy. These heterostructures are formed by the P/sub 2/ exposure of an As-stabilized GaAs surface, and ex situ high-resolution X-ray diffraction (HRXRD) is performed to determine the phosphorus composition at the interfaces. A first-order kinetic model is then developed to describe the mechanisms of anion exchange, surface desorption, and diffusion. A semi-empirical hybrid neural network is used to estimate the parameters of the kinetic model and analyze the microscopic processes occurring at the interfaces of the mixed anion III-V heterostructures. The phosphorus diffusion process in GaAs is estimated to have a diffusion coefficient of D=1.4/spl times/10/sup -14/exp(-0.11 eV/k/sub B/T/sub s/) cm/sup 2//spl middot/s/sup -1/ for samples with P/sub As4/=4/spl times/10/sup -6/ torr and exhibits enhanced phosphorus intermixing for samples with lower As-stabilizing fluxes.     

Top-gate TFTs using 13.56 MHz PECVD microcrystalline silicon

Top-gate thin-film transistors (TFTs) with microcrystalline silicon (/spl mu/c-Si) channel layers deposited using standard 13.56 MHz plasma-enhanced chemical vapor deposition were fabricated at a maximum processing temperature of 250/spl deg/C. The TFTs employ amorphous silicon nitride (a-SiN) as the gate dielectric layer. The 80-nm-thick /spl mu/c-Si channel layer showed a dark conductivity of the order of 10/sup -7/ S/cm and a crystalline volume fraction of over 80%. The /spl mu/c-Si TFTs showed a field effect mobility of 0.85 cm/sup 2//V/spl middot/s, a threshold voltage of 4.8 V, a subthreshold slope of 1 V/dec, and an ON/OFF current ratio of /spl sim/10/sup 7/. More importantly, the TFTs were very stable under gate bias stress, offering promise for organic light-emitting display (OLED) applications.     

Development of a hybrid helical microwiggler with four poles per period

A compact strong test hybrid helical microwiggler has been designed and developed with ten periods, each with length 10 mm and four poles, and gap diameter of 5 mm. One period is constructed with four segments. Each segment has a thickness of 2.5 mm and consists of pentagonal permanent magnets and permendur poles. Each segment is stacked along the wiggler axis and is rotated by an angle of 90/spl deg/ to the adjacent segment. The outer width is only 72 mm. The wiggler is divided into two sections where two kinds of permanent magnet - one with apex angle of 90/spl deg/ and one with 120/spl deg/ - were installed in order to find out the effect of geometrical size for the field. Peak fields of 0.360 and 0.381 T were achieved with small rms variations of about 1.1% and 0.6%, respectively, depending on the geometrical size of the permanent magnet.     

A dependency of quantum efficiency of silicon CMOS n/sup +/pp/sup +/ LEDs on current density

A dependency of quantum efficiency of nn/sup +/pp/sup +/ silicon complementary metal-oxide-semiconductor integrated light-emitting devices on the current density through the active device areas is demonstrated. It was observed that an increase in current density from 1.6/spl times/10/sup +2/ to 2.2/spl times/10/sup +4/ A/spl middot/cm/sup -2/ through the active regions of silicon n/sup +/pp/sup +/ light-emitting diodes results in an increase in the external quantum efficiency from 1.6/spl times/10/sup -7/ to 5.8/spl times/10/sup -6/ (approximately two orders of magnitude). The light intensity correspondingly increase from 10/sup -6/ to 10/sup -1/ W/spl middot/cm/sup -2//spl middot/mA (approximately five orders of magnitude). In our study, the highest efficiency device operate in the p-n junction reverse bias avalanche mode and utilize current density increase by means of vertical and lateral electrical field confinement at a wedge-shaped n/sup +/ tip placed in a region of lower doping density and opposite highly conductive p/sup +/ regions.     

A thyristor-based photoreceiver based on the dual-channel double-heterostructure optoelectronic switch

A new approach to photoreceiver design is described based on the functionality of an optoelectronic thyristor. The receiver eliminates the transimpedance amplifier and the decision circuit by utilizing the internal gain of the thyristor and its nonlinear thresholding property. The sensitivity is determined by the shot noise on the input signal to be 360 photons per bit at a bit-error rate of 10/sup -9/. The speed of the photoreceiver is determined by the switching times of the thyristor. An output voltage signal from 0 to 1.5 V is obtained with switch on and off times of 12.5 ps and input photocurrent densities of 10/sup 4/ A/cm/sup 2/. The switch off time is equally as fast as the switch on due to the absence of stored charge in the modulation doped structure. The key to the high speed is the utilization of the third and fourth terminal contacts to the thyristor and the integration of the biasing transistors, which control the switching currents. An input optical signal of 0.5 mW will achieve this bandwidth in a device size of 0.2 /spl mu/m/spl times/12.5 /spl mu/m.     

Nitride-based LEDs with an SPS tunneling contact Layer and an ITO transparent contact

The indium-tin-oxide [ITO(80 nm)] and Ni(5 nm)-Au(10 nm) films were separately deposited on glass substrates, p-GaN layers, n/sup +/-InGaN-GaN short-period-superlattice (SPS) structures, and nitride-based light-emitting diodes (LEDs). It was found that ITO on n/sup +/-SPS structure could provide us an extremely high transparency (i.e., 93.2% at 465 nm) and also a reasonably small specific contact resistance of 1.6/spl times/10/sup -3//spl Omega//spl middot/cm/sup 2/. Although the forward voltage which corresponds to 20-mA operating current for LED with ITO on n/sup +/-SPS upper contact was slightly higher than that of the LED with Ni-Au on n/sup +/-SPS upper contact, a 30% higher output intensity could still be achieved by using ITO on n/sup +/-SPS upper contact. Moreover, the output power of packaged LED with ITO was about twice as large as that of the other conventional Ni-Au LEDs.     

Stable polycrystalline silicon TFT with MICC

We studied the bias-induced changes in the performance of the poly-Si thin-film transistor (TFT) by metal-induced crystallization of amorphous silicon through a cap layer (MICC) poly-Si. The p-channel poly-Si TFT exhibited a field-effect mobility of 101 cm/sup 2//V/spl middot/s and a minimum leakage current of <1.0/spl times/10/sup -12/ A//spl mu/m at V/sub ds/=-10 V. The MICC poly-Si TFT performance changes little by either gate or hot-carrier bias stress. The better stability appears to be due to the smooth surface of MICC poly-Si, which is /spl sim/2 nm that is much smaller than that (13 nm) of a laser-annealed poly-Si.     

GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition

For the first time, a III-V compound semiconductor MOSFET with the gate dielectric grown by atomic layer deposition (ALD) is demonstrated. The novel application of the ALD process on III-V compound semiconductors affords tremendous functionality and opportunity by enabling the formation of high-quality gate oxides and passivation layers on III-V compound semiconductor devices. A 0.65-/spl mu/m gate-length depletion-mode n-channel GaAs MOSFET with an Al/sub 2/O/sub 3/ gate oxide thickness of 160 /spl Aring/ shows a gate leakage current density less than 10/sup -4/ A/cm/sup 2/ and a maximum transconductance of 130 mS/mm, with negligible drain current drift and hysteresis. A short-circuit current-gain cut-off frequency f/sub T/ of 14.0 GHz and a maximum oscillation frequency f/sub max/ of 25.2 GHz have been achieved from a 0.65-/spl mu/m gate-length device.     

A resonant tunneling quantum-dot infrared photodetector

A novel device-resonant tunneling quantum-dot infrared photodetector-has been investigated theoretically and experimentally. In this device, the transport of dark current and photocurrent are separated by the incorporation of a double barrier resonant tunnel heterostructure with each quantum-dot layer of the device. The devices with In/sub 0.4/Ga/sub 0.6/As-GaAs quantum dots are grown by molecular beam epitaxy. We have characterized devices designed for /spl sim/6 /spl mu/m response, and the devices also exhibit a strong photoresponse peak at /spl sim/17 /spl mu/m at 300 K due to transitions from the dot excited states. The dark currents in the tunnel devices are almost two orders of magnitude smaller than those in conventional devices. Measured values of J/sub dark/ are 1.6/spl times/10/sup -8/ A/cm/sup 2/ at 80 K and 1.55 A/cm/sup 2/ at 300 K for 1-V applied bias. Measured values of peak responsivity and specific detectivity D/sup */ are 0.063 A/W and 2.4/spl times/10/sup 10/ cm/spl middot/Hz/sup 1/2//W, respectively, under a bias of 2 V, at 80 K for the 6-/spl mu/m response. For the 17-/spl mu/m response, the measured values of peak responsivity and detectivity at 300 K are 0.032 A/W and 8.6/spl times/10/sup 6/ cm/spl middot/Hz/sup 1/2//W under 1 V bias.