Technology and design challenges of MOS VLSI

The past decade of MOS technology has been characterized by the scaling of Si-gate LOCOS NMOS to ever smaller geometries. However, NMOS circuits with 1 /spl mu/m geometries will not be achieved by continued direct scaling of this structure. Major changes will be required in the 1-2 /spl mu/m range in terms of: 1) process and structure enhancements that will be required to realize the performance advantages predicted by scaling, and 2) new physical phenomena that will become important in determining MOSFET behavior. The 1-2 /spl mu/m range of NMOS technology is referred to as the `1.25 /spl mu/m discontinuity'. Both aspects of this discontinuity are explored, and some projections for MOS are made for the next decade.     

Limitations and challenges of multigigabit DRAM chip design

This paper describes the limitations and challenges involved in designing gigabit DRAM chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage circuits. The key results obtained are as follows. 1) For formation of a MOSFET shallow junction, which suppresses threshold voltage (V_T) variation and offset voltage of sense amplifiers, reduction in ion-implantation energy and process temperature is essential. Also, the keys in terms of area, speed, stable cell operation, and ease of fabrication are use of low-resistivity multilevel metal wiring and high permittivity materials and three-dimensional memory cells to reduce a difference in height between the memory cell array and the surrounding peripheral circuits. 2) For creation of a high speed, the keys are memory-subsystem technology such as pipeline operation, wide-bit I/O, low-voltage interfaces, and high-density packaging. Embedded DRAM further enhances the speed and throughput by using massively parallel processing of signals on a large number of data-lines and reducing internal bus capacitances. 3) For power reduction, the key continues to be reduction of the data-line dissipating charge through both partial activation of multidivided data-lines and lowering of the data-line voltage. Ultralow-voltage operation, essential to drastic power reduction, can be achieved by subthreshold-current reduction circuits such as source-gate backbiasing, multi-V_T, dynamic V_T, and node-boosting schemes     

混合模式与深亚微米设计面临的新挑战

基于硅的VLSI设计和制造技术在取得极大进展的同时面临纳米新材料新工艺的挑战,世界各大公司相继开发成功纳米晶体管和纳米器件制造工艺.可以说,模拟电路的设计和制造在电子学领域起着举足轻重的作用,它是大系统前端和后端信号处理和转换的关键部件.     

Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system

The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process, from system specifications to integrated circuit layout, is carried out with the aid of specialized computer programs for the analysis, synthesis, and optimization at each design level: the filter network, the architecture, and the circuit layout. These CAD tools support a top-down custom design methodology based on bit-serial architectures and standard cells. A customized architecture is constructed which is integrated using a 5-/spl mu/m CMOS cell library. The results are compared with a fully manual design and demonstrate the power of architecture based computer-aided design methodologies for VLSI filtering. By combining both synthesis and optimization aids at each design level it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput, and moderate power consumption.     

SoC技术现状及其挑战

当前,在微电子及其应用领域正在发生一场前所未有的变革,这场变革是由片上系统（SoC）技术研究应用和发展引起的。从技术层面看,SoC技术是超大规模集成电路发展的必然趋势和主流,它以超深亚微米VDSM（Very Deep Submicron）工艺和知识产权IP核复用技术为支撑。     

VLSI technology in China

Very-large-scale integration (VLSI) technology applications, developments, and markets in China are discussed. It is suggested that VLSI technology is gaining momentum in China, especially in the area of application specific integrated circuits (ASICs) development. The key issues in ASIC design are outlined, and research and development in microelectronics for telecommunications is described     

MOS technology for VLSI

The scaling laws for MOS transistors are reviewed and the optimum performance predicted for both n-channel and p-channel devices are discussed. The physical and technological limitations for MOS VLSI are then described and some important technological challenges such as the implementation of new isolation techniques are pointed out. The mobility degragation effect due to velocity saturation is explained and illustrated by experimental data. The various limitations to the maximum operating voltage of scaleg devices are discussed. Finally, some considerations about speed and power consumption of scaled technologies are made.     

VLSI technology and techniques for telecommunications

The rapidly increasing complexity of telecommunication systems has created a growing need for both standard and custom vlsi devices. The recently standardized Sonet, sdh and atm networks are areas where circuit integration is especially essential in order to make implementation of these networks practical. Telecommspecific vlsi devices present interesting challenges to the designer. This paper analyzes some of the requirements for integrated circuits that are frequently encountered or are unique to telecommunications, and suggests approaches to dealing with them.     

Computer-aided design of VLSI circuits

With the rapid evolution of integrated circuit (IC) technology to larger and more complex circuits, new approaches are needed for the design and verification of these very-large-scale integrated (VLSI) circuits. A large number of design methods are currently in use. However, the evolution of these computer aids has occurred in an ad hoc manner. In most cases, computer programs have been written to solve specific problems as they have exist and no truly integrated computer-aided desisn (CAD) systems exist for the design of IC's. A structured approach both to circuit desisn and to circuit verification, as well as the development of integrated design systems, is necessary to produce cost-effective error-free VLSI circuits. This paper presents a review of the CAD techniques which have been used in the design of IC's, as well as a number of design methods to which the application of computer aids has proven most successful. The successful application of design-aids to VLSI circuits requites an evolution from these techniques and design methods.     

Man-computer graphics for computer-aided design

This paper reviews the history, concepts, state-of-the-art, and future directions of the use of man-computer graphics for computer-aided design. Computer-aided design is based on a real-time graphical dialogue between the man and the computer in which the man draws on a display by means of a "light pen" or other input device. The computer "understands" the picture, makes calculations based on it, and presents the results pictorially to the user for his approval or revision. This man-computer graphical conversation has been made possible by recent advances in the speed of the digital computer, time-sharing programming, computer-driven display technology, and graphical input devices. The light pen is the most commonly used graphical input device, but keyboards, joysticks, flat matrix arrays, and other devices are also used. The programming state-of-the-art is a limiting factor in the implementatation of graphical computer-aided design; much work remains to be done in systems programming, efficient time sharing, list structure concepts, file organization, and memory protection. A number of experimental equipment configurations in use in various laboratories are cited and the hardware state-of-the-art is reviewed. Several experimental and production applications of computer-aided design evolved in a large aircraft company are described and illustrated, by display photographs. These applications relate to structural analysis, dynamics, information retrieval, accounting, and numerical control tape preparation. For the future, advances are required in improved man-computer communication, techniques to permit the operation of displays at great distances from the central computer, and methods of inputting existing drawings into the computer in a meaningful form.     

VLSI: linking design and manufacturing

A set of computer-aided design (CAD) tools that predict the effects of various manufacturing steps along with the chip's internal dimensions is described. Called the Process Engineer's Workbench, the system predicts the chip's characteristics, their statistical distribution, and the manufacturing yield likely from any one fabrication process. The tools are even sensitive to the small random variations that increase in significance as devices shrink in size. Workbench can be used to compare its programs' predictions and those of other software tools with actual measurements of devices and processes. Some existing CAD tools are reviewed to highlight the Workbench's advantages, and the features of the latter are examined. Written in C language for a Digital Equipment VAXstation, Workbench was designed to be portable and runs on several other popular workstations. It contains two basic libraries, namely, one of device models, the other of process step models     

Semistate theory and analog VLSI design

Semistate theory as applied to electronic circuits is reviewed in a tutorial fashion. The resulting theory is applied to the design of linear VLSI circuits using an admittance framework for which the main components are MOS capacitors, differential pairs and current mirrors. The results are extended to nonlinear designs through the use of CMOS multipliers.     

Quadruple-well CMOS for VLSI technology

A novel process has been developed to fabricate high-density CMOS with four wells. These wells are self aligned to increase packing density. Two of them are relatively deep wells used to optimize both n- and p-channel active devices. The other two are shallow wells under field oxide to form channel stops for both device types. The channel stops provide rigorous isolation among similar devices and between the devices of the opposite polarity. Subthreshold leakage currents in isolation regions are <0.05 pA/µm when devices are biased at <16.5 V. The channel stops also suppress lateral parasitic bipolar action. To reduce the vertical bipolar gain, a new process technique employing a double-retrograde well and transient annealing has been established. For the CMOS structure with 2-µm p⁺-to-p-well spacing, we have eliminated latchup by suppressing the beta product to below unity. Moreover, the quadruple-well approach has produced active n- and p-channel FET's with excellent characteristics such as low threshold voltage (∼±0.5 V), low subthreshold slope (≲95 mV/dec), low contact resistivity (∼10^-7Ω-cm²), and high channel mobility (620 and 210 cm²/V . s).     

VLSI design using Apple MacIntosh

VLSI design has caused a revolution in microminiaturization. The design process requires construction of stick diagrams for the digital circuit to be designed. These diagrams are prepared using different colored layers. The color graphics and the color monitors make the overall system quite expensive. The object of this article is to show how an inexpensive personal computer like the Apple MacIntosh can be used for preparing VLSI stick diagrams. The Apple MacIntosh's capabilities include translation, mirroring, detail work and hatching; which are indispensible in the construction of stick diagrams. The stick diagrams for a few examples such as serial adder, half adder, adder/subtractor and generalized pipeline array cell have been worked out. It is hoped that this paper will aid in making VLSI design easier on less expensive and easily obtainable personal computers.     

Limitations in solid-state technology

In a field in which success is a matter of record some constructive criticism is in order to spur even greater and more meaningful progress. In this vein the present article highlights shortcomings and limitations in the burgeoning area of solid-state technology. One of the main problems is that practice so often outdistances fundamental theory and understanding. Thus it is important that we be able to predict the growth and changes in the technology, but unfortunately our techniques of analysis, simulation, and measurement are inadequate and the number of theoretical limits pitifully small. Undoubtedly, more effort is essential.     

VLSI technology for telecommunication ICs

The majority of integrated circuits used in telecommunication applications involves a mix of analog and digital functions. Of the available silicon integrated circuit technologies NMOS, CMOS, and I/SUP 2/L/bipolar appear to be the most suitable for these applications since they can provide low power operation as well as high functional density analog and digital circuits on the same chip. The author reviews the requirements for telecommunications VLSI products, and discusses the choice of suitable IC technologies and the future status of these technologies.