基于Verilog HDL的微处理器ALU运算流水线设计

本文使用硬件描述语言VerilogHDL设计了一个ALU运算流水线,包括接口、FIFO模块、ALU模块和测试环境等,有助于提高微处理器的运算效率,为通过先进的描述手段设计微处理器打下良好的基础。     

基于资源共享的ALU设计

文章结合ALU设计,提出了基于等价变换的资源共享设计方法,在分析了ALU功能的基础上,给出了一个资源共享型ALU设计实例,与基于指令功能设计方法相比,资源共享设计方法在节省资源方面有独到的优势。该设计方法不仅适用于基于HDL描述的现代设计方法,而且也适用于传统的原理图设计方法。     

三端口64位处理器的VLSI设计

引入多端口处理器的概念并介绍三端口64位ALU及其旋转器的设计方法。为了提高处理器的工作效率,在ALU的每个输入端口设置适当容量的RAM是一种新的尝试。文中介绍了ALU端口RAM寄存器及其管理电路的设计方法。为了适应Windows环境中的多媒体数据的地址分级管理,本文提出“整地址”概念,并相应定义了qword地址和byte地址。文中也介绍了基于分级管理概念的地址发生器的设计方法以及如何使用两个地址发生器管理四种不同地址的设计方法。模块化、总线化结构是本设计的另一显著特点。     

基于FPGA的32位ALU软核设计

介绍了一种基于可编程逻辑器件FPGA和硬件描述语言VHDL的32位ALU的设计方法。该ALU采取层次化设计方法,由控制模块、逻辑模块、加减法模块、乘法模块和除法模块组成,能实现32位有符号数和无符号数的加减乘除运算,另外还能实现9种逻辑运算、6种移位运算以及高低字节内容互换。该ALU在QuartusII软件环境下进行了功能仿真, 通过验证表明,所设计的ALU完全正确,可供直接调用。     

基于图聚集算法的寄存器传输级ALU工艺映射算法

给出了寄存器传输级工艺映射(RTLM)算法,该方法支持使用高层次综合和设计再利用的现代VLSI设计方法学,允许复杂的RT级组件,尤其是算术逻辑单元(ALU)在设计中重用.首先提出了ALU的工艺映射问题,给出了源组件和目标组件以及标准组件的定义,在此基础上通过表格的方式给出映射规则的描述.映射算法套用一定的映射规则用目标ALU组件来实现源ALU组件.采用一种基于分支估界法的图聚集算法,用该算法不仅可以产生面积最优的,而且还可以产生延时最优的设计.针对不同库的实验结果证明该算法对于规则结构的数据通路特别有效.     

基于功能复用的高性能ALU设计

算术逻辑单元(ALU)是处理器中不可或缺的重要部分,可以进行两输入逻辑和加减法运算.设计了一款通用数字信号处理器中使用的高性能ALU.提出了一种高效的逻辑与算术运算复用的电路结构,提高复用度的同时,减少了ALU的面积.并提出一种融合进位选择和超前进位加法器结构的优化进位链设计,该进位链可以提高加法器的速度,并同时支持数字信号处理器的双16位运算.     

ALU运算器网络虚拟实验平台的设计与实现

介绍了开发ALU运算器网络虚拟实验平台所需要使用的软件、设计理念以及实现方法,对设计过程中面临的难点问题提出了详细的解决方案。     

基于图聚集算法的寄存器传输级ALU工艺映射算法

给出了寄存器传输级工艺映射(RTLM)算法,该方法支持使用高层次综合和设计再利用的现代VLSI设计方法学,允许复杂的RT级组件,尤其是算术逻辑单元(ALU)在设计中重用.首先提出了ALU的工艺映射问题,给出了源组件和目标组件以及标准组件的定义,在此基础上通过表格的方式给出映射规则的描述.映射算法套用一定的映射规则用目标ALU组件来实现源ALU组件.采用一种基于分支估界法的图聚集算法,用该算法不仅可以产生面积最优的,而且还可以产生延时最优的设计.针对不同库的实验结果证明该算法对于规则结构的数据通路特别有效.     

一种基于ALU运算单元的译码分配电路设计

本文介绍了一种基于ALU运算单元的译码器分配电路硬件设计,利用verilog硬件描述语言实现整体设计,并利用仿真编译工具对硬件功能进行验证.该译码分配电路实现了对ALU指令行进行逻辑解析,译成各个控制字,控制ALU指令的执行.     

基于FPGA的32位ALU的设计与实现

针对FPGA运算速度快,设计灵活的特点,提出了一种新颖的利用可编程逻辑器件FP-GA和硬件描述语言VHDL实现的功能齐全的32位ALU的方法.该ALU具备4种算术运算,9种逻辑运算,4种移位运算以及比较、求补、奇偶校验等共20种运算.采用层次化设计,给出了ALU的主要子模块,各模块均占用了较少的逻辑资源（LE）,实现了节省资源与速度提升.通过QuartusⅡ9.1进行编译,Modelsim6.5SE进行仿真,仿真结果与预期结果一致,将设计下载到Altera公司的EP2C35F484C6 FPGA中进行验证,证实了设计的可行性.实验结果表明,采用基于FPGA技术设计运算器灵活易修改,提高了设计效率.     

Carry checking/parity prediction adders and ALUs

In this paper, we present efficient self-checking implementations valid for all existing adder and arithmetic and logic unit (ALU) schemes (e.g., ripple carry, carry lookahead, skip carry schemes). Among all the known self-checking adder and ALU designs, the parity prediction scheme has the advantage that it requires the minimum hardware overhead for the adder/ALU and the minimum hardware overhead for the other data-path blocks. It also has the advantage to be compatible with memory systems checked by parity codes. The drawback of this scheme is that it is not fault secure for single faults. The scheme proposed in this work has all the advantages of the parity prediction scheme. In addition, the new scheme is totally self-checking for single faults. Thus, the new scheme is substantially better than any other known solution.     

与或结构算术逻辑单元的优化设计

对传统与或结构的 ALU进行分析并改进 ,并提出一种新结构的 ALU。它具有两级流水线结构 ,可以执行 2 0条指令 ,具有更为有效的 P和 G的函数发生器 ,并且减少了控制端的数目 ,以降低译码电路的规模 ,有利于控制整个系统的面积和功耗。     

Design of CNTFET-based 2-bit ternary ALU for nanoelectronics

This article presents a hardware-efficient design of 2-bit ternary arithmetic logic unit (ALU) using carbon nanotube field-effect transistors (CNTFETs) for nanoelectronics. The proposed structure introduces a ternary adder–subtractor functional module to optimise ALU architecture. The full adder–subtractor (FAS) cell uses nearly 72% less transistors than conventional architecture, which contains separate ternary cells for addition as well as subtraction. The presented ALU also minimises ternary function expressions with utilisation of binary gates for optimisation at the circuit level, thus attaining a simple design. Hspice simulations results demonstrate that the ALU ternary circuits achieve great improvement in terms of power delay product with respect to their CMOS counterpart at 32 nm.     

Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design andscaling trends

In this paper, we present: 1) design of a single-rail energy-efficient 64-b Han-Carlson ALU, operating at 482 ps in 1.5 V, 0.18-μm bulk CMOS; 2) direct port of this ALU to 0.18-μm partially depleted SOI process; 3) SOI-optimal redesign of the ALU using a novel deep-stack quaternary-tree architecture; 4) margining for max-delay pushout due to reverse body bias in SOI designs; and 5) performance scaling trends of the ALU designs in 0.13-μm generation. We show that a direct port of the Han-Carlson ALU to 0.18-μm SOI offers 14% performance improvement after margining. A redesign of the ALU, using an SOI-favored deep-stack architecture improves the margined speedup to 19%. A 10% margin was required for the SOI designs, to account for reverse body-bias-induced max-delay pushout. Preconditioning the intermediate stack nodes in the dynamic ALU designs reduced this margin to 2%. Scaling the ALUs to 0.13-μm generation reduces the overall SOI speedup for both architectures to 9% and 16%, respectively, confirming the trend that speedup offered by SOI technology decreases with scaling     

Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA

In this work, we are making energy efficient ALU using the most energy efficient LVCMOS IO standard for the highest frequency of i7 processor. It is observed that LVCMOS12 is the most energy efficient than all available LVCMOS having 26.23, 58.37 and 75.65 % less IO power reduction than LVCMOS18, LVCMOS25 and LVCMOS33 respectively at 1 GHz. Then we are making this ALU portable using MOBILE DDR IO standard in place of default LVCMOS33 IO standard which we use in traditional ALU. As we replace LVCMOS with MOBILE DDR, we are achieving 69.07 % portability in terms of IO power and 29.36 % in terms of Leakage power at 2.9 GHz. In next stage, we try to enhance the performance of ALU with MOBILE DDR but not beyond the power consumption with LVCMOS. In that way, we achieve the highest frequency of 12 GHz with MOBILE DDR. That was earlier possible for 3.8 GHz 64-bit ALU using CMOS. In this HDL based implementation of 64-bit ALU on FPGA, Kintex-7 FPGA is used with XC7K70T device and FBG676 package is used.     

基于探测概率曲线的探测灵敏度测试方法

相对于传统直接测试探测灵敏度的方法,提出了基于探测概率曲线的探测灵敏度测试方法,详细阐述了测试方法和步骤以及数据处理方法.按照上述方法,对某高性能激光探测接收机的探测灵敏度进行了测试,测试过程及结果表明,该方法在操作的简便性和测试结果的准确度上均优于传统测试方法.     

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry /spl times/ 32-bit register file is described. In a 130 nm six-metal, dual-V/sub T/ CMOS technology, the 2.3 mm/sup 2/ prototype contains 160 K transistors. Measurements demonstrate capability for 5-GHz single-cycle integer execution at 25/spl deg/C. The single-ended, leakage-tolerant dynamic scheme used in the ALU and scheduler enables up to 9-wide ORs with 23% critical path speed improvement and 40% active leakage power reduction when compared to a conventional Kogge-Stone implementation. On-chip body-bias circuits provide additional performance improvement or leakage tolerance. Stack node preconditioning improves ALU performance by 10%. At 5 GHz, ALU power is 95 mW at 0.95 V and the register file consumes 172 mW at 1.37 V. The ALU performance is scalable to 6.5 GHz at 1.1 V and to 10 GHz at 1.7 V, 25/spl deg/C.     

On the design of fast, easily testable ALU's

A design methodology for implementing fast, easily testable arithmetic-logic units (ALUs) is presented. Here, we describe a set of fast adder designs, which are testable with a test set that has either &thetas;(N) complexity (Lin-testable) or &thetas;(1) complexity (C-testable), where N is the input operand size of the ALU. The various levels of testability are achieved by exploiting some inherent properties of carry-lookahead addition. The Lintestable and C-testable ALU designs require only one extra input, regardless of the size of the ALU. The area overhead for a high-speed 64-bit Lintestable ALU is only 0.5%