High Performance Indium‐Gallium‐Zinc Oxide Thin Film Transistor via Interface Engineering

Solution‐processed indium‐gallium‐zinc oxide (IGZO) thin film transistors (TFTs) have become well known in recent decades for their promising commercial potential. However, the unsatisfactory performance of small‐sized IGZO TFTs is limiting their applicability. To address this issue, this work introduces an interface engineering method of bi‐functional acid modification to regulate the interfaces between electrodes and the channels of IGZO TFTs. This method increases the interface oxygen vacancy concentration and reduces the surface roughness, resulting in higher mobility and enhanced contact at the interfaces. The TFT devices thus treated display contact resistance reduction from 9.1 to 2.3 kΩmm, as measured by the gated four‐probe method, as well as field‐effect mobility increase from 1.5 to 4.5 cm² (V s)^?1. Additionally, a 12 × 12 organic light emitting diode display constructed using the acid modified IGZO TFTs as switching and driving elements demonstrate the applicability of these devices.     

Molecule Charge Transfer Doping for p‐Channel Solution‐Processed Copper Oxide Transistors

The doping of semiconductors plays a critical role in improving the performance of modern electronic devices by precisely controlling the charge carrier density. However, the absence of a stable doping method for p‐type oxide semiconductors has severely restricted the development of metal oxide‐based transparent p–n junctions and complementary circuits. Here, an efficient and stable doping process for p‐type oxide semiconductors by using molecule charge transfer doping with tetrafluoro‐tetracyanoquinodimethane (F₄TCNQ) is reported. The selections of a suitable dopant and geometry play a crucial role in the charge‐transfer doping effect. The insertion of a F₄TCNQ thin dopant film (2–7 nm) between a Au source‐drain electrode and solution‐processed p‐type copper oxide (Cu_xO) film in bottom‐gate top‐contact thin‐film transistors (TFTs) provides a mobility enhancement of over 20‐fold with the desired threshold voltage adjustment. By combining doped p‐type Cu_xO and n‐type indium gallium zinc oxide TFTs, a solution‐processed transparent complementary metal‐oxide semiconductor inverter is demonstrated with a high gain voltage of 50. This novel p‐doping method is expected to accelerate the development of high‐performance and reliable p‐channel oxide transistors and has the potential for widespread applications.     

Top Interface Engineering of Flexible Oxide Thin‐Film Transistors by Splitting Active Layer

The effect of active layer (amorphous indium–gallium–zinc oxide, a‐IGZO) splitting on the performances of back‐channel‐etched (BCE) and etch‐stopper (ES) thin‐film transistors (TFTs) on polyimide substrate is studied. While the performance of BCE TFT is independent of active layer splitting, the performance of ES TFT is improved significantly by splitting the active layer into 2–4 µm width along the channel. The saturation mobility is enhanced from 24.3 to 76.8 cm² V^?1 s^?1 and this improvement is confirmed by the operation of a ring oscillator made of the split TFTs also. X‐ray photoelectron spectroscopy (XPS) analysis of the split a‐IGZO indicates the incorporation of F at the island interface and thus improves the top interface quality, leading to a significant improvement of the top channel TFT mobility from 0.25 to 24.22 cm² V^?1 s^?1. This improvement is correlated with bonding of In with F at the top interface according to XPS results. The bias stability, hysteresis, and mechanical stability of the ES a‐IGZO TFT are also remarkably improved by splitting a‐IGZO active layer.     

Skin‐Like Oxide Thin‐Film Transistors for Transparent Displays

Flexible transparent display is a promising candidate to visually communicate with each other in the future Internet of Things era. The flexible oxide thin‐film transistors (TFTs) have attracted attention as a component for transparent display by its high performance and high transparency. The critical issue of flexible oxide TFTs for practical display applications, however, is the realization on transparent and flexible substrate without any damage and characteristic degradation. Here, the ultrathin, flexible, and transparent oxide TFTs for skin‐like displays are demonstrated on an ultrathin flexible substrate using an inorganic‐based laser liftoff process. In this way, skin‐like ultrathin oxide TFTs are conformally attached onto various fabrics and human skin surface without any structural damage. Ultrathin flexible transparent oxide TFTs show high optical transparency of 83% and mobility of 40 cm² V^?1 s^?1. The skin‐like oxide TFTs show reliable performance under the electrical/optical stress tests and mechanical bending tests due to advanced device materials and systematic mechanical designs. Moreover, skin‐like oxide logic inverter circuits composed of n‐channel metal oxide semiconductor TFTs on ultrathin, transparent polyethylene terephthalate film have been realized.     

Water‐Induced Scandium Oxide Dielectric for Low‐Operating Voltage n‐ and p‐Type Metal‐Oxide Thin‐Film Transistors

Solution‐processed metal‐oxide thin films based on high dielectric constant (k) materials have been extensively studied for use in low‐cost and high‐performance thin‐film transistors (TFTs). Here, scandium oxide (ScO_x) is fabricated as a TFT dielectric with excellent electrical properties using a novel water‐inducement method. The thin films are annealed at various temperatures and characterized by using X‐ray diffraction, atomic‐force microscopy, X‐ray photoelectron spectroscopy, optical spectroscopy, and a series of electrical measurements. The optimized ScO_x thin film exhibits a low‐leakage current density of 0.2 nA cm^?2 at 2 MV cm^?1, a large areal capacitance of 460 nF cm^?2 at 20 Hz and a permittivity of 12.1. To verify the possible applications of ScO_x thin films as the gate dielectric in complementary metal oxide semiconductor (CMOS) electronics, they were integrated in both n‐type InZnO (IZO) and p‐type CuO TFTs for testing. The water‐induced full oxide IZO/ScO_x TFTs exhibit an excellent performance, including a high electron mobility of 27.7 cm² V^?1 s^?1, a large current ratio (I_on/I_off) of 2.7 × 10⁷ and high stability. Moreover, as far as we know it is the first time that solution‐processed p‐type oxide TFTs based on a high‐k dielectric are achieved. The as‐fabricated p‐type CuO/ScO_x TFTs exhibit a large I_on/I_off of around 10⁵ and a hole mobility of 0.8 cm² V^?1 at an operating voltage of 3 V. To the best of our knowledge, these electrical parameters are among the highest performances for solution‐processed p‐type TFTs, which represents a great step towards the achievement of low‐cost, all‐oxide, and low‐power consumption CMOS logics.     

A Transparent Logic Circuit for RFID Tag in a‐IGZO TFT Technology

This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistor (TFT) technology. The RFID logic circuit generates 16‐bit code programmed in read‐only memory. All circuits are implemented in a pseudo‐CMOS logic style using transparent a‐IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300‐nm to 800‐nm wavelength. The RFID logic chip generates Manchester‐encoded 16‐bit data with a 3.2‐kHz clock frequency and consumes 170 μW at . It employs 222 transistors and occupies a chip area of 5.85 mm².     

Mirrored OLED pixel circuit for threshold voltage and mobility compensation with IGZO TFTs

In this paper, pixel circuit using mirroring structure with Indium–Gallium–Zinc oxide (IGZO) thin film transistors (TFTs) for active matrix organic light emitting diode (AMOLED) display is proposed. This pixel circuit consists of only four TFTs, and one capacitor. Due to the mirroring structure, characteristic of the driving TFT can be precisely sensed by the sensing TFT, which is deployed in a discharging path for gate electrode of the driving TFT. This discharging process is strongly dependent on threshold voltage (V_T) and effective mobility of the sensing TFT. Circuit operating details are discussed, and compensation effects for threshold voltage shift and mobility variations are verified through numerical derivation and SPICE simulations. Furthermore, compared with conventional schematics, the proposed pixel circuit might have much simplified external driving circuits, and it is a promising alternative solution of high performance AMOLED display.     

Large‐Area Schottky Barrier Transistors Based on Vertically Stacked Graphene–Metal Oxide Heterostructures

The fabrication of all‐transparent flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–metal oxide–metal heterostructures and ion gel gate dielectrics is demonstrated. The vertical SB transistor structure is formed by (i) vertically sandwiching a solution‐processed indium‐gallium‐zinc‐oxide (IGZO) semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with a vertical channel through an ion gel. The channel current is modulated by tuning the Schottky barrier height across the graphene–IGZO junction under an applied external gate bias. The ion gel gate dielectric with high specific capacitance enables modulation of the Schottky barrier height at the graphene–IGZO junction over 0.87 eV using a voltage below 2 V. The resulting vertical devices show high current densities (18.9 A cm^?2) and on–off current ratios (>10⁴) at low voltages. The simple structure of the unit transistor enables the successful fabrication of low‐power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large‐area, and room‐temperature deposition of both semiconducting metal oxide and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene‐based future electronics.     

Donor‐Induced Performance Tuning of Amorphous SrTiO3 Memristive Nanodevices: Multistate Resistive Switching and Mechanical Tunability

Metal–oxide valence‐change memristive devices are the key contenders for the development of multilevel nonvolatile analog memories and neuromorphic computing architectures. Reliable low energy performance and tunability of nonlinear resistive switching dynamics are essential to streamline the high‐density circuit level integration of these devices. Here, manipulation of room temperature‐synthesized defect chemistry is employed to enhance and tune the switching characteristics of high‐performance amorphous SrTiO₃ (a‐STO) memristors. Substitutional donor (Nb) doping with low concentrations in the a‐STO oxide structure allows extensive improvements in energy requirements, stability, and controllability of the memristive performance, as well as field‐dependent multistate resistive switching. Evidence is presented that room temperature donor doping results in a modified insulator oxide where dislocation sites act as charge carrier modulators for low energy and multilevel operation. Finally, the performance of donor‐doped a‐STO‐based memristive nanodevices is showcased, with the possibility of mechanical modulation of the nonlinear memristive characteristics of these devices demonstrated. These results highlight the potential of donor‐doped a‐STO nanodevices for high‐density integration as analog memories and multifunctional alternative logic elements.     

Highly Robust Bendable Oxide Thin‐Film Transistors on Polyimide Substrates via Mesh and Strip Patterning of Device Layers

Advancement in thin‐film transistor (TFT) technologies has extended to applications that can withstand extreme bending or folding. The changes of the performances of amorphous‐indium‐gallium‐zinc‐oxide (a‐IGZO) TFTs on polyimide substrate after application of extreme mechanical bending strain are studied. The TFT designs include mesh and strip patterned source/drain metal lines as well as strip patterned a‐IGZO semiconductor layer. The robustness of the a‐IGZO TFTs with the strain of 2.17% corresponding to the radius of 0.32 mm is tested and no crack generation even after 60 000 bending cycles is found. The split of source/drain electrodes and semiconductor layer can improve the mechanical bending stability of the TFTs. This can be possible by using conventional TFT manufacturing process so that this technology can be easily applied to build robust TFT array for foldable displays.     

Low‐Temperature‐Processed Printed Metal Oxide Transistors Based on Pure Aqueous Inks

Additive patterning of transparent conducting metal oxides at low temperatures is a critical step in realizing low‐cost transparent electronics for display technology and photovoltaics. In this work, inkjet‐printed metal oxide transistors based on pure aqueous chemistries are presented. These inks readily convert to functional thin films at lower processing temperatures (T ≤ 250 °C) relative to organic solvent‐based oxide inks, facilitating the fabrication of high‐performance transistors with both inkjet‐printed transparent electrodes of aluminum‐doped cadmium oxide (ACO) and semiconductor (InO_x ). The intrinsic fluid properties of these water‐based solutions enable the printing of fine features with coffee‐ring free line profiles and smoother line edges than those formed from organic solvent‐based inks. The influence of low‐temperature annealing on the optical, electrical, and crystallographic properties of the ACO electrodes is investigated, as well as the role of aluminum doping in improving these properties. Finally, the all‐aqueous‐printed thin film transistors (TFTs) with inkjet‐patterned semiconductor (InO_x ) and source/drain (ACO) layers are characterized, which show ideal low contact resistance (R _c < 160 Ω cm) and competitive transistor performance (µ _lin up to 19 cm² V^?1 s^?1, Subthreshold Slope (SS) ≤150 mV dec^?1) with only low‐temperature processing (T ≤ 250 °C).     

Effect of Temperature and Illumination on the Electrical Characteristics of Polymer–Fullerene Bulk‐Heterojunction Solar Cells

The current–voltage characteristics of ITO/PEDOT:PSS/OC₁C₁₀‐PPV:PCBM/Al solar cells were measured in the temperature range 125–320 K under variable illumination, between 0.03 and 100 mW cm^–2 (white light), with the aim of determining the efficiency‐limiting mechanism(s) in these devices, and the temperature and/or illumination range(s) in which these devices demonstrate optimal performance. (ITO: indium tin oxide; PEDOT:PSS: poly(styrene sulfonate)‐doped poly(ethylene dioxythiophene); OC₁C₁₀‐PPV: poly[2‐methoxy‐5‐(3,7‐dimethyl octyloxy)‐1,4‐phenylene vinylene]; PCBM: phenyl‐C₆₁ butyric acid methyl ester.) The short‐circuit current density and the fill factor grow monotonically with temperature until 320 K. This is indicative of a thermally activated transport of photogenerated charge carriers, influenced by recombination with shallow traps. A gradual increase of the open‐circuit voltage to 0.91 V was observed upon cooling the devices down to 125 K. This fits the picture in which the open‐circuit voltage is not limited by the work‐function difference of electrode materials used. The overall effect of temperature on solar‐cell parameters results in a positive temperature coefficient of the power conversion efficiency, which is 1.9 % at T = 320 K and 100 mW cm^–2 (2.5 % at 0.7 mW cm^–2). The almost‐linear variation of the short‐circuit current density with light intensity confirms that the internal recombination losses are predominantly of monomolecular type under short‐circuit conditions. We present evidence that the efficiency of this type of solar cell is limited by a light‐dependent shunt resistance. Furthermore, the electronic transport properties of the absorber materials, e.g., low effective charge‐carrier mobility with a strong temperature dependence, limit the photogenerated current due to a high series resistance, therefore the active layer thickness must be kept low, which results in low absorption for this particular composite absorber.     

Effect of Oxygen Binding Energy on the Stability of Indium‐Gallium‐Zinc‐Oxide Thin‐Film Transistors

From a practical viewpoint, the topic of electrical stability in oxide thin‐film transistors (TFTs) has attracted strong interest from researchers. Positive bias stress and constant current stress tests on indium‐gallium‐zinc‐oxide (IGZO)‐TFTs have revealed that an IGZO‐TFT with a larger Ga portion has stronger stability, which is closely related with the strong binding of O atoms, as determined from an X‐ray photoelectron spectroscopy analysis.     

Fabrication of Releasable Single‐Crystal Silicon–Metal Oxide Field‐Effect Devices and Their Deterministic Assembly on Foreign Substrates

A new class of thin, releasable single‐crystal silicon semiconductor device is presented that enables integration of high‐performance electronics on nearly any type of substrate. Fully formed metal oxide–semiconductor field–effect transistors with thermally grown gate oxides and integrated circuits constructed with them demonstrate the ideas in devices mounted on substrates ranging from flexible sheets of plastic, to plates of glass and pieces of aluminum foil. Systematic study of the electrical properties indicates field‐effect mobilities of ≈710 cm² V^?1 s^?1, subthreshold slopes of less than 0.2 V decade^?1 and minimal hysteresis, all with little to no dependence on the properties of the substrate due to bottom silicon surfaces that are passivated with thermal oxide. The schemes reported here require only interconnect metallization to be performed on the final device substrate, which thereby minimizes the need for any specialized processing technology, with important consequences in large‐area electronics for display systems, flexible/stretchable electronics, or other non‐wafer‐based devices.     

Printed Sub‐2 V Gel‐Electrolyte‐Gated Polymer Transistors and Circuits

The fabrication and characterization of printed ion‐gel‐gated poly(3‐hexylthiophene) (P3HT) transistors and integrated circuits is reported, with emphasis on demonstrating both function and performance at supply voltages below 2 V. The key to achieving fast sub‐2 V operation is an unusual gel electrolyte based on an ionic liquid and a gelating block copolymer. This gel electrolyte serves as the gate dielectric and has both a short polarization response time (<1 ms) and a large specific capacitance (>10 µF cm^?2), which leads simultaneously to high output conductance (>2 mS mm^?1), low threshold voltage (<1 V) and high inverter switching frequencies (1–10 kHz). Aerosol‐jet‐printed inverters, ring oscillators, NAND gates, and flip‐flop circuits are demonstrated. The five‐stage ring oscillator operates at frequencies up to 150 Hz, corresponding to a propagation delay of 0.7 ms per stage. These printed gel electrolyte gated circuits compare favorably with other reported printed circuits that often require much larger operating voltages. Materials factors influencing the performance of the devices are discussed.     

Field‐Effect Transistors on Photonic Cellulose Nanocrystal Solid Electrolyte for Circular Polarized Light Sensing

The integration of bioinspired chiral cellulose nanocrystal (CNC) films into transistor devices with distinct sensing properties for left‐ and right‐handed circular polarized light (LCPL and RCPL, respectively) is reported. The CNC films with a left‐handed internal long‐range order are infiltrated with sodium ions to yield solid‐state electrolytes with photonic properties capable of LCPL reflection and RCPL transmission. They are employed as gate dielectrics in sputtered amorphous indium–gallium–zinc oxide (a‐IGZO) transistors. The obtained devices operate in depletion mode at low voltages (<2 V) with On–Off ratios of up to 7 orders of magnitude, subthreshold swings around 80 mV dec^?1, and saturation mobilities up to 9 cm² V^?1 s^?1. Combining the photonic character of the CNC films with the light sensitivity of a‐IGZO, the devices are capable of discrimination between LCPL and RCPL signals in the blue region. These type of devices can find application in photonics, emission, conversion, or sensing with CPL but also imaging or spintronics.     

Low‐Temperature,Nontoxic Water‐Induced Metal‐Oxide Thin Films and Their Application in Thin‐Film Transistors

Here, a simple, nontoxic, and inexpensive “water‐inducement” technique for the fabrication of oxide thin films at low annealing temperatures is reported. For water‐induced (WI) precursor solution, the solvent is composed of water without additional organic additives and catalysts. The thermogravimetric analysis indicates that the annealing temperature can be lowered by prolonging the annealing time. A systematic study is carried out to reveal the annealing condition dependence on the performance of the thin‐film transistors (TFTs). The WI indium‐zinc oxide (IZO) TFT integrated on SiO₂ dielectric, annealed at 300 °C for 2 h, exhibits a saturation mobility of 3.35 cm² V^?1 s^?1 and an on‐to‐off current ratio of ≈10⁸. Interestingly, through prolonging the annealing time to 4 h, the electrical parameters of IZO TFTs annealed at 230 °C are comparable with the TFTs annealed at 300 °C. Finally, fully WI IZO TFT based on YO_x dielectric is integrated and investigated. This TFT device can be regarded as “green electronics” in a true sense, because no organic‐related additives are used during the whole device fabrication process. The as‐fabricated IZO/YO_x TFT exhibits excellent electron transport characteristics with low operating voltage (≈1.5 V), small subthreshold swing voltage of 65 mV dec^?1 and the mobility in excess of 25 cm² V^?1 s^?1.     

Unexpected Propeller‐Like Hexakis(fluoren‐2‐yl)benzene Cores for Six‐Arm Star‐Shaped Oligofluorenes: Highly Efficient Deep‐Blue Fluorescent Emitters and Good Hole‐Transporting Materials

Grafting six fluorene units to a benzene ring generates a new highly twisted core of hexakis(fluoren‐2‐yl)benzene. Based on the new core, six‐arm star‐shaped oligofluorenes from the first generation T1 to third generation T3 are constructed. Their thermal, photophysical, and electrochemical properties are studied, and the relationship between the structures and properties is discussed. Simple double‐layer electroluminescence (EL) devices using T1–T3 as non‐doped solution‐processed emitters display deep‐blue emissions with Commission Internationale de l'Eclairage (CIE) coordinates of (0.17, 0.08) for T1 , (0.16, 0.08) for T2 , and (0.16, 0.07) for T3 . These devices exhibit excellent performance, with maximum current efficiency of up to 5.4 cd A^?1, and maximum external quantum efficiency of up to 6.8%, which is the highest efficiency for non‐doped solution‐processed deep‐blue organic light‐emitting diodes (OLEDs) based on starburst oligofluorenes, and is even comparable with other solution‐processed deep‐blue fluorescent OLEDs. Furthermore, T2‐ and T3‐ based devices show striking blue EL color stability independent of driving voltage. In addition, using T0–T3 as hole‐transporting materials, the devices of indium tin oxide (ITO)/poly(3,4‐ethylenedioxythiophene):poly(styrene sulfonic acid) (PEDOT:PSS)/ T0–T3 /tris(8‐hydroxyquinolinato)aluminium (Alq₃)/LiF/Al achieve maximum current efficiencies of 5.51–6.62 cd A^?1, which are among the highest for hole‐transporting materials in identical device structure.     

Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

Effects of Interfacial Dielectric Layers on the Electrical Performance of Top‐Gate In‐Ga‐Zn‐Oxide Thin‐Film Transistors

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top‐gate In‐Ga‐Zn‐oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si₃N₄ and Al₂O₃, the electrical properties are analyzed. After post‐annealing at 200°C for 1 hour in an O₂ ambient, the sub‐threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative‐bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si‐based broken bonds and hydrogen‐based bonds. From constant‐current stress tests of Id = 3 µA, an IGZO‐TFT with heat‐treated Si₃N₄ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge‐injection and electron‐trapping behavior.