High Performance Millimeter‐Wave Image Reject Low‐Noise Amplifier Using Inter‐stage Tunable Resonators

A Q‐band pHEMT image‐rejection low‐noise amplifier (IR‐LNA) is presented using inter‐stage tunable resonators. The inter‐stage L‐C resonators can maximize an image rejection by functioning as inter‐stage matching circuits at an operating frequency (F_OP) and short circuits at an image frequency (F_IM). In addition, it also brings more wideband image rejection than conventional notch filters. Moreover, tunable varactors in L‐C resonators not only compensate for the mismatch of an image frequency induced by the process variation or model error but can also change the image frequency according to a required RF frequency. The implemented pHEMT IR‐LNA shows 54.3 dB maximum image rejection ratio (IRR). By changing the varactor bias, the image frequency shifts from 27 GHz to 37 GHz with over 40 dB IRR, a 19.1 dB to 17.6 dB peak gain, and 3.2 dB to 4.3 dB noise figure. To the best of the authors' knowledge, it shows the highest IRR and F_IM/F_OP of the reported millimeter/quasi‐millimeter wave IR‐LNAs.     

A switch‐controlled multimode narrowband receiver RF front‐end

This work illustrates a flexible and convenient method to build a multimode narrowband receiver RF front‐end by means of controlled switches, switched capacitors, and switched inductors. The front‐end comprises a dual‐gain‐mode narrowband low‐noise amplifier (LNA) and a dual‐linearity‐mode mixer. A four‐mode receiver RF front‐end constructed with the dual‐gain‐mode LNA and the dual‐linearity‐mode mixer operating in frequency band range from 1800 to 2050 MHz was demonstrated with an IBM 90‐nm CMOS process. The front‐end achieves a 1/1.6 dB noise figure, 30/20 dB power gain, and 16/?10 dBm third‐order input intercept point while draws a 5.9/3.6 mA current from a 1.8‐V supply voltage at the low noise mode and high linearity mode, respectively. The proposed technique can be employed to build an intelligent mobile system.     

High‐Gain Wideband CMOS Low Noise Amplifier with Two‐Stage Cascode and Simplified Chebyshev Filter

An ultra‐wideband low‐noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18‐μm CMOS process and adopts a two‐stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input‐impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power‐gain bandwidth product of 399.4 GHz.     

A 75 GHz to 115 GHz quasi-optical amplifier

A wideband quasi-optical amplifier employing two pyramidal back-to-back horns has been developed. Using a four-stage W-band low noise amplifier (LNA) designed and fabricated by Martin Marietta Laboratories, the quasi-optical amplifier gives a system gain greater than 11 dB from 86 GHz to 113 GHz without any low frequency oscillations. A peak system gain of 15.5 dB is measured at 102 GHz, and the measured noise figure of the system is 7.4 dB at 94 GHz. The quasi-optical amplifier design maintains the same polarization of the received and transmitted signal, provides better than -40 dB isolation, and can be fabricated monolithically at millimeter-wave frequencies     

A low-current Ku-band GaAs monolithic image rejectiondown-converter

A single-chip image rejection downconverter has been designed, fabricated. and tested for broadcast satellite receivers operating in the 11.7- to 12.2-GHz range. The downconverter consists of an RF low-noise amplifier (LNA), a filter-type image rejection mixer (IRM), and an intermediate frequency amplifier (IFA). It receives 11.7- to 12.2-GHz RF signals and down converts to 1.0- to 1.5-GHz IF signals with an external local oscillator. Since the filter integrated on the downconverter produces an image rejection of more than 30 dB, the downconverter requires no off-chip circuits for the image rejection. A conversion gain of 37±1 dB and a noise figure of less than 3.5 dB have been achieved over the RF frequency range. The current dissipation is only 40 mA, and the chip size is 2.8 mm×2.8 mm×0.45 mm     

Design and implementation of a 94 GHz CMOS down-conversion mixer with integrated miniature planar baluns for image radar sensors

A 94 GHz down-conversion mixer for image radar sensors using standard 90 nm CMOS technology is reported. The down-conversion mixer comprises a double-balanced Gilbert cell with peaking inductors between RF transconductance stage and LO switching transistors for conversion gain (CG) enhancement and noise figure suppression, a miniature planar balun for converting the single RF input signals to differential signals, another miniature planar balun for converting the single LO input signals to differential signals, and an IF amplifier. The mixer consumes 22.5 mW and achieves excellent RF-port input reflection coefficient of ?10 to ?35.9 dB for frequencies of 87.6–104.4 GHz, and LO-port input reflection coefficient of ?10 to ?31.9 dB for frequencies of 88.2–110 GHz. In addition, the mixer achieves CG of 4.9–7.9 dB for frequencies of 81.8–105.8 GHz (the corresponding 3-dB CG bandwidth is 24 GHz) and LO–RF isolation of 37.7–47.5 dB for frequencies of 80–110 GHz, one of the best CG and LO–RF isolation results ever reported for a down-conversion mixer with operation frequency around 94 GHz. Furthermore, the mixer achieves an excellent input third-order intercept point of ?3 dBm at 94 GHz. These results demonstrate the proposed down-conversion mixer architecture is promising for 94 GHz image radar sensors.     

Concurrent design of Schottky diode limiter and LNA

In this paper concurrent design of Schottky diode based limiter and low noise amplifier (LNA), based on noise matching, is investigated to achieve minimum noise figure (NF) of the receiver chain. In design procedure of the LNA, the noise figure is minimum, gain at central frequency is 14.5 dB, and limiter structure tolerates up to 5 W continuous wave input power. In the proposed concurrent design, a pass-band filter is applied at the LNA output to attenuate undesired out-of-band signals. In the proposed design, the limiter-LNA is implemented with a 0.25 µm gate length AlGaAs/InGaAs pHEMT process. Measured noise figure of chain is 2.7 dB and average gain over 8.5–9.5 GHz frequency range and the gain at 9 GHz center frequency are 10 dB and 14.5 dB respectively. The performance results of proposed matching network are compared with traditional 50 Ω matching networks in limiter-LNA with identical circuit specifications.

     

Erratum to: Using Improved Product-Coded Modulation Codes to Reduce the Peak-to-Average Power Ratio in Single-Carrier Frequency Division Multiple Access Systems

A new ultra-wideband common gate low noise amplifier (LNA) for 3–6 GHz WLAN and WPAN applications is presented in which a current reused noise canceling structure utilized in the first stage not only provides a suitable noise performance, but also enhances the linearity characteristics of the LNA in a power efficient manner needed by WLAN/WPAN applications. The overall structure of the proposed LNA, consisting of three stages, namely input matching common gate stage with noise canceling, gain stage, and buffer one, is designed, laid out, and analyzed in 0.18 µm RF CMOS process. The LNA has a noise figure of 3.5–3.6 dB, a high and flat power gain of 20.27 ± 0.13 dB, and input and output losses of better than ?11 and ?14 dB, respectively, over the entire frequency band of 3–5 GHz, while these parameters are 3.5 dB, 20.75 ± 0.25 dB, ?15 and ?9 dB for the frequency band of 5–6 GHz, respectively. IIP2 and IIP3 of the proposed topology are equal to 25.9 and ?1.85 dBm, respectively, at 4 GHz frequency. The proposed LNA has 15.3 mW power dissipation from a 1.8 V supply.     

A Ka-band Four-stage Self-biased Monolithic Low Noise Amplifier

A Ka-band four-stage self-biased monolithic low noise amplifier has been developed using a commercial 0.18-μm pseudomorphic high electron-mobility transistor (pHEMT) process. For the application of self-bias technique, the low noise amplifier (LNA) is biased from a single power supply rail. The LNA has achieved a broadband performance with a gain of more than 18 dB, a noise figure of less than 3.8 dB in the RF frequency of 26 to 40 GHz. The chip size is 3 × 1 mm².     

宽带高增益输出平衡CMOS低噪声放大器的设计

设计了一种带片内变压器、适用于0.05～2.5 GHz频段的宽带低噪声放大器(LNA).电路设计采用了并行的共栅共源放大结构,将从天线接收到的单端输入信号转换为一对差分信号输出给后级链路.针对变压器结构的LNA噪声系数不够低和输出不平衡的问题,采用了缩放技术、噪声消除技术以及两级的全差分放大器作为输出缓冲级,来有效降低电路的噪声系数,提高增益和输出平衡度.电路采用TSMC 0.18μm 1P6M RF CMOS工艺设计仿真和流片,测试结果表明:在0.05 ～ 2.5 GHz频带范围内,该LNA的最高功率增益达24.5 dB,全频段内噪声系数为2.6～4 dB,输入反射系数小于-10 dB,输出差分信号幅度和相位差分别低于0.6dB和1.8°.     

10‐Gbit/s Wireless Communication System at 300 GHz

A 10‐Gbit/s wireless communication system operating at a carrier frequency of 300 GHz is presented. The modulation scheme is amplitude shift keying in incoherent mode with a high intermediate frequency (IF) of 30 GHz and a bandwidth of 20 GHz for transmitting a 10‐Gbit/s baseband (BB) data signal. A single sideband transmission is implemented using a waveguide‐tapered 270‐GHz highpass filter with a lower sideband rejection of around 60 dB. This paper presents an all‐electronic design of a terahertz communication system, including the major modules of the BB and IF band as well as the RF modules. The wireless link shows that, aided by a clock and data recovery circuit, it can receive 2⁷?1 pseudorandom binary sequence data without error at up to 10 Gbit/s for over 1.2 m using collimating lenses, where the transmitted power is 10 μW.     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.     

Design of a Noise-Canceling CMOS Wideband Receiver Front-End with Inherent Active Balun

This paper presents the design of an ESD-protected noise-canceling CMOS wideband receiver front-end for cognitive and ultra-wideband (UWB) radio-based wireless communications. Designed in a 0.13-μm CMOS technology, the RF front-end integrates a broadband low-noise amplifier (LNA) and a quadrature down-conversion mixer. While having ESD and package parasitics absorbed into a wideband input matching network, the LNA exploits a combination of a common-gate (CG) stage and a common-source (CS) stage to cancel the noise of the CG-stage and to provide a well balanced differential output for driving the double-balance mixer, which has a merged quadrature topology. A variable-gain method is developed for the LNA to achieve a large factor of gain switch without degrading the input impedance match and the balun function. Drawing 24 mA from 1.5 V, simulations show that the proposed front-end has a 3-dB bandwidth of around 10 GHz spanning from 1.8 GHz up to 11.8 GHz with a maximum voltage conversion gain of 30 dB and a noise figure of 4.3–6.7 dB over the entire band.     

6‐GHz‐to‐18‐GHz AlGaN/GaN Cascaded Nonuniform Distributed Power Amplifier MMIC Using Load Modulation of Increased Series Gate Capacitance

A 6‐GHz‐to‐18‐GHz monolithic nonuniform distributed power amplifier has been designed using the load modulation of increased series gate capacitance. This amplifier was implemented using a 0.25‐μm AlGaN/GaN HEMT process on a SiC substrate. With the proposed load modulation, we enhanced the amplifier's simulated performance by 4.8 dB in output power, and by 13.1% in power‐added efficiency (PAE) at the upper limit of the bandwidth, compared with an amplifier with uniform gate coupling capacitors. Under the pulse‐mode condition of a 100‐μs pulse period and a 10% duty cycle, the fabricated power amplifier showed a saturated output power of 39.5 dBm (9 W) to 40.4 dBm (11 W) with an associated PAE of 17% to 22%, and input/output return losses of more than 10 dB within 6 GHz to 18 GHz.     

110-120-GHz monolithic low-noise amplifiers

The authors discuss the development of 110-120-GHz monolithic low-noise amplifiers (LNAs) using 0.1-mm pseudomorphic AlGaAs/InGaAs/GaAs low-noise HEMT technology. Two 2-stage LNAs have been designed, fabricated, and tested. The first amplifier demonstrates a gain of 12 dB at 112 to 115 GHz with a noise figure of 6.3 dB when biased for high gain, and a noise figure of 5.5 dB is achieved with an associated gain of 10 dB at 113 GHz when biased for low-noise figure. The other amplifier has a measured small-signal gain of 19.6 dB at 110 GHz with a noise figure of 3.9 dB. A noise figure of 3.4 dB with 15.6-dB associated gain was obtained at 113 GHz. The authors state that the small-signal gain and noise figure performance for the second LNA are the best results ever achieved for a two-stage HEMT amplifier at this frequency band     

0.18 /spl mu/m CMOS dual-band UWB LNA with interference rejection

A CMOS dual-band ultra-wideband low noise amplifier (LNA) with interference rejection is presented. The proposed LNA employs a current reuse structure to reduce power consumption and an active notch filter to produce in-band rejection in the 5 GHz WLAN frequency band. The load tank of the current reuse stage is optimised to provide an additional out-band attenuation in the 2.4 GHz WLAN band. Measurement shows a peak gain of 19.7 dB in the low band (3-5 GHz) and 20.3 dB in the high band (6-10 GHz), while the in-band and out-band maximum rejections are 19.6 and 12.8 dB, respectively.     

Design of UWB switched gain controlled LNA using 0.18 μm CMOS

A switched gain controlled low noise amplifier (LNA) for the 3.1- 4.8 GHz ultra-wideband system is presented. The LNA is fabricated with the 0.18 mum 1P6M standard CMOS process. Measurement of the LNA was performed using an RF probe station. In gain mode, measured results show a noise figure of 4.68-4.97 dB, gain of 12.5-13.9 dB, and input/output return loss higher than 10/8.2 dB. The input IP3 (IIP3) at 4.1 GHz is 1 dBm, and consumes 14.6 mW of power. In bypass mode, measured results show a gain of-7.0 to -8.7 dB, and input/output return loss higher than 10/6.3 dB. The input IP3 at 4.1 GHz is 9.2 dBm, and consumes 1 muW of power.     

16‐QAM OFDM‐Based W‐Band Polarization‐Division Duplex Communication System with Multi‐gigabit Performance

This paper presents a novel 90 GHz band 16‐quadrature amplitude modulation (16‐QAM) orthogonal frequency‐division multiplexing (OFDM) communication system. The system can deliver 6 Gbps through six channels with a bandwidth of 3 GHz. Each channel occupies 500 MHz and delivers 1 Gbps using 16‐QAM OFDM. To implement the system, a low‐noise amplifier and an RF up/down conversion fourth‐harmonically pumped mixer are implemented using a 0.1‐μm gallium arsenide pseudomorphic high‐electron‐mobility transistor process. A polarization‐division duplex architecture is used for full‐duplex communication. In a digital modem, OFDM with 256‐point fast Fourier transform and (255, 239) Reed‐Solomon forward error correction codecs are used. The modem can compensate for a carrier‐frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of 10^–5 at a signal‐to‐noise ratio of about 19.8 dB.     

A Packaged and ESD-Protected Inductorless 0.1–8 GHz Wideband CMOS LNA

In this letter, an inductorless 0.1-8 GHz wideband CMOS differential low noise amplifier (LNA) based on a modified resistive feedback topology is proposed. Without using any passive inductors, the modified resistive feedback technique implemented with a parallel R-C feedback, an active inductor load, and neutralization capacitors achieves high gain, low noise, and good return loss over a wide bandwidth. To ensure the robustness in the system integration, electro-static discharge diodes are added to the radio frequency pads. The LNA was fabricated using a digital 90 nm CMOS technology. It achieves a 3 dB bandwidth of 8 GHz with a 16 dB voltage gain, noise figures from 3.4 dB to 5.8 dB across the whole band, and an input third-order intermodulation product (IIP3) of -9 dBm. The active area of the chip is 0.034 mm². The chip was packaged and tested on an FR4 PCB using the chip-on-board approach.     

6?10 GHz ultra-wideband CMOS LNA

A two-stage matched ultra-wideband CMOS low noise amplifier (LNA) is presented. The LNA is designed to achieve a low noise figure with high voltage gain. The LNA fabricated in a 0.13 mum CMOS process shows a 3.9 dB average noise figure with a 27 dB voltage gain in the 6-10 GHz frequency band with a power consumption of 14 mW.