General Architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC Intra Frame Transcoding

The latest international video-coding standard H.264/AVC significantly achieves better coding performance compared to prior video coding standards such as MPEG-2 and H.263, which have been widely used in today’s digital video applications. To provide the interoperability between different coding standards, this paper proposes an efficient architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC intra frame transcoding, using the original information such as discrete cosine transform (DCT) coefficients and coded mode type. Low-frequency components of DCT coefficients and a novel rate distortion cost function are used to select a set of candidate modes for rate distortion optimization (RDO) decision. For H.263 and H.264/AVC, a mode refinement scheme is utilized to eliminate unlikely modes before RDO mode decision, based on coded mode information. The experimental results, conducted on JM12.2 with fast C8MB mode decision, reveal that average 58%, 59% and 60% of computation (re-encoding) time can be saved for MPEG-2, H.263, H.264/AVC to H.264/AVC intra frame transcodings respectively, while preserving good coding performance when compared with complex cascaded pixel domain transcoding (CCPDT); or average 88% (a speed up factor of 8) when compared with CCPDT without considering fast C8MB. The proposed algorithm for H.264/AVC homogeneous transcoding is also compared to the simple cascaded pixel domain transcoding (with original mode reuse). The results of this comparison indicate that the proposed algorithm significantly outperforms the mode reuse algorithm in coding performance, with only slightly higher computation.     

Delta-modulation/p.c.m. convertor

A simple and sufficiently accurate digital convertor is suggested that converts a delta sequence of an exponential delta modulator into a sequence of digital numbers. Each number equals the height of the analogue signal at the input of the delta modulator at each moment. The system employs an up-down counter and some logic based on conventional full adders.     

1 /spl mu/m MOSFET VLSI technology. I. An overview

Highlights of various aspects of the technology development are discussed briefly. These include device design, circuit design, hot-electron effects, processing technology, electron-beam lithography, metal silicide interconnections and radiation effects.     

1 /spl mu/m MOSFET VLSI technology. VIII. Radiation effects

For pt.VII see ibid., vol.SC14, no.2, p.291 (1979). The effect of electron-beam radiation on polysilicon-gate MOSFETs is examined. The irradiations were performed at 25 kV in a vector scan electron-beam lithography system at dosages typical of those used to expose electron-beam resists. Two types of studies are reported. In the first type, devices fabricated with optical lithography were exposed to blanket electron-beam radiation after fabrication. In the second, discrete devices from a test chip, fabricated entirely with electron-beam lithography, were used.     

CdTe/Langmuir-film m.i.s. structures

Langmuir films based on cadmium stearate have been successfully deposited on to the surface of p-type CdTe. The measured C/V curves show, for the first time, the accumulation, depletion and weak-inversion regions typical of an ideal device. The G/V curves show a sharp peak in the depletion region at high frequencies which is thought to be due to losses at interface states. An initial estimate of the density yields an average value of 1011 states cm?2.     

B.C.D. serial adder/subtractor

For the pure serial addition or subtraction of binary-coded decimal numbers, a simple network is proposed. It consists of a binary adder and a correction system using another adder. In an arithmetic unit, the position of this adder/subtractor at the beginning of the input/output register simplifies the design.     

1 /spl mu/m MOSFET VLSI technology. VI. Electron-beam lithography

For pt.V see ibid., vol.SC14, no.2, p.275 (1979). The authors discuss the fabrication of 1 /spl mu/m minimum linewidth FET polysilicon-gate devices and circuits, with emphasis on vector-scan electron-beam technology and processing. Different types of 1 /spl mu/m MOSFET chips were written on 57 mm Si wafers using a totally automated electron-beam system. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance between shapes. A novel two-layer positive resist system has been developed to achieve reproducible liftoff profiles over topography and better linewidth control. The final results presented here demonstrate that there are no fundamental barriers to the extension of this work to small dimensions.     

VHF/UHF radar. 1. Characteristics

Low-frequency radars have the potential to counter stealth efforts and detect low-flying targets beyond the horizon. This paper gives an overview of the fundamental properties of radars at metric wavelengths, based on research over the past few years conducted at the German Research Institute for High-Frequency Physics and Radar Techniques (FGAN-FHR). It provides an analysis of radar cross-section to underline the anti-stealth properties of the low-frequency range and presents simulations as well as measurement results to demonstrate the beyond-the-horizon detection and foliage penetration capability of metric waves. Specific clutter properties are highlighted     

Multi/demultiplexing in Gbit/s range using dual gate GaAs m.e.s.f.e.t.s

Multiplexing from 1 to 2 Gbit/s and corresponding demultiplexing from 2 to 1 Gbit/s including clock regeneration and pulse width reduction has been performed using dual gate GaAs m.e.s.f.e.t.s. Circuits and time behaviour of input, clock and output signals are shown.