High‐Sensitivity Floating‐Gate Phototransistors Based on WS2 and MoS2

In recent years, 2D layered materials have been considered as promising photon absorption channel media for next‐generation phototransistors due to their atomic thickness, easily tailored single‐crystal van der Waals heterostructures, ultrafast optoelectronic characteristics, and broadband photon absorption. However, the photosensitivity obtained from such devices, even under a large bias voltage, is still unsatisfactory until now. In this paper, high‐sensitivity phototransistors based on WS₂ and MoS₂ are proposed, designed, and fabricated with gold nanoparticles (AuNPs) embedded in the gate dielectric. These AuNPs, located between the tunneling and blocking dielectric, are found to enable efficient electron trapping in order to strongly suppress dark current. Ultralow dark current (10^?11 A), high photoresponsivity (1090 A W^?1), and high detectivity (3.5 × 10¹¹ Jones) are obtained for the WS₂ devices under a low source/drain and a zero gate voltage at a wavelength of 520 nm. These results demonstrate that the floating‐gate memory structure is an effective configuration to achieve high‐performance 2D electronic/optoelectronic devices.     

Nonvolatile Floating‐Gate Memories Based on Stacked Black Phosphorus–Boron Nitride–MoS2 Heterostructures

Research on van der Waals heterostructures based on stacked 2D atomic crystals is intense due to their prominent properties and potential applications for flexible transparent electronics and optoelectronics. Here, nonvolatile memory devices based on floating‐gate field‐effect transistors that are stacked with 2D materials are reported, where few‐layer black phosphorus acts as channel layer, hexagonal boron nitride as tunnel barrier layer, and MoS₂ as charge trapping layer. Because of the ambipolar behavior of black phosphorus, electrons and holes can be stored in the MoS₂ charge trapping layer. The heterostructures exhibit remarkable erase/program ratio and endurance performance, and can be developed for high‐performance type‐switching memories and reconfigurable inverter logic circuits, indicating that it is promising for application in memory devices completely based on 2D atomic crystals.     

Nonvolatile Ferroelectric Memory Effect in Ultrathin α‐In2Se3

High‐density memory is integral in solid‐state electronics. 2D ferroelectrics offer a new platform for developing ultrathin electronic devices with nonvolatile functionality. Recent experiments on layered α‐In₂Se₃ confirm its room‐temperature out‐of‐plane ferroelectricity under ambient conditions. Here, a nonvolatile memory effect in a hybrid 2D ferroelectric field‐effect transistor (FeFET) made of ultrathin α‐In₂Se₃ and graphene is demonstrated. The resistance of the graphene channel in the FeFET is effectively controllable and retentive due to the electrostatic doping, which stems from the electric polarization of the ferroelectric α‐In₂Se₃. The electronic logic bit can be represented and stored with different orientations of electric dipoles in the top‐gate ferroelectric. The 2D FeFET can be randomly rewritten over more than 10⁵ cycles without losing the nonvolatility. The approach demonstrates a prototype of rewritable nonvolatile memory with ferroelectricity in van der Waals 2D materials.     

Low‐Power Nonvolatile Charge Storage Memory Based on MoS2 and an Ultrathin Polymer Tunneling Dielectric

Low‐power, nonvolatile memory is an essential electronic component to store and process the unprecedented data flood arising from the oncoming Internet of Things era. Molybdenum disulfide (MoS₂) is a 2D material that is increasingly regarded as a promising semiconductor material in electronic device applications because of its unique physical characteristics. However, dielectric formation of an ultrathin low‐k tunneling on the dangling bond‐free surface of MoS₂ is a challenging task. Here, MoS₂‐based low‐power nonvolatile charge storage memory devices are reported with a poly(1,3,5‐trimethyl‐1,3,5‐trivinyl cyclotrisiloxane) (pV3D3) tunneling dielectric layer formed via a solvent‐free initiated chemical vapor deposition (iCVD) process. The surface‐growing polymerization and low‐temperature nature of the iCVD process enable the conformal growing of low‐k (≈2.2) pV3D3 insulating films on MoS₂. The fabricated memory devices exhibit a tunable memory window with high on/off ratio (≈10⁶), excellent retention times of 10⁵ s with an extrapolated time of possibly years, and an excellent cycling endurance of more than 10³ cycles, which are much higher than those reported previously for MoS₂‐based memory devices. By leveraging the inherent flexibility of both MoS₂ and polymer dielectric films, this research presents an important milestone in the development of low‐power flexible nonvolatile memory devices.     

Air‐Stable Cesium Lead Iodide Perovskite for Ultra‐Low Operating Voltage Resistive Switching

CsPbX₃ (X = halide, Cl, Br, or I) all‐inorganic halide perovskites (IHPs) are regarded as promising functional materials because of their tunable optoelectronic characteristics and superior stability to organic–inorganic hybrid halide perovskites. Herein, nonvolatile resistive switching (RS) memory devices based on all‐inorganic CsPbI₃ perovskite are reported. An air‐stable CsPbI₃ perovskite film with a thickness of only 200 nm is successfully synthesized on a platinum‐coated silicon substrate using low temperature all‐solution process. The RS memory devices of Ag/polymethylmethacrylate (PMMA)/CsPbI₃/Pt/Ti/SiO₂/Si structure exhibit reproducible and reliable bipolar switching characteristics with an ultralow operating voltage (<+0.2 V), high on/off ratio (>10⁶), reversible RS by pulse voltage operation (pulse duration < 1 ms), and multilevel data storage. The mechanical flexibility of the CsPbI₃ perovskite RS memory device on a flexible substrate is also successfully confirmed. With analyzing the influence of phase transition in CsPbI₃ on RS characteristics, a mechanism involving conducting filaments formed by metal cation migration is proposed to explain the RS behavior of the memory device. This study will contribute to the understanding of the intrinsic characteristics of IHPs for low‐voltage resistive switching and demonstrate the huge potential of them for use in low‐power consumption nonvolatile memory devices on next‐generation computing systems.     

All‐Polymer Bistable Resistive Memory Device Based on Nanoscale Phase‐Separated PCBM‐Ferroelectric Blends

All polymer nonvolatile bistable memory devices are fabricated from blends of ferroelectric poly(vinylidenefluoride–trifluoroethylene (P(VDF‐TrFE)) and n‐type semiconducting [6,6]‐phenyl‐C61‐butyric acid methyl ester (PCBM). The nanoscale phase separated films consist of PCBM domains that extend from bottom to top electrode, surrounded by a ferroelectric P(VDF‐TrFE) matrix. Highly conducting poly(3,4‐ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) polymer electrodes are used to engineer band offsets at the interfaces. The devices display resistive switching behavior due to modulation of this injection barrier. With careful optimization of the solvent and processing conditions, it is possible to spin cast very smooth blend films (R_rms ≈ 7.94 nm) and with good reproducibility. The devices exhibit high I_on/I_off ratios (≈3 × 10³), low read voltages (≈5 V), excellent dielectric response at high frequencies (?_r ≈ 8.3 at 1 MHz), and excellent retention characteristics up to 10 000 s.     

Large‐Area Schottky Barrier Transistors Based on Vertically Stacked Graphene–Metal Oxide Heterostructures

The fabrication of all‐transparent flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–metal oxide–metal heterostructures and ion gel gate dielectrics is demonstrated. The vertical SB transistor structure is formed by (i) vertically sandwiching a solution‐processed indium‐gallium‐zinc‐oxide (IGZO) semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with a vertical channel through an ion gel. The channel current is modulated by tuning the Schottky barrier height across the graphene–IGZO junction under an applied external gate bias. The ion gel gate dielectric with high specific capacitance enables modulation of the Schottky barrier height at the graphene–IGZO junction over 0.87 eV using a voltage below 2 V. The resulting vertical devices show high current densities (18.9 A cm^?2) and on–off current ratios (>10⁴) at low voltages. The simple structure of the unit transistor enables the successful fabrication of low‐power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large‐area, and room‐temperature deposition of both semiconducting metal oxide and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene‐based future electronics.     

Controllable Shifts in Threshold Voltage of Top‐Gate Polymer Field‐Effect Transistors for Applications in Organic Nano Floating Gate Memory

Organic field‐effect transistor (FET) memory is an emerging technology with the potential to realize light‐weight, low‐cost, flexible charge storage media. Here, solution‐processed poly[9,9‐dioctylfluorenyl‐2,7‐diyl]‐co‐(bithiophene)] (F8T2) nano floating gate memory (NFGM) with a top‐gate/bottom‐contact device configuration is reported. A reversible shift in the threshold voltage (V_Th) and reliable memory characteristics was achieved by the incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative charges (electrons) at the interface between polystyrene and cross‐linked poly(4‐vinylphenol). The F8T2 NFGM showed relatively high field‐effect mobility (µ_FET) (0.02 cm² V^?1 s^?1) for an amorphous semiconducting polymer with a large memory window (ca. 30 V), a high on/off ratio (more than 10⁴) during writing and erasing with an operation voltage of 80 V of gate bias in a relatively short timescale (less than 1 s), and a retention time of a few hours. This top‐gated polymer NFGM could be used as an organic transistor memory element for organic flash memory.     

Optimal Structure for High‐Performance and Low‐Contact‐Resistance Organic Field‐Effect Transistors Using Contact‐Doped Coplanar and Pseudo‐Staggered Device Architectures

A low contact resistance achieved on top‐gated organic field‐effect transistors by using coplanar and pseudo‐staggered device architectures, as well as the introduction of a dopant layer, is reported. The top‐gated structure effectively minimizes the access resistance from the contact to the channel region and the charge‐injection barrier is suppressed by doping of iron(III)trichloride at the metal/organic semiconductor interface. Compared with conventional bottom‐gated staggered devices, a remarkably low contact resistance of 0.1–0.2 kΩ cm is extracted from the top‐gated devices by the modified transfer line method. The top‐gated devices using thienoacene compound as a semiconductor exhibit a high average field‐effect mobility of 5.5–5.7 cm² V^?1 s^?1 and an acceptable subthreshold swing of 0.23–0.24 V dec^?1 without degradation in the on/off ratio of ≈10⁹. Based on these experimental achievements, an optimal device structure for a high‐performance organic transistor is proposed.     

Simultaneous quality improvement of tunneling- and interpoly-oxides of nonvolatile memory devices by NH/sub 3/ and N/sub 2/O nitridation

This brief presents a new nitridation process on a floating poly-Si gate to improve the quality of both tunneling oxide and interpoly-oxide of nonvolatile memories. Three types of poly-Si for a floating gate have been investigated. We found in-situ doped poly-Si shows the best performance in terms of breakdown field, charge-to-breakdown (Q/sub BD/) and trapping rate. The Q/sub BD/ of interpoly-oxide can be reached as high as 35 C/cm/sup 2/. This scheme is very promising for nonvolatile memory devices.     

Printed,Flexible, Organic Nano‐Floating‐Gate Memory: Effects of Metal Nanoparticles and Blocking Dielectrics on Memory Characteristics

The effects of using a blocking dielectric layer and metal nanoparticles (NPs) as charge‐trapping sites on the characteristics of organic nano‐floating‐gate memory (NFGM) devices are investigated. High‐performance NFGM devices are fabricated using the n‐type polymer semiconductor, poly{[N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)} (P(NDI2OD‐T2)), and various metal NPs. These NPs are embedded within bilayers of various polymer dielectrics (polystyrene (PS)/poly(4‐vinyl phenol) (PVP) and PS/poly(methyl methacrylate) (PMMA)). The P(NDI2OD‐T2) organic field‐effect transistor (OFET)‐based NFGM devices exhibit high electron mobilities (0.4–0.5 cm² V^?1 s^?1) and reliable non‐volatile memory characteristics, which include a wide memory window (≈52 V), a high on/off‐current ratio (I_on/I_off ≈ 10⁵), and a long extrapolated retention time (>10⁷ s), depending on the choice of the blocking dielectric (PVP or PMMA) and the metal (Au, Ag, Cu, or Al) NPs. The best memory characteristics are achieved in the ones fabricated using PMMA and Au or Ag NPs. The NFGM devices with PMMA and spatially well‐distributed Cu NPs show quasi‐permanent retention characteristics. An inkjet‐printed flexible P(NDI2OD‐T2) 256‐bit transistor memory array (16 × 16 transistors) with Au‐NPs on a polyethylene naphthalate substrate is also fabricated. These memory devices in array exhibit a high I_on/I_off (≈10^{4 ± 0.85}), wide memory window (≈43.5 V ± 8.3 V), and a high degree of reliability.     

2D TMD Channel Transistors with ZnO Nanowire Gate for Extended Nonvolatile Memory Applications

2D transition metal dichalcogenides (TMDs) have been extensively studied due to their excellent physical properties. Mixed dimensional devices including 2D materials have also been studied, motivated by the possibility of any synergy effect from unique structures. However, only few such studies have been conducted. Here, semiconducting 1D ZnO nanowires are used as thin gate material to support 2D TMD field effect transistors (FETs) and 2D stack‐based interface trap nonvolatile memory. For the trap memory, deep level electron traps formed at the first MoS₂/second MoS₂ stack interface are exploited, since the first MoS₂ is treated in an atomic layer deposition chamber for a short while. On the one hand, a complementary inverter type memory device can also be achieved using a long single ZnO wire as a common gate to simultaneously support both n‐ and p‐channel TMD FETs. In addition, it is found that the semiconducting ZnO nanowire itself operates as an n‐type channel when the TMD materials can become a top‐gate to charge the ZnO channel. It means that 2D (bottom gated) and 1D channel (top gated) FETs are respectively operational in a single device structure. The 1D–2D mixed devices seem deserving broad attention in both aspects of novelty and functionality.     

Multilevel characteristics and operating mechanisms of nonvolatile memory devices based on a floating gate of graphene oxide sheets sandwiched between two polystyrene layers

Nonvolatile organic memory devices were fabricated utilizing a graphene oxide (GO) layer embedded between two polystyrene (PS) layers. Scanning electron microscope images of GO sheets sandwiched between two PS layers showed that the GO sheets were clearly embedded in the PS layers. Capacitance–voltage (C–V) curves of the Al/PS/GO/PS/n-type Si devices clearly showed hysteresis behaviors with multilevel characteristics. The window margin of the nonvolatile memory devices increased from 1 to 7 V with increasing applied sweep voltages from 6 to 32 V. The cycling retention of the ON/OFF switching for the devices was measured by applying voltages between +15 and −15 V. While the capacitance of the memory devices at an ON state have retained as 230 pF up to 10⁴ cycles, that at an OFF state maintained as 16 pF during three times of repeated measurements. The extrapolation of the retention data for the devices maintained up to 10⁶ cycles. The operating mechanisms of the nonvolatile organic memory devices with a floating gate were described by the C–V results and the energy band diagrams.     

Interface‐Engineered Amorphous TiO2‐Based Resistive Memory Devices

Crossbar‐type bipolar resistive memory devices based on low‐temperature amorphous TiO₂ (a‐TiO₂) thin films are very promising devices for flexible nonvolatile memory applications. However, stable bipolar resistive switching from amorphous TiO₂ thin films has only been achieved for Al metal electrodes that can have severe problems like electromigration and breakdown in real applications and can be a limiting factor for novel applications like transparent electronics. Here, amorphous TiO₂‐based resistive random access memory devices are presented that universally work for any configuration of metal electrodes via engineering the top and bottom interface domains. Both by inserting an ultrathin metal layer in the top interface region and by incorporating a thin blocking layer in the bottom interface, more enhanced resistance switching and superior endurance performance can be realized. Using high‐resolution transmission electron microscopy, point energy dispersive spectroscopy, and energy‐filtering transmission electron microscopy, it is demonstrated that the stable bipolar resistive switching in metal/a‐TiO₂/metal RRAM devices is attributed to both interface domains: the top interface domain with mobile oxygen ions and the bottom interface domain for its protection against an electrical breakdown.     

Electrically Driven Random Laser Memory

The first electrically driven random laser diode with nonvolatile resistive random access memory functionality is designed and demonstrated. To illustrate the working principle, a metal–insulator–semiconductor structure based on Pt/MgO/ZnO thin‐film layers is fabricated on indium tin oxide glass. The current–voltage curve of the dual‐function random laser memory (RLM) device exhibits an excellent electrical bistability with a high ON/OFF current ratio (≈10⁷). The random lasing behavior is simultaneously demonstrated by using electrical pumping with the appearance of sharp‐peak emissions and a drastic enhancement of peak intensity. A wide angle‐dependent electroluminescence not only reveals its emitting advantage but also further supports the origin of random lasers. The first proof‐of‐concept presentation of RLM possesses several advantages of dual memory and lasing functions, which enables to open up new avenues to practical applications, such as light emitting memories for electrical and optical communication. This new horizon for the realization of all optical memories should therefore be able to attract academic as well as industrial interests. It is stressed here that the electrical reading of conventional memory array is usually in serial sequence, which limits the maximum data throughput. This hurdle can be overcome by optically readable memory devices.     

DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.     

High‐Speed,Low‐Voltage,and Environmentally Stable Operation of Electrochemically Gated Zinc Oxide Nanowire Field‐Effect Transistors

Single‐crystal, 1D nanostructures are well known for their high mobility electronic transport properties. Oxide‐nanowire field‐effect transistors (FETs) offer both high optical transparency and large mechanical conformability which are essential for flexible and transparent display applications. Whereas the “on‐currents” achieved with nanowire channel transistors are already sufficient to drive active matrix organic light emitting diode (AMOLED) displays; it is shown here that incorporation of electrochemical‐gating (EG) to nanowire electronics reduces the operation voltage to ≤2 V. This opens up new possibilities of realizing flexible, portable, transparent displays that are powered by thin film batteries. A composite solid polymer electrolyte (CSPE) is used to obtain all‐solid‐state FETs with outstanding performance; the field‐effect mobility, on/off current ratio, transconductance, and subthreshold slope of a typical ZnO single‐nanowire transistor are 62 cm²/Vs, 10⁷, 155 μS/μm and 115 mV/dec, respectively. Practical use of such electrochemically‐gated field‐effect transistor (EG FET) devices is supported by their long‐term stability in air. Moreover, due to the good conductivity (≈10^?2 S/cm) of the CSPE, sufficiently high switching speed of such EG FETs is attainable; a cut‐off frequency in excess of 100 kHz is measured for in‐plane FETs with large gate‐channel distance of >10 μm. Consequently, operation speeds above MHz can be envisaged for top‐gate transistor geometries with insulator thicknesses of a few hundreds of nanometers. The solid polymer electrolyte developed in this study has great potential in future device fabrication using all‐solution processed and high throughput techniques.     

N-type polymeric organic flash memory device: Effect of reduced graphene oxide floating gate

In this paper, n type nonvolatile memory devices were fabricated by implanting a bilayer (rGO sheets/Au NP) floating gates, using n-type polymer semiconductor, poly {[N, N′ bis (2octyldodecyl) - naphthalene-1, 4, 5, 8 - bis (dicarboximide)-2,6-diyl] – alt - 5,5′ - (2, 2′ bithiophene)} [P(NDI2OD-T2)n]. In the developed organic field effect transistor memory devices, electrons are trapped/detrapped in rGO sheet/Au NP's nano-floating gates by controlling the charge carrier density in the active layer through back gate bias control. The devices showed interesting non-volatile memory properties with a large memory window of ∼34 V, a programming-reading-erasing cycling endurance of 103 times and most importantly, an improved retention time characteristics estimated by extrapolation (longer than the technological requirement of commercial memory devices (>10 years)). This approach provides a great potential for fabricating high-performances organic nano-floating gate memory devices and opens up a new way for the development of next-generation non-volatile memory devices.     

Inch‐Size Single Crystal of a Lead‐Free Organic–Inorganic Hybrid Perovskite for High‐Performance Photodetector

Large‐size crystals of organic–inorganic hybrid perovskites (e.g., CH₃NH₃PbX₃, X = Cl, Br, I) have gained wide attention since their spectacular progress on optoelectronic technologies. Although presenting brilliant semiconducting properties, a serious concern of the toxicity in these lead‐based hybrids has become a stumbling block that limits their wide‐scale applications. Exploring lead‐free hybrid perovskite is thus highly urgent for high‐performance optoelectronic devices. Here, a new lead‐free perovskite hybrid (TMHD)BiBr₅ (TMHD = N,N,N,N‐tetramethyl‐1,6‐hexanediammonium) is prepared from facile solution process. Emphatically, inch‐size high‐quality single crystals are successfully grown, the dimensions of which reach up to 32 × 24 × 12 mm³. Furthermore, the planar arrays of photodetectors based on bulk lead‐free (TMHD)BiBr₅ single crystals are first fabricated, which shows sizeable on/off current ratios (≈10³) and rapid response speed (τ_rise = 8.9 ms and τ_decay = 10.2 ms). The prominent device performance of (TMHD)BiBr₅ strongly underscores the lead‐free hybrid perovskite single crystals as promising material candidates for optoelectronic applications.     

Graphene Solution‐Gated Field‐Effect Transistor Array for Sensing Applications

Graphene, with its unique combination of physical and electronic properties, holds great promise for biosensor and bioelectronic applications. In this respect, the development of graphene solution‐gated field‐effect transistor (SGFET) arrays capable of operation in aqueous environments will establish the real potential of graphene in this rapidly emerging field. Here, we report on a facile route for the scalable fabrication of such graphene transistor arrays and provide a comprehensive characterization of their operation in aqueous electrolytes. An on‐chip structure for Hall‐effect measurements allows the direct determination of charge carrier concentrations and mobilities under electrolyte gate control. The effect of the solution‐gate potential on the electronic properties of graphene is explained using a model that considers the microscopic structure of water at the graphene/electrolyte interface. The graphene SGFETs exhibit a high transconductance and correspondingly high sensitivity, together with an effective gate noise as low as tens of μV. Our study demonstrates that graphene SGFETs, with their facile technology, high transconductance, and low noise promise to far outperform state‐of‐the‐art Si‐based devices for biosensor and bioelectronic applications.