Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

40‐TFLOPS artificial intelligence processor with function‐safe programmable many‐cores for ISO26262 ASIL‐D

The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function‐safe architecture is proposed for a fault‐tolerance system such as an electronics system for autonomous cars. The general‐purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self‐recovering cache and dynamic lockstep function. The function‐safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28‐nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function‐safe design can have ISO26262 ASIL‐D with the single‐point fault‐tolerance rate of 99.64%.     

High energy‐efficient and privacy‐preserving secure data aggregation for wireless sensor networks

An efficient data process technology is needed for wireless sensor networks composed of many sensors with constrained communication, computational, and memory resources. Data aggregation is presented as an efficient and significant method to reduce transmitted data and prolong lifetime for wireless sensor networks. Meanwhile, many applications require preserving privacy for secure data aggregation. In this paper, we propose a high energy‐efficient and privacy‐preserving scheme for secure data aggregation. Because of the importance of communication overhead and accuracy, our scheme achieves less communication overhead and higher data accuracy besides providing for privacy preservation. For extensive simulations, we evaluate and conclude the performance of our high energy‐efficient and privacy‐preserving scheme. The conclusion shows that the high energy‐efficient and privacy‐preserving scheme provides better privacy preservation and is more efficient than existing schemes. Copyright © 2012 John Wiley & Sons, Ltd.     

Hopfield neural‐network‐based dynamic resource allocation scheme for non‐real‐time traffic in wireless networks

Dynamic resource allocation (DRA) plays a fundamental role in current and future wireless networks, including 3G systems. In this paper, a scheduling DRA scheme for non‐real‐time (NRT) packet services in wireless system is proposed based on the use of Hopfield neural networks (HNN). The scheme exploits the fast response time of HNN for solving NP optimization problems and has been particularized for the downlink transmission in a UMTS system, although it could be easily extended to any other radio access technology. The new DRA scheme follows a delay‐centric approach, since it maximizes the overall system resource utilization while minimizing the packet delay. Simulation results confirm that the proposed HNN‐based DRA scheme is effective in supporting different types of NRT services, while achieving efficient utilization of radio resources. Copyright © 2008 John Wiley & Sons, Ltd.     

Integrating the self‐growing concept in a self‐organizing wireless network for topology optimization

The concept of self‐organizing networks is considered one of the most promising approaches for the efficient management of future wireless networks that will support a large number of nodes and a plethora of services with diverse characteristics. Today, different types of networks (e.g. WLANs, wireless sensor networks) are deployed to serve different needs but do not interoperate. Their possible loose integration will provide opportunities that could be exploited through collaborative approaches to devise novel solutions to extend the capabilities and improve the performance of these networks. The self‐growing paradigm addresses this challenge by extending network nodes to dynamically evolve in terms of purpose and operational features. In this paper we describe the CONSERN architecture, which targets the realization of the self‐growing concept in the context of self‐organized networks. To test our ideas we designed and implemented a WLAN topology optimization scheme that provides the best coverage at a minimum energy consumption, through dynamic access point (AP) deactivation and reactivation. Using self‐growing mechanisms and typical motion detectors we present how the operation of the proposed topology optimization mechanism can be improved. The reduced energy consumption attained under the proposed scheme at the AP side, as well as the efficient utilization of network resources, are evaluated via a proof‐of‐concept implementation that we have deployed in a real office environment that consists of WLAN APs and motion sensors. Copyright © 2014 John Wiley & Sons, Ltd.     

Spectral efficiency improvement with SISO and SIMO in M‐QAM over millimeter‐wave links

This paper proposes a spectral efficiency improvement technique for millimeter wave (mmWave) links. The proposed technique provides an efficient utilization of the mmWave link capacity. This technique is applied in three cases the single‐input single‐output (SISO), single‐input multiple‐output (SIMO) with the maximal ratio combining and with the equal gain combining. The M‐ary quadrature amplitude modulation scheme is used in our work. The power series expansion is used for deriving closed‐form expressions for bit error rate (BER) performances in all studied cases. The BER closed‐form expressions are confirmed by the numerical solution of the integral equations. The simulation results show that a high spectral efficiency can be accomplished by the proposed technique. As well as the derived expressions closely match with the numerical solution of integration expressions at different values of modulations order the Rician factor. For instance, the spectral efficiency gain achievement is 8 at signal‐to‐noise ratio (SNR) equals 34 dB in the case of SISO system whereas in the case of SIMO system, the same gain is achieved at SNR equals 24 dB. As well as the BER performance is enhanced from 1.188 × 10^?4, 7.112 × 10^?4, 4.164 × 10^?3, and 3.286 × 10^?2 to 8.717 × 10^?16, 1.119 × 10^?12, 1.308 × 10^?9, and 4.905 × 10^?6 for M = 4, 16, 64, and 256, respectively, at SNR equals 30 dB.     

Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high‐performance shared‐memory switches

Burst traffic is a common traffic pattern in modern IP networks, and it may lead to the unfairness problem and seriously degrade the performance of switches and routers. From the perspective of switching mechanism, the majority of commercial switches adopt the on‐chip shared‐memory switching architecture, and high‐speed packet buffer with efficient queue management is required to deal with the unfairness and congestion problem. In this paper, the performance of a shared‐private buffer management scheme is analyzed in detail. In the proposed scheme, the total memory space is split into shared area and private area. Each output port has a private memory area that cannot be used by other ports. The shared area is completely shared among all output ports. A theoretical queuing model of the proposed scheme is formulated, and closed‐form formulas for multiple performance parameters are derived. Through the numerical studies, we demonstrate that a nearly optimal buffer partition policy can be obtained by setting an equally small amount of private area for each queue. This work is validated by simulations as well as hardware experiments. Software simulations show that the proposed scheme performs better than existing methods, and packet dropping caused by burst traffic can be significantly reduced. Besides, a prototype of the buffer management module is implemented and evaluated in field programmable gate array platform. The evaluation shows that the proposed scheme can ensure the efficiency and fairness while keeping a high throughput in real workload.     

AB9: A neural processor for inference acceleration

We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteristics inherent in neural networks while providing fast access to large on‐chip memory. Complementing the hardware is an intuitive and user‐friendly development environment that includes a simulator and an implementation flow that provides a high degree of programmability with a short development time. Along with a 40‐TFLOP STC that includes 32k arithmetic units and over 36 MB of on‐chip SRAM, our baseline implementation of AB9 consists of a 1‐GHz quad‐core setup with other various industry‐standard peripheral intellectual properties. The acceleration performance and power efficiency were evaluated using YOLOv2, and the results show that AB9 has superior performance and power efficiency to that of a general‐purpose graphics processing unit implementation. AB9 has been taped out in the TSMC 28‐nm process with a chip size of 17 × 23 mm². Delivery is expected later this year.     

Energy and spectral efficiency trade‐off for the downlink OFDM‐distributed antenna systems

This paper investigates an energy efficient optimization scheme for the downlink multiuser OFDM‐distributed antenna systems. We adopt a multicriteria optimization method to offer a systematic study on the relationship between spectral efficiency (SE) and energy efficiency (EE). First, we transform the energy efficient optimization problem with high complexity into a simpler downlink multiuser OFDM problem. Then, using the weighted sum method in multicriteria optimization, an optimal energy efficient scheme is presented to allocate the available power to balance the trade‐off between SE and EE efficiently. Simulation results demonstrate that the energy efficient scheme is effective, and there existed a trade‐off between SE and EE in the downlink multiuser OFDM‐distributed antenna systems. Copyright © 2013 John Wiley & Sons, Ltd.     

Concatenation of polar codes with three‐dimensional parity check (3D‐PC) codes to improve error performance over fading channels

In this paper, we concatenated of three‐dimensional parity check (3D‐PC) block and polar codes for improving error correction performance and bit error rate (BER). Three different sizes of 3D parity check blocks (4 × 4 × 4, 8 × 8 × 8, and 16 × 16 × 16) are used for polar code concatenation. The 4 × 4 × 4 block returns the best performance, but higher complexity of decoder is needed unlikely. The 8 × 8 × 8 has returned acceptable complexity and good performacne. The complexity of decoder is less in the case of 16 × 16 × 16 with slight performance. The performance of the 3D‐PC is reduced when the codewords length is increased. The experiment considered the presence of additive white Gaussian noise (AWGN) with Rayleigh and Rician fading environments. 3D‐PC and polar code concatenation is more precise with codewords of short length, whereas there is insufficient concatenation accuracy with longer codewords. The outcomes of this study contain comparison between AWGN, Rayleigh, and Rician environments. The AWGN is noticed to have a lesser negative impact on the performance of code. Furthermore, increasing the code length may slightly fill the gap of performance between the concatenated and none concatenated polar codes due to the impact of code length on parity check code performance. Simulation results showed the coding performance in case of the polar code with concatenation and without concatenation for different code lengths. Generally, the 3D‐PC polar code concatenation is drawn the optimal result in AWGN environments.     

A bridged architecture for two‐way data communications over cable TV networks

The traditional cable TV network has recently emerged as a promising infrastructure for high‐speed data communications such as the Internet and multimedia. A cable TV network may cover a wide range of geographical area that thousands of subscribers live in or work at. However, this broad service range also brings some problems such as bandwidth congestion due to too many users, and the overhead in the design of access protocol. This article presents a bridged architecture that can increase the bandwidth re‐usability and data transmission reliability over the cable TV network. It first describes the method of bridging the cable TV networks and then gives the design of a cable bridge which partitions the cable segment into several subnetworks. For load‐balancing and fairness among subnetworks, a prioritized queuing scheme with a numerical analysis will be also described. Copyright © 2000 John Wiley & Sons, Ltd.     

Multi‐granular,multi‐purpose and multi‐Gb/s monitoring on off‐the‐shelf systems

As an attempt to make network managers’ life easier, we present M³Omon , a system architecture that helps to develop monitoring applications and perform network diagnosis. M³Omon behaves as an intermediate layer between the traffic and monitoring applications that provides advanced features, high performance and low cost. Such advanced features leverage a multi‐granular and multi‐purpose approach to the monitoring problem. Multi‐granular monitoring provides answers to tasks that use traffic aggregates to identify an event, and requires either flow records or packet data or even both to understand it and, eventually, take convenient countermeasures. M³Omon provides a simple API to access traffic simultaneously at several different granularities, i.e. packet‐level, flow‐level and aggregate statistics. The multi‐purposed design of M³Omon allows not only performing tasks in parallel that are specifically targeted to different traffic‐related purposes (e.g. traffic classification and intrusion detection) but also sharing granularities between applications, e.g. several concurrent applications fed from flow records that are provided by M³Omon . Finally, the low‐cost characteristic is brought by off‐the‐shelf systems (the combination of open‐source software and commodity hardware) and the high performance is achieved thanks to modifications in the standard NIC driver, low‐level hardware interaction, efficient memory management and programming optimization. Copyright © 2014 John Wiley & Sons, Ltd.     

Real‐time performance evaluation of asynchronous time division traffic‐aware and delay‐tolerant scheme in ad hoc sensor networks

Wireless infrastructureless networks demand high resource availability with respect to the progressively decreasing energy consumption. A variety of new applications with different service requirements demand fairness to the service provision and classification, and reliability in an end‐to‐end manner. High‐priority packets are delivered within a hard time delay bound whereas improper power management in wireless networks can substantially degrade the throughput and increase the overall energy consumed. In this work a new scheme is being proposed and evaluated in real time using a state‐based layered oriented architecture for energy conservation (EC). The proposed scheme uses the node's self‐tuning scheme, where each node is assigned with a dissimilar sleep and wake time, based on traffic that is destined for each node. This approach is based on stream's characteristics with respect to different caching behavioral and storage‐capacity characteristics, and considers a model concerning the layered connectivity characteristics for enabling the EC mechanism. EC characteristics are modeled and through the designed tiered architecture the estimated metrics of the scheme can be bounded and tuned into certain regulated values. The real‐time evaluation results were extracted by using dynamically moving and statically located sensor nodes. A performance comparison is done with respect to different data traffic priority classifications following a real‐time asymmetrical transmission channel. Results have shown the scheme's efficiency in conserving energy while the topology configuration changes with time. Copyright © 2009 John Wiley & Sons, Ltd.     

W‐Band MMIC chipset in 0.1‐μm mHEMT technology

We developed a 0.1‐μm metamorphic high electron mobility transistor and fabricated a W‐band monolithic microwave integrated circuit chipset with our in‐house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz–108 GHz band and achieved excellent spurious suppression. A low‐noise amplifier (LNA) with a four‐stage single‐ended architecture using a common‐source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W‐band image‐rejection mixer (IRM) with an external off‐chip coupler was also designed. The IRM provided a conversion gain of 13 dB–17 dB for RF frequencies of 80 GHz–110 GHz and image‐rejection ratios of 17 dB–19 dB for RF frequencies of 93 GHz–100 GHz.     

Performance modeling and optimization of multiple‐objective cross‐layer design in multi‐flow ad‐hoc networks

In ad‐hoc wireless networks, to achieve good performance, multiple parameters need to be optimized jointly. However, existing literature lacks a design framework that investigates the synchronic impact of several parameters on overall system performance. Among several design parameters, energy conservation, end‐to‐end delay minimization, and improved throughput are considered most important for efficient operation of these networks. In this paper, we propose a novel scheme for multiple‐objective cross‐layer optimization capable of optimizing all these performance objectives simultaneously for reliable, energy‐efficient, and timely transmission of continuous media information across the network. The three global criteria considered for optimization are incorporated in a single programming problem via linear scalarization. Besides, we employ standard convex optimization method and Lagrangian technique to solve the proposed problem to seek optimality. Extensive simulation results are generated accounting for several topologies with multiple concurrent flows in the network. These results are used to validate the analytical results and demonstrate the efficiency of the proposed optimization model. Efficiency of the model is verified by finding the set of Pareto‐optimal solutions plotted in three‐dimensional objective space. These solution points constituting the Pareto front are used as the best possible balance points among maximum throughput, maximum residual energy, and least network delay. Finally, to emphasize the effectiveness and supremacy of our proposed multiple‐objective cross‐layer design scheme, we compare it with the conventional multiple‐objective genetic algorithm. Simulation results demonstrate that our method provides significant performance gain over the genetic algorithm approach in terms of the above specified three objectives.     

An efficient load balancing method for ad hoc networks

Routing is the most basic and essential operation of any ad hoc network. A mobile ad hoc network presents many challenges, because of the severe resource limitations such as dynamic and varying topology, lack of centralized control, insecure medium, and limited battery power, among others. Therefore, optimization and conservation is the key to success of any ad hoc network operation. In this paper, we propose and define 2 new metrics for ad hoc networks: bandwidth utilization ratio and load index. These metrics can be used as an indicator to measure and monitor the network usability and to improve its efficiency by efficient load distribution. They can be used to predict the additional load that can be accommodated in the network, without causing any congestion or overflows. We also propose a new load balancing routing scheme for ad hoc networks, called efficient load balancing method. This method tries to offset the load on different paths using load index as a metric. Load index is defined as a measure of a node's degree of involvement in the message routing process, which is indicative of its load. To make this algorithm efficient, we limit our routes to a few efficient ones only. This number of alternate routes used, out of the pool of all available routes, is defined as degree of distribution. Simulation results adequately prove the efficiency of proposed method, vis‐à‐vis 2 other load balancing approaches, and these are verified statistically at 99% confidence interval. A p × q factorial design is used to verify that simulation results are the actual measurements and not due to some unknown errors.     

Bandwidth Optimized and High Performance Interpolation Architecture in Motion Compensation for H.264/AVC HDTV Decoder

In this paper, we present high performance motion compensation architecture for H.264/AVC HDTV decoder. The bottleneck of efficient motion compensation implementation primarily rests on the high memory bandwidth demand and six-tap fractional interpolation complexity. To solve the bottleneck for H.264/AVC HD applications, three combined bandwidth optimization strategies are proposed to minimize the memory bandwidth for MB-based decoding process. To improve the interpolation hardware utilization and reduce the interpolation cycles, an interpolation classification scheme is proposed. By classifying the fifteen fractional pixels into five types and processing correspondingly, the interpolation cycles decrease significantly. A direct mapping memory cache characterized with circular addressing, byte-aligned addressing and horizontal and vertical parallel access is designed to support the proposed scheme. The hardware of proposed motion compensation is implemented at 100 M with 31.841 K logic gates, averagely 70–80% reduced memory bandwidth can be offered and the interpolation hardware can be fully utilized and interpolate one MB within 304 cycles, which can satisfy the real time constraint for H.264/AVC HD (1,920 × 1,088) 30 fps decoder. The design is implemented under UMC 0.18 μm technology, and the synthesis results and comparisons are shown.

Extending P2PMesh: topology‐aware schemes for efficient peer‐to‐peer data sharing in wireless mesh networks

Wireless mesh networks (WMNs) have emerged as a promising technology that provides low‐cost broadband access to the Internet for fixed and mobile wireless end users. An orthogonal evolution in computer networking has been the rise of peer‐to‐peer (P2P) applications such as P2P data sharing. It is of interest to enable effective P2P data sharing in this type of networks. Conventional P2P data sharing systems are not cognizant of the underlying network topology and therefore suffer from inefficiency. We argue for dual‐layer mesh network architecture with support from wireless mesh routers for P2P applications. The main contribution of this paper is P2PMesh: a topology‐aware system that provides combined architecture and efficient schemes for enabling efficient P2P data sharing in WMNs. The P2PMesh architecture utilizes three schemes: (i) an efficient content lookup that mitigates traffic load imbalance at mesh routers; (ii) an efficient establishment of download paths; and (iii) a data transfer protocol for multi‐hop wireless networks with limited capacity. We note here that the path establishment and data transfer schemes are specific to P2P traffic and that other traffic would use routes determined by the default routing protocol in the WMN. Simulation results suggest that P2PMesh has the potential to improve the performance of P2P applications in a wireless multi‐hop setting; specifically, we focused on data sharing, but other P2P applications can also be supported by this approach. Copyright © 2011 John Wiley & Sons, Ltd.     

A Viterbi Decoder with Efficient Memory Management

This paper proposes a new architecture for a Viterbi decoder with an efficient memory management scheme. The trace‐back operation is eliminated in the architecture and the memory storing intermediate decision information can be removed. The elimination of the trace‐back operation also reduces the number of operation cycles needed to determine decision bits. The memory size of the proposed scheme is reduced to 1/(5×constraint length) of that of the register exchange scheme, and the throughput is increased up to twice that of the trace‐back scheme. A Viterbi decoder complying with the IS‐95 reverse link specification is designed to verify the proposed architecture. The decoder has a code rate of 1/3, a constraint length of 9, and a trace‐forward depth of 45.     

A 9‐Bit 80‐MS/s CMOS Pipelined Folding A/D Converter with an Offset Canceling Technique

A 9‐bit 80‐MS/s CMOS pipelined folding analog‐to‐digital converter employing offset‐canceled preamplifiers and a subranging scheme is proposed to extend the resolution of a folding architecture. A fully differential dc‐decoupled structure achieves high linearity in circuit design. The measured differential nonlinearity and integral nonlinearity of the prototype are ×0.6 LSB and ×1.6 LSB, respectively.