基于OOPN的嵌入式系统的建模研究与实现

本文结合了面向对象和Petri网两种建模方法的优点，提出了一种新的面向对象Petri网的建模方法。主要研究了面向对象Petri网方法在嵌入式系统设计中的具体应用，并通过实验对该方法进行了正确性论证以及资源分配情况的定量分析。该方法为嵌入式系统的设计提出了一种行之有效的形式化分析方法，使得复杂的嵌入式系统描述更加模块化，具有可重用性，大大提高了嵌入式系统建模和分析的效率。     

基于分层思想的基本通信系统CPN建模

针对通信系统建模复杂度高、可靠性差、模型缺乏形式化验证方法以及可重用性差的问题,提出一种基于分层思想,并结合面向对象的概念,利用着色Petri网(CPN)对基本通信系统进行建模的方法。该方法融合CPN和面向对象技术的优点,从形式化、可视化的角度描述基本通信系统的运行过程。以一个简单的基本通信系统为例进行建模,证明该模型与实际系统中的对象可以相互对应,易于理解和实现。     

一种嵌入式系统设计的建模方法研究

针对在嵌入式系统设计中,目前常用的VHDL建模方法方法存在不易理解、模型描述困难、工作量大的问题,UML建模方法存在模型需形式化、验证难等问题,提出了一种基于SpecCharts语言的嵌入式系统建模方法--使用SpecCharts语言语法、文字和图形相结合来描述嵌入式系统,能满足嵌入式系统设计的描述要求,建模效率是VHDL方法的2.82倍,是UML方法的1.25倍,并且具有容易理解、容易描述、能利用VHDL的支撑工具直接进行模拟验证、建模工作量小等优点,较好地解决了嵌入式系统设计建模中存在的上述问题,有较高的实用价值.     

嵌入式VOIP系统中ASN.1编解码器的实现

抽象语法描述ASN.1已经被广泛地运用于协议通信。在VOIP应用中,同样也要用到ASN.1编解码。但是由于H.323协议栈本身的asn描述文件较大,使得传统的ASN.1编解码方案在资源有限的嵌入式系统中并不适用。文章在实际开发项目的基础上,提出了一个适用于嵌入式系统的解决方案。     

嵌入式系统数据缓存机制的形式化分析

嵌入式系统在高速通信时通常需要设计缓存机制以保证数据不会丢失,以某嵌入式系统为例,介绍了该系统的硬件及软件平台的设计,利用模型检查工具SPIN对该系统的数据缓存机制进行形式化建模,并利用时态逻辑公式LTL描述了该系统待验证属性,验证结果表明,该缓存机制满足设计需求,为嵌入式系统数据交互设计提供了严密的研究论证方法.     

基于带抑制弧的Petri网表示的嵌入式系统模型的子网化简

基于Petri网表示的嵌入式系统PRES+(Petri net based Representation for Embedded Systems)模型可以描述实时嵌入式系统。为了提高PRES+的建模能力,将抑制弧加入PRES+模型中,得到基于带抑制弧的Petri网表示的嵌入式系统PIRES+(Petri net with Inhibitor arcs based Representation for Embedded Systems)模型。PIRES+模型提高了建模和验证复杂嵌入式系统的能力,但是在建模和验证过程中存在状态空间爆炸问题。为了缓解这一问题,提出两种PIRES+模型的子网的化简规则,使得简化后的模型与原模型具有相同的可达性、实时性和功能性。     

UML在实时系统中的应用研究

UML是最广泛使用的面向对象建模语言,是可视化面向对象系统的建模方法.针对嵌入式系统设计和开发的特点,文中描述了一种将时间组件融入到UML建模中的方法,把时间特性从系统中分离出来.用UML对嵌入式实时系统进行面向对象分析与设计,并以冰箱温度平衡器系统为例,建立了需求分析、静态结构模型和动态行为模型,该方法能够有效地提高开发效率、改善设计质量.     

国民经济动员仿真演练仿真概念建模研究

国民经济动员仿真演练是一个复杂的HLA分布式交互仿真系统,为解决系统仿真概念建模问题,首先针对动员仿真演练建模要素进行分析,借鉴军事仿真概念建模思想,提出CMMS的动员仿真演练分层概念模型逻辑结构.其次,对于工作流模式,提出概念模型形式化描述方法,以及慨念模型校核规则,为管理部门各单位提供仿真训练服务.通过建立形式化概念模型及其校核方法,能有效加强动员领域专家与仿真技术专家之间的沟通效果,并为系统建模与仿真互操作、重用、质量等提供有力保证.     

层次建模分析方法在C4ISR系统中的应用

C4ISR系统是一个规模庞大、层次分明的离散动态系统。文章提出了一种面向C4ISR系统的UML和Petri网结合的建模分析方法。该方法采用从上到下的层次分析方法。用扩展的UML模型对系统组织结构和系统的静态特征进行描述,用扩展的Petri网模型描述和分析系统动态特性,通过相应的规则将Petri网模型转化成状态图和序列图。新方法可以对系统要求进行验证,同时还可以编程实现。最后通过该方法,对一个C4ISR系统进行了建模分析。     

一种用UML和SystemC进行嵌入式系统的系统级建模的方法

本文用UML建模工具RationalRose设计了果蔬清洗机的嵌入式系统UML模型,然后再以UML模型为蓝本,用可执行的SystemC语言对该系统进行系统级描述.论文同时给出了系统的最终描述结果,并运行得出了仿真结果.     

A characterization of the stochastic process underlying astochastic Petri net

Stochastic Petri nets (SPN's) with generally distributed firing times can model a large class of systems, but simulation is the only feasible approach for their solution. We explore a hierarchy of SPN classes where modeling power is reduced in exchange for an increasingly efficient solution. Generalized stochastic Petri nets (GSPN's), deterministic and stochastic Petri nets (DSPN's), semi-Markovian stochastic Petri nets (SM-SPN's), timed Petri nets (TPN's), and generalized timed Petri nets (GTPN's) are particular entries in our hierarchy. Additional classes of SPN's for which we show how to compute an analytical solution are obtained by the method of the embedded Markov chain (DSPN's are just one example in this class) and state discretization, which we apply not only to the continuous-time case (PH-type distributions), but also to the discrete case     

Designing and modeling cyberworlds using the incrementally modular abstraction hierarchy based on homotopy theory

For designing and modeling complicated and sophisticated systems such as cyberworlds, their mathematical foundation is critical. To realize it, two important properties called the homotopy lifting property (HLP) and homotopy extension property (HEP) are applied for designing and modeling a system in a bottom-up way and a top-down way, respectively. In this paper, an enterprise system and a real-time embedded system are considered as important socially emerging cases of cyberworlds, where the π-calculus processes for describing these behaviors formally, a Petri net for explaining process interactions, and XMOS XC programs are modeled and designed by our approach. The spaces in both properties are specified by the incrementally modular abstraction hierarchy by climbing down the abstraction hierarchy from the most abstract homotopy level to the most specific view level, while keeping invariants such as homotopy equivalence and topological equivalence.     

Liveness and Boundedness Preservations of Sharing Synthesis of Petri Net Based Representation for Embedded Systems

Petri net based Representation for Embedded Systems (PRES+) is an outstanding methodology for analysis, modeling and verification of embedded systems. State space explosion is an awful problem for PRES+ to model and analyze large complex embedded systems. In order to solve this problem, we concern with a method for expending PRES+ model by using synthesis approach. A kind of sharing synthesis operation for PRES+ is proposed in this paper. Under some conditions liveness and boundedness will be preserved by using this sharing synthesis approach. An applicable example in the form of an embedded control system illustrates the useful of our synthesis method. These results can be nicely used to investigate dynamic properties of large embedded systems.     

基于BIP框架的DPU系统建模与验证

DPU(data process unit,数据处理单元)是嵌入式系统中的一个典型组件,被广泛应用于太空领域,它在层次化的嵌入式系统架构中起到承上启下的作用。保证这类安全攸关系统可靠性的主要方法包括冗余容错、测试和仿真。近年来,形式化方法作为确保可靠性的一种重要补充,得到了广泛的关注。BIP(behavior interaction priority)是一个通用的系统级形式化建模框架,支持层次化和模块化,包含一套支持建模、模拟和验证的工具集。给出了一种基于BIP框架对DPU进行系统级建模与验证的一般方法,总结了一套使用BIP框架对DPU建模应遵循的原则及技巧。以航天领域一个真实DPU系统为例,系统地对方法、原则和技巧进行了介绍。通过该方法,找出了使用传统方法难以发现的错误。实践表明,该方法具有很好的可复用性和可扩展性,是确保系统可靠性的有益补充。     

Propagation of conic model uncertainty in hierarchical systems

Conic sectors are used for analysis of stability and modeling uncertainty propagation in interconnected systems with a hierarchical structure. For large systems that can be readily decomposed into sparsely interconnected groups subsystems, sub-subsystems, sub-sub-subsystems, etc., analysis is greatly facilitated: formulas for conic uncertainty propagation and stability analysis are applied successively to the various groups, beginning at the bottom of the hierarchy and moving up one level at a time. At each level of the hierarchy the results both test stability and yield tight cone bounds on the modeling uncertainty in terms of the cone parameters at the level immediately below.     

智能机器人系统建模的新理论─—环递阶模型理论

本文走从语言文字描述到符号化再到形式化的崭新道路来探索智能机器人系统的建模问题。首先，为智能机器人系统建立了更全面、确切的语言文字描述，然后，通过直现地符号化，为智能机器人系统提出并建造成了一种新型的结构模型，命名为环递阶模型，最后，利用形式语言理论，将环递阶模型形式化，从而，首次将智能机器人系统整体形式化地建模成了一种上下文无关文法，为智能机器人系统的建模问题开发成了一种解析的框架。形成了一种新的理论，命名为环递阶模型理论。     

Property Preservation of Petri Synthesis Net Based Representation for Embedded Systems

Embedded systems have numerous applications in everyday life.Petri-net-based representation for embedded systems(PRES+)is an important methodology for the modeling and analysis of these embedded systems.For a large complex embedded system,the state space explosion is a difficult problem for PRES+to model and analyze.The Petri net synthesis method allows one to bypass the state space explosion issue.To solve this problem,as well as model and analyze large complex systems,two synthesis methods for PRES+are presented in this paper.First,the property preservation of the synthesis shared transition set method is investigated.The property preservation of the synthesis shared transition subnet set method is then studied.An abstraction-synthesis-refinement representation method is proposed.Through this representation method,the synthesis shared transition set approach is used to investigate the property preservation of the synthesis shared transition subnet set operation.Under certain conditions,several important properties of these synthetic nets are preserved,namely reachability,timing,functionality,and liveness.An embedded control system model is used as an example to illustrate the effectiveness of these synthesis methods for PRES+.     

A prototyping language for real-time software

PSDL is a language for describing prototypes of real-time software systems. It is most useful for requirements analysis, feasibility studies, and the design of large embedded systems. PSDL has facilities for recording and enforcing timing constraints, and for modeling the control aspects of real-time systems using nonprocedural control constraints, operator abstractions, and data abstractions. The language has been designed for use with an associated prototyping methodology. PSDL prototypes are executable if supported by a software base containing reusable software components in an underlying programming language (e.g. Ada)     

A queueing theoretic approach for performance evaluation of low-power multi-core embedded systems

With Moore’s law supplying billions of transistors on-chip, embedded systems are undergoing a transition from single-core to multi-core to exploit this high transistor density for high performance. However, the optimal layout of these multiple cores along with the memory subsystem (caches and main memory) to satisfy power, area, and stringent real-time constraints is a challenging design endeavor. The short time-to-market constraint of embedded systems exacerbates this design challenge and necessitates the architectural modeling of embedded systems to reduce the time-to-market by expediting target applications to device/architecture mapping. In this paper, we present a queueing theoretic approach for modeling multi-core embedded systems that provides a quick and inexpensive performance evaluation both in terms of time and resources as compared to the development of multi-core simulators and running benchmarks on these simulators. We verify our queueing theoretic modeling approach by running SPLASH-2 benchmarks on the SuperESCalar simulator (SESC). Results reveal that our queueing theoretic model qualitatively evaluates multi-core architectures accurately with an average difference of 5.6% as compared to the architectures’ evaluations from the SESC simulator. Our modeling approach can be used for performance per watt and performance per unit area characterizations of multi-core embedded architectures, with varying number of processor cores and cache configurations, to provide a comparative analysis.