Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus

The reliability of FPGA based hardware designs has become an important field of research particularly for space computing. Traditionally, redundancy is utilized in FPGA based designs to achieve reliable or error-tolerant computing. However, the redundant designs vary according to the granularity level and the voter placement algorithms used for the hardware design. The resulting circuit configurations vary in area, latency and power as well as in the achieved reliability. While the evaluation of area, latency and power is done by the FPGA design tools, quantitative data for reliability are usually not derived. Consequently, there is a need for an automated reliability evaluation tool especially considering the huge design space of redundant circuit structures. In this paper, we combine the Boolean difference error calculator (BDEC), a probabilistic reliability model for hardware designs, with a reliability model for fault-tolerant circuit structures. As a result, we are able to study the reliability of fault-tolerant circuit structures at the logic layer. We focus on fault-tolerant circuits to be implemented in FPGAs and show how to extend our combined model from combinational to sequential circuits. For an automated analysis, we develop a MATLAB-based tool utilizing our extended BDEC model. With this tool, we conduct a case study on dynamic reliability management and show how quantitative reliability data obtained from this tool improves the four-dimensional Pareto optimization for area, latency, power and reliability.     

High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs

Field-programmable gate arrays (FPGAs) have become an attractive option for accelerating scientific applications. Many scientific operations such as matrix-vector multiplication and dot product involve the reduction of a sequentially produced stream of values. Unfortunately, because of the pipelining in FPGA-based floating-point units, data hazards may occur during these sequential reduction operations. Improperly designed reduction circuits can adversely impact the performance, impose unrealistic buffer requirements, and consume a significant portion of the FPGA. In this paper, we identify two basic methods for designing serial reduction circuits: the tree-traversal method and the striding method. Using accumulation as an example, we analyze the design trade-offs among the number of adders, buffer size, and latency. We then propose high-performance and area-efficient designs using each method. The proposed designs reduce multiple sets of sequentially delivered floating-point values without stalling the pipeline or imposing unrealistic buffer requirements. Using a Xilinx Virtex-ll Pro FPGA as the target device, we implemented our designs and present performance and area results.     

FPGA realization of the LIRA neural classifier

Different types of neural networks can be used to classify images. We propose to apply LIRA (LImited Receptive Area) neural classifier to work with images. To accelerate the neural network functioning we propose a digital implementation of the LIRA neural classifier. We begin with a neuron design, and then continue with the neural network simulation. The advantage of neural network is its parallel structure and possibility of the training. FPGA (Field Programmable Gate Array) allows the implementation of these parallel algorithms in a single device. Speed of classification is one of the most important requirements in adaptive control systems based on computer vision. The contribution of this article is LIRA neural classifier implementation with FPGA for two classes to accelerate the training and recognition processes.     

基于FPGA的DDS虚拟AWG研制

Quartus环境以FPGA为数字电路和存储体载体,运用DDS技术虚拟实现任意信号产生,并在信号低频段仍能保持恒定很高的频率相对精度。本文重点介绍其系统设计原理、恒定精度分析、FPGA设计及实验结果。     

Design of a real time automatic speech recognition system using Modified One Against All SVM classifier

In this paper, Texas Instruments TMS320C6713 DSP based real-time speech recognition system using Modified One Against All Support Vector Machine (SVM) classifier is proposed. The major contributions of this paper are: the study and evaluation of the performance of the classifier using three feature extraction techniques and proposal for minimizing the computation time for the classifier. From this study, it is found that the recognition accuracies of 93.33%, 98.67% and 96.67% are achieved for the classifier using Mel Frequency Cepstral Coefficients (MFCC) features, zerocrossing (ZC) and zerocrossing with peak amplitude (ZCPA) features respectively. To reduce the computation time required for the systems, two techniques – one using optimum threshold technique for the SVM classifier and another using linear assembly are proposed. The ZC based system requires the least computation time and the above techniques reduce the execution time by a factor of 6.56 and 5.95 respectively. For the purpose of comparison, the speech recognition system is also implemented using Altera Cyclone II FPGA with Nios II soft processor and custom instructions. Of the two approaches, the DSP approach requires 87.40% less number of clock cycles. Custom design of the recognition system on the FPGA without using the soft-core processor would have resulted in less computational complexity. The proposed classifier is also found to reduce the number of support vectors by a factor of 1.12–3.73 when applied to speaker identification and isolated letter recognition problems. The techniques proposed here can be adapted for various other SVM based pattern recognition systems.     

基于Multisim 11.0的PLD图形化仿真设计与应用

简要介绍CPLD/FPGA(Complex programmable Logic Device/Field programmable Gates Array)器件的特点和应用范围,并以数字钟设计为例,介绍了在Multisim 11.0开发软件下,利用原理图的输入方式来设计数字逻辑电路的过程和方法,突出Multisim 11.0在教学中的重要作用,尤其是对于数字逻辑设计这门课程的学习。并且详细介绍了Multisim 11.0与Quartus II两个软件之间的互通,给出了一条PLD设计由:图形化模块搭建-Multisim系统化仿真-VHDL代码自动生成-Quartus II加载代码-Quartus II中的仿真-下载到硬件电路中-实际应用。整个一个完整的设计过程。     

支持隐私保护的k近邻分类器

k近邻（k-nearest neighbor,简称kNN）分类器在生物信息学、股票预测、网页分类以及鸢尾花分类预测等方面都有着广泛的应用.随着用户隐私保护意识的日益提高,kNN分类器也需要对密文数据提供分类支持,进而保证用户数据的隐私性,即设计一种支持隐私保护的k近邻分类器（privacy-preserving k-nearest neighbor classifier,简称PP-kNN）.首先,对kNN分类器的操作进行分析,从中提取出一些基本操作,包括加法、乘法、比较、内积等.然后,选择两种同态加密方案和一种全同态加密方案对数据进行加密.在此基础上设计了针对基本操作的安全协议,其输出结果与在明文数据上执行同一方法的输出结果一致,且证明该协议在半诚实模型下是安全的.最后,通过将基本操作的安全协议进行模块化顺序组合的方式实现kNN分类器对密文数据处理的支持.通过实验,对所设计的PP-kNN分类器进行测试.结果表明,该分类器能够以较高效率实现对密文数据的分类,同时为用户数据提供隐私性保护.     

高性能浮点除法和开方的设计与实现

在基于现场可编程门阵列（FPGA）的设计中,低延时、高吞吐量、小面积是3个主要考虑因素。针对以上因素,提出不同基数SRT浮点除法和开方算法,设计基于Virtex—IIproFPGA的可变位宽浮点除法和开方的3种实现方案,包括小面积的迭代实现、低延时的阵列实现和高吞吐量的流水实现。实验结果表明,对于浮点除法和开方算法的流水实现,在综合面积符合要求的基础上,实现频率最高分别可达到180MHz和200MHz以上,证明了该实现方案的有效I陛。     

A generalizable dynamic flow pairing method for traffic classification

The goal of network traffic classification is to identify the protocols or types of protocols in the network traffic. In particular, the identification of network traffic with high resource consumption, such as peer-to-peer (P2P) traffic, represents a great concern for Internet Service Providers (ISP) and network managers. Most current flow-based classification approaches report high accuracy without paying attention to the generalization ability of the classifier. However, without this ability, a classifier may not be suitable for on-line classification. In this paper, a number of experiments on real traffic help to elucidate the reason for this lack of generalization. It is also shown that one way to attain the generalization ability is by using dynamic classifiers. From these results, a dynamic classification approach based on the pairing of flows according to a similarity criterion is proposed. The pairing method is not a classifier by itself. Rather, its goal is to determine in a fast way that two given flows are similar enough to conclude they correspond to the same protocol. Combining this method with a classifier, most of the flows do not need to be explicitly evaluated by the later, so that the computational overhead is reduced without a significant reduction in accuracy. In this paper, as a case study, we explore complementing the pairing method with payload inspection. In the experiments performed, the pairing approach generalizes well to traffic obtained in different conditions and scenarios than that used for calibration. Moreover, a high portion of the traffic unclassified by payload inspection is categorized with the pairing method.     

Advancing synthesis of decision tree-based multiple classifier systems: an approximate computing case study

So far, multiple classifier systems have been increasingly designed to take advantage of hardware features, such as high parallelism and computational power. Indeed, compared to software implementations, hardware accelerators guarantee higher throughput and lower latency. Although the combination of multiple classifiers leads to high classification accuracy, the required area overhead makes the design of a hardware accelerator unfeasible, hindering the adoption of commercial configurable devices. For this reason, in this paper, we exploit approximate computing design paradigm to trade hardware area overhead off for classification accuracy. In particular, starting from trained DT models and employing precision-scaling technique, we explore approximate decision tree variants by means of multiple objective optimization problem, demonstrating a significant performance improvement targeting field-programmable gate array devices.

     

A Universal BIST Approach for Virtex-Ultrascale Architecture

Interconnected cells, Configurable Logic Blocks (CLBs), and input/output (I/O) pads are all present in every Field Programmable Gate Array (FPGA) structure. The interconnects are formed by the physical paths for connecting the blocks . The combinational and sequential circuits are used in the logic blocks to execute logical functions. The FPGA includes two different tests called interconnect testing and logical testing. Instead of using an additional circuitry, the Built-in-Self-Test (BIST) logic is coded into an FPGA, which is then reconfigured to perform its specific operation after the testing is completed. As a result, additional test circuits for the FPGA board are no longer required. The FPGA BIST has no area overhead or performance reduction issues like conventional BIST. A resource-efficient testing scheme is essential to assure the appropriate operation of FPGA look-up tables for effectively testing the functional operation. In this work, the Configurable Logic Blocks (CLBs) of virtex-ultrascale FPGAs are tested using a BIST with a simple architecture. To evaluate the CLBs’ capabilities including distributed modes of operation of Random Access Memory (RAM), several types of configurations are created. These setups have the ability to identify 100% stuck-at failures in every CLB. This method is suitable for all phases of FPGA testing and has no overhead or performance cost.     

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

This paper presents a resource-efficient time-division multiplexing network interface of a network-on-chip intended for use in a multicore platform for hard real-time systems. The network-on-chip provides virtual circuits to move data between core-local on-chip memories. In such a platform, a change of the application’s operating mode may require reconfiguration of virtual circuits that are setup by the network-on-chip. A unique feature of our network interface is the instantaneous reconfiguration between different time-division multiplexing schedules, containing sets of virtual circuits, without affecting virtual circuits that persist across the reconfiguration. The results show that the worst-case latency from triggering a reconfiguration until the new schedule is executing, is in the range of 300 clock cycles. Experiments show that new schedules can be transmitted from a single master to all slave nodes for a 16-core platform in between 500 and 3500 clock cycles. The results also show that the hardware cost for an FPGA implementation of our architecture is considerably smaller than other network-on-chips with similar reconfiguration functionalities, and that the worst-case time for a reconfiguration is smaller than that seen in functionally equivalent architectures.     

采用FPGA的高速CCD相机的时钟发生器

采用IL－E2 TDI CCD做为传感器，与计算机构成了成像系统，并在计算机CRT上显示出图像。主要介绍高速CCD相机的工作时钟产生电路的设计，采用大规模集成电路FPGA实现了该工作时钟驱动电路，采用AHDL语言对工作时钟驱动电路进行了硬件描述，并利用Max Plus2软件对所设计的工作时钟驱动电路进行了仿真，最后对FPGA器件进行了编程和硬件电路调试，进而实现了整个CCD相机的控制。     

A comparison of multiple classifier combinations using different voting-weights for remote sensing image classification

Remote sensing image classification is a common application of remote sensing images. In order to improve the performance of Remote sensing image classification, multiple classifier combinations are used to classify the Landsat-8 Operational Land Imager (Landsat-8 OLI) images. Some techniques and classifier combination algorithms are investigated. The classifier ensemble consisting of five member classifiers is constructed. The results of every member classifier are evaluated. The voting strategy is experimented to combine the classification results of the member classifier. The results show that all the classifiers have different performances and the multiple classifier combination provides better performance than a single classifier, and achieves higher overall accuracy of classification. The experiment shows that the multiple classifier combination using producer’s accuracy as voting-weight (MCC_mod2 and MCC_mod3) present higher classification accuracy than the algorithm using overall accuracy as voting-weight (MCC_mod1).And the multiple classifier combinations using different voting-weights affected the classification result in different land-cover types. The multiple classifier combination algorithm presented in this article using voting-weight based on the accuracy of multiple classifier may have stability problems, which need to be addressed in future studies.     

Discriminative training approaches to fabric defect classification based on wavelet transform

Wavelet transform is able to characterize the fabric texture at multiscale and multiorientation, which provides a promising way to the classification of fabric defects. For the objective of minimum error rate in the defect classification, this paper compares six wavelet transform-based classification methods, using different discriminative training approaches to the design of the feature extractor and classifier. These six classification methods are: methods of using an Euclidean distance classifier and a neural network classifier trained by maximum likelihood method and backpropagation algorithm, respectively; methods of using an Euclidean distance classifier and a neural network classifier trained by minimum classification error method, respectively; method of using a linear transformation matrix-based feature extractor and an Euclidean distance classifier, designed by discriminative feature extraction (DFE) method; method of using an adaptive wavelet-based feature extractor and an Euclidean distance classifier, designed by the DFE method. These six approaches have been evaluated on the classification of 466 defect samples containing eight classes of fabric defects, and 434 nondefect samples. The DFE training approach using adaptive wavelet has been shown to outperform the other approaches, where 95.8% classification accuracy was achieved.     

Artificial immune‐based supervised classifier for land‐cover classification

This paper explores the potential of an artificial immune‐based supervised classification algorithm for land‐cover classification. This classifier is inspired by the human immune system and possesses properties similar to nonlinear classification, self/non‐self identification, and negative selection. Landsat ETM+ data of an area lying in Eastern England near the town of Littleport are used to study the performance of the artificial immune‐based classifier. A univariate decision tree and maximum likelihood classifier were used to compare its performance in terms of classification accuracy and computational cost. Results suggest that the artificial immune‐based classifier works well in comparison with the maximum likelihood and the decision‐tree classifiers in terms of classification accuracy. The computational cost using artificial immune based classifier is more than the decision tree but less than the maximum likelihood classifier. Another data set from an area in Spain is also used to compare the performance of immune based supervised classifier with maximum likelihood and decision‐tree classification algorithms. Results suggest an improved performance with the immune‐based classifier in terms of classification accuracy with this data set, too. The design of an artificial immune‐based supervised classifier requires several user‐defined parameters to be set, so this work is extended to study the effect of varying the values of six parameters on classification accuracy. Finally, a comparison with a backpropagation neural network suggests that the neural network classifier provides higher classification accuracies with both data sets, but the results are not statistically significant.     

FPGA中的微程序设计

基于查表的商用ＦＰＧＡ是当前进行快速系统原型设计最流行的ＡＳＩＣ手段，文中根据ＸＩＬＩＮＸ的ＦＰＧＡ产品具有片上ＲＯＭ的特性，提出了在其内部实现微程序控制和管理复杂逻辑电路的新思想，并且在实际应用中取得满意的效果。文中还详细描述了在ＦＰＧＡ内部编写微程序的方法和编址技巧，给出了用ＦＰＧＡ实现一个典型的微程序控制器的电路模板，并总结了其应用特点和局限性。     

Physical synthesis of quantum circuits using templates

Similar to traditional CMOS circuits, quantum circuit design flow is divided into two main processes: logic synthesis and physical design. Addressing the limitations imposed on optimization of the quantum circuit metrics because of no information sharing between logic synthesis and physical design processes, the concept of “physical synthesis” was introduced for quantum circuit flow, and a few techniques were proposed for it. Following that concept, in this paper a new approach for physical synthesis inspired by template matching idea in quantum logic synthesis is proposed to improve the latency of quantum circuits. Experiments show that by using template matching as a physical synthesis approach, the latency of quantum circuits can be improved by more than 23.55 % on average.     

Classifier ensemble construction with rotation forest to improve medical diagnosis performance of machine learning algorithms

Improving accuracies of machine learning algorithms is vital in designing high performance computer-aided diagnosis (CADx) systems. Researches have shown that a base classifier performance might be enhanced by ensemble classification strategies. In this study, we construct rotation forest (RF) ensemble classifiers of 30 machine learning algorithms to evaluate their classification performances using Parkinson's, diabetes and heart diseases from literature.While making experiments, first the feature dimension of three datasets is reduced using correlation based feature selection (CFS) algorithm. Second, classification performances of 30 machine learning algorithms are calculated for three datasets. Third, 30 classifier ensembles are constructed based on RF algorithm to assess performances of respective classifiers with the same disease data. All the experiments are carried out with leave-one-out validation strategy and the performances of the 60 algorithms are evaluated using three metrics; classification accuracy (ACC), kappa error (KE) and area under the receiver operating characteristic (ROC) curve (AUC).Base classifiers succeeded 72.15%, 77.52% and 84.43% average accuracies for diabetes, heart and Parkinson's datasets, respectively. As for RF classifier ensembles, they produced average accuracies of 74.47%, 80.49% and 87.13% for respective diseases.RF, a newly proposed classifier ensemble algorithm, might be used to improve accuracy of miscellaneous machine learning algorithms to design advanced CADx systems.     

The route to a defect tolerant LUT through artificial evolution

Evolutionary techniques may be applied to search for specific structures or functions, as specified in the fitness function. This paper addresses the challenge of finding an appropriate fitness function when searching for generic rather than specific structures which, when combined wiacteristic of defect tolerance on the circuit. Production defects for integrated circuits are expected to increase considerably. To avoid a corresponding drop in yield, improved defect tolerance solutions are needed. In the case of Field Programmable Gate Arrays (FPGAs), the pre-designed gate array provides a bridge between production and the application designers. Thus, introduction of defect tolerant techniques to the FPGA itself could provide a defect free gate array to the application designer, despite production defects. The search for defect tolerance presented herein is directed at finding defect tolerant structures for an important building block of FPGAs: Look-Up Tables (LUTs). Two key approaches are presented: (1) applying evolved generic building blocks to a traditional LUT design and (2) evolving the LUT design directly. The results highlight the fact that evolved generic defect tolerant structures can contribute to highly reliable circuit designs at the expense of area usage. Further, they show that applying such a technique, rather than direct evolution, has benefits with respect to evolvability of larger circuits, again at the expense of area usage.