A -90-dB THD rail-to-rail input opamp using a new local charge pumpin CMOS

This paper describes the principle and design of a CMOS rail-to-rail input operational amplifier with THD performance of -90 dB which is suited for high-quality audio systems. A new output stage has been used featuring an output suing that extends to either supply rail and is capable of driving a low ohmic load (32 Ω). The opamp, which is realized in a 0.5-μm 3.3-V digital CMOS process, uses a standard two-stage Miller configuration. The rail-to-rail input functionality is achieved with a new area-efficient on-chip charge pump which provides the local supply voltage for the input differential pair. THD levels below -90 dB have not yet been shown with existing rail-to-rail techniques. This rail-to-rail input configuration also behaves independently of the common mode level with respect to transconductance and slewing characteristics     

一种恒跨导轨对轨CMOS运算放大器的设计

设计了一种新颖的恒跨导轨对轨CMOS运算放大器结构。输入级采用轨对轨的结构,在输入级采用4个虚拟差分对管来对输入差分对的电流进行限制,使运放的输入级跨导在工作范围内保持恒定。输出级采用前馈式AB类输出结构,以使输出达到全摆幅。仿真结果显示,在5 V电源电压和带有10 pF电容与10 kΩ电阻并联的负载下,该运放在共模输入范围内实现了恒跨导,在整个共模输入范围内跨导变化率仅为3%,输出摆幅也达到了轨对轨全摆幅,运放的开环增益为108.5 dB,增益带宽积为26.7 MHz,相位裕度为76.3°。     

A Low-Voltage Fully Differential Constant-Gm Rail-to-Rail CMOS Operational Amplifier

A low-voltage fully differential CMOS operational amplifier withconstant-g_mand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output stages have also afull voltage swing. A rail-to-rail input common mode feedback structureallows the output voltage control. Measurements in a 0.7 µ standardCMOS process with threshold voltages of about 0.7 V have been done. Theminimum experimental supply voltage is about 1.1 V. The circuit provides a60 dB low frequency voltage gain and about 1.5 MHz unity gain frequency fora total power consumption of about 0.72 mW at a 1.5 V supply voltage.     

负阻负载和复制运放增益增强技术相结合的低电压低功耗高增益端到端输出范围运算放大器

设计了一种低电压低功耗高增益端到端运算放大器.为了提高运放的直流增益,采用了复制运放增益增强技术,这种技术的特点是在提高增益的同时不影响输出摆幅,非常适合低电压场合.该运放采用0.18μm标准CMOS工艺,工作电压为1V.仿真结果表明,在5pF负载电容下所获得运放的直流增益达到65.9dB,增益带宽积为70.28MHz,相位裕度为50°,静态功耗为156.7μW.     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

A high-speed low-power rail-to-rail column driver for AMLCD application

A high-speed rail-to-rail low-power column driver for active matrix liquid crystal display application is proposed. An inversion controller is attached to a typical column driver for rail-to-rail operation. Two high-speed complementary differential buffer amplifiers are proposed to drive a pair of column lines and to realize a rail-to-rail and high-speed drive. The output buffer amplifier achieves a large driving capability by employing a simple comparator to sense the transients of the input to turn on an auxiliary driving transistor, which is statically off in the stable state. This increases the speed without increasing static power consumption. The experimental prototype 6-bit column driver implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the driver exhibits the maximum settling times of 1.2 /spl mu/s and 1.4 /spl mu/s for rising and falling edges with a dot inversion under a 680-pF capacitance load. The static current consumptions are 4.7 and 4.2 /spl mu/A for pMOS input buffers and nMOS input buffers, respectively. The values of the differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 1/2 LSB.     

基于最小电流选择的运算放大器设计

设计了一种工作电压为3V恒跨导满幅CMOS运算放大器,针对轨对轨输入级中存在的跨导不恒定和简单AB类输出级性能偏差这2个问题,提出了利用最小电流选择电路来稳定输入级的总跨导;浮动电流源控制的无截止前馈AB类输出级实现了运放的满幅输出,同时减小了交越失真。该电路通过HSpice进行仿真验证,在0～3V输入共模范围内,输入级跨导的变化小于3.3%,开环增益为93dB,单位增益带宽为8MHz,相位裕量为66°。     

一种宽带恒定跨导轨对轨运算放大器的设计

介绍了一种具有轨对轨输入功能的CMOS输入级电路。该电路克服了一般运算放大器只能工作在一定共模输入范围的输入级的缺陷，在各种共模输入电平下有着几乎恒定的跨导，使频率补偿更容易实现，且由于其工作原理与MOS晶体管的C—V解析关系无关，对制造工艺依赖性小，适用于深亚微米工艺。在此基础上，设计出了一种宽带的运算放大器，该运算放大器具有轨对轨输入、输出能力，可以作为常用模拟电路的基本单元模块。它没有严格的共模输入限制，跨导和整体性能稳定，适于为更大规模的数字／模拟混合信号系统提供行为级模型。     

一种输入输出轨到轨CMOS运算放大器的设计

随着电源电压的日益降低,信号幅度不断减小,在噪声保持不变的情况下,信噪比也会相应地减小。为了在低电源电压下获得高的信噪比,需提高信号幅度,而输入输出轨到轨运算放大器可获得与电源电压轨相当的信号幅度。中文在理论分析了输入输出轨到轨CMOS运算放大器主要架构优缺点后,给出了一种新的输入输出轨到轨CMOS运算放大器的设计,该电路在华润上华0.18 μm工艺平台上流片验证。测试结果表明,输入范围从0到电源电压,输出范围从50 mV到电源电压减去50 mV,实现了输入输出轨到轨的目标。     

A rail-to-rail CMOS op amp

A CMOS op amp (operational amplifier) is reported which has a rail-to-rail voltage range at its input as well as its output. An area-efficient output stage has been used. While the entire op amp occupies only 600 mil², when used as a unity-gain buffer and with ±5-V supplies, the op amp can drive a 9-V_pp/1-kHz sine wave across a 300-Ω load with -64 dB of harmonic distortion     

一种基于准浮栅技术的折叠差分结构及其应用

提出了一种基于准浮栅技术的新型折叠差分结构,其偏置电流源的电压降被折叠到输出电压摆幅中,且不受共模输入电压限制而达到较大范围,非常适于低压应用。基于此结构,实现了一种超低压运算放大器。仿真分析表明,该运算放大器能够实现轨到轨(rail-to-rail)的共模输入电压范围和输出电压摆幅,以及较高的共模抑制比。     

Class AB CMOS amplifiers with high efficiency

A new class AB CMOS operational-amplifier principle is presented. A transconductance amplifier based on this principle exhibits small-signal characteristics comparable to those of a conventional OTA. It has, however, a superior current efficiency and its settling time is not slew-rate limited. The new class AB principle can also be used in an output stage with a well-defined quiescent current, a rail-to-rail output swing, and a good driving capability. A two-stage amplifier with both the input and output stages based on the new principle has been realized. It features a rail-to-rail input and output common-mode range, a gain-bandwidth of 370-kHz, a settling time of less than 5 μs independent of the applied step, and a power consumption of 247 μW. It drives a resistive load of 3 kΩ in parallel with a capacitive load of 400 pF when operated on a 2.5-V/-2.5-V power supply     

Rail-to-rail low-power high-slew-rate CMOS analogue buffer

A low-power rail-to-rail CMOS analogue buffer is presented. The circuit is based on an input stage made up of two complementary class AB differential pairs, while a simple additional circuit allows rail-to-rail operation at the output terminal. The proposed circuit combines low static power consumption and high drive capability, resulting in suitability for applications with large capacitive loads. Simulated results are provided.     

A highly linear CMOS buffer amplifier

A CMOS buffer amplifier which achieves significant improvements in linearity and drive capability over previously reported high-swing amplifiers is described. The buffer operates from a 5-V supply, is capable of rail-to-rail operation at both the input and output, an exhibits a remarkably high linearity of 0.05% THD while driving 3 V/SUB p-p/ into 100 /spl Omega/ at 20 kHz.     

一种恒跨导CMOS运算放大器的设计

设计了一种宽带轨对轨运算放大器,此运算放大器在3.3 V单电源下供电,采用电流镜和尾电流开关控制来实现输入级总跨导的恒定。为了能够处理宽的电平范围和得到足够的放大倍数,采用用折叠式共源共栅结构作为前级放大。输出级采用AB类控制的轨对轨输出。频率补偿采用了级联密勒补偿的方法。基于TSMC 2.5μm CMOS工艺,电路采用HSpice仿真,该运放可达到轨对轨的输入/输出电压范围。     

A high-efficiency 4×20 W monolithic audio amplifier forautomobile radios using a complementary D-MOS BCD technology

A monolithic quad audio power amplifier which reduces power dissipation by 45% with a music signal compared to a standard class-AB amplifier is described. A new two-stage operational amplifier, capable of providing high output current, is used for each one of eight power amplifiers. In a bridge configuration, a common-loop mode control is performed exploiting a sample-and-hold circuit. A multipower bipolar-CMOS-DMOS (BCD) technology is employed with a push-pull rail-to-rail output stage and a low-loss power switch. Experimental results are presented     

一种0.8V衬底驱动轨对轨运算放大器设计

采用衬底驱动技术设计低压低功耗轨对轨运算放大器。输入级采用衬底驱动MOSFET,有效避开阈值电压限制,将电源电压降至0.8V,实现低压下轨对轨共模输入范围。增加衬底驱动冗余差分对及反折式共源共栅求和电路实现恒定跨导控制,消除共模电压对输入级跨导的影响,输出采用前馈式AB类输出级,以提高动态输出电压范围。基于标准0.18μmCMOS工艺仿真运放,测得输出范围0.4～782.5mV,功耗48.8μW,电源抑制比58dB,CMRR65dB,直流开环增益63.8dB,单位增益带宽2.4MHz,相位裕度68°。版图设计采用双阱交叉空铅技术,面积为97.8μm×127.6μm。     

New low-voltage class AB/AB CMOS op amp with rail-to-rail input/output swing

A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two V/sub GS/ drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-/spl mu/m CMOS technology verify the scheme operating with /spl plusmn/0.9-V supplies and close to rail-to-rail input and output swing.     

Rail-to-rail BiCMOS operational amplifier using input signal adapters with floating outputs

An operational amplifier with rail-to-rail input and output voltage range in 0.6 μm BiCMOS technology is presented. Two simple input signal adapters with floating outputs serving as pre-stages are introduced. They are followed by a differential amplifier. The adapters translate the input signals into a floating level within the operating region of the differential amplifier, enabling rail-to-rail operation. An inverter-based simple rail-to-rail class AB output stage has been used. With a single supply of 1.5 V, the proposed rail-to-rail operational amplifier achieves 72 dB DC open-loop gain, 2.54 MHz unity-gain frequency, 62° phase margin, 2.5 V/μs slew rate, and 147 μW power consumption.     

一种电流跟踪补偿的输入输出全摆幅运算放大器

介绍了一种工作在2.5V电压下、具有全摆幅输入与输出功能的两级CMOS运算放大器。通过一种简单有效的电流跟踪电路实现了输入跨导恒定的要求，这样使得频率补偿变得容易实现；为了降低功耗，输入级工作在弱反型区：输出级采用带有前馈控制电路的AB类输出电路，实现了输出信号的轨至轨。电路具有结构简单、功耗低、面积小、性能高等优点。