浅析贴片设备

由于表面组装技术不断地朝着小型化的方向发展，特别是在细间距、小直径的凸点和使用的焊剂的诸多因素的推动下，促使设备供应商根据倒装芯片技术的需求而研制新一代的贴装机。本主要介绍了设备的制造厂家根据倒装芯片 的特点，采用柔性（软件）方法和视觉系统等方案对现有的设备进行改型，从而实现了贴装设备的自动化。实践证明研制开发倒装芯片技术的自动组装技术可使生产率、材料和工艺设备取得了明显的进步。     

环球仪器将在上海举办研讨会

环球仪器将于8月10日（周五）在上海先进工艺实验室，举办“倒装芯片工艺”研讨会，邀请相关客户及有兴趣人士参加，共同探讨表面贴装行业最新的工艺，进一步提高业界水平。目的是让参加者认识整个倒装芯片过程，每一个工作流程的要点，以及倒装芯片工艺的设备要求。研讨会除介绍倒装芯片工艺及其实施外，也将示范整个倒装芯片的过程，从机器的设置、材料的准备以及实际的拾取、贴装过程。     

倒装芯片在基板上的装配工艺

倒装芯片装配是能否实现产品微型化能力的关键。我们以前己经针对一些倒装芯片的互连形式开展了研究工作，包括：各向异性的导电簿膜或者焊膏，以及金-金热声波键合。目的主要是瞄准间距为0．200和0．250mm的倒装芯片的焊接装配工作。对于倒装芯片来说有二种施加焊剂的方法：焊剂沉浸方式和对基板进行焊剂喷射的方式。我们对传统的SMT贴装设备（可以满足倒装芯片装配的价格提升的高档货）所具有的贴装准确性展开了研究，并且对所获得的结果进行讨论。     

表面组装技术的发展趋势

分析了表面组装工艺和表面组装设备的发展趋势,指出了表面组装工艺的芯片级组装技术、多芯片模块技术和三维立体组装技术等三大发展趋势.同时给出了贴装机、印刷机、回流焊机、波峰焊机、清洗设备和检测设备的发展趋势.     

SMT贴片设备的结构和技术参数探讨

表面贴装技术（SurfaceMountTechnology简称SMT）是电子产品板级组装的主要工艺流程，因此SMT贴片设备引起广泛的关注，并且在现实生活中SMT组装技术给企业带来了高效率低成本的收益，因此逐渐发展壮大。随着电子元件封装体积口形状等特征的改变和对贴装速度的不断追求，SMT贴装设备为了满足贴装需求和效率的提升也随之逐渐完善。与此同时，SMT贴装设备的结构和技术参数也越来越受关注。本文主要介绍现今几款主流SMT贴片设备的结构和使,qEJm常用的技术参数，以及不同结构设备之间存在的联系和优越性，以供相关业界人士参考。     

引入模块化概念的贴装设备

向模块化组装生产线方向发展正获得愈来愈多人们的关注。一条由多种“高速模块”所组成的生产线具有许多优点,将对现有的装配厂商具有很大的诱惑力。由高速柔性化贴装设备所组成的组装生产线可以超越传统的芯片射手和微细间距贴装设备。     

倒装芯片结构中不流动底部填充工艺参数

介绍了倒装芯片贴装工艺中焊剂涂布技术的工艺控制、芯片贴装及回流过程的条件控制。讨论了贴装工艺中焊剂材料的热远配参数和改进型填补材料取代传统填补剂的可行性。     

微电子封装中芯片焊接技术及其设备的发展

概述了微电子封装中引线键合、载带自动键合、倒装芯片焊料焊凸键合、倒装芯片微型焊凸键合等芯片焊接技术及其设备的发展 ,同时报告了世界著名封装设备制造公司芯片焊接设备的现状及发展趋势。     

书讯

低成本倒装芯片技术——DCA、WLCSP和PBGA芯片的贴装技术;DSP处理器和微控制器硬件电路。     

ASE和IBM二公司在倒装芯片组装中进行合作

据可靠消息,台湾ASE(日月光半导体制造公司)和美国IBM公司在倒装芯片组装技术方面相互合作,采用IBM公司开发的SLC(Surface Laminar Circuit)基板,共同开发第二代的倒装芯片组装技术。ASE公司采用该基板进行倒装芯片组件的设计、制造、安装等。另外,二公司计划共同提供基板组装的设计服务等。     

对表面贴装设备带来影响的BGA器件

BGA技术的出现给制造业带来了压力,迫使人们要用一种新的眼光来寻找装配工艺方法。为了能够满足产品小型化的要求,能够降低引脚针间距的芯片规模封装和倒装芯片技术,将永无止境地向前发展,精确贴装的能力将继续是一个非常重要的因素。     

基于Linux的半导体生产设备通用平台的实现

上芯机、贴片机等是半导体制造行业中非常重要的生产设备,分析了上芯机、贴片机等半导体生产设备的系统控制平台,并且对各个系统的结构进行了比较,在抽取出它们的共同特征的基础上,提出了基于Linux操作系统的实时多任务系统通用平台的构建及其实现方法.     

Using GA-SVM for defect inspection of flip chips based on vibration signals

Flip chip technology has been widely used in IC packaging, and the combination of flip chip technology and solder joint interconnection technology has been utilized in the manufacturing of electronic devices universally. As the development of flip chip towards high density and ultra-fine pitch, the inspection of flip chips is confronted with great challenges. In this paper, we developed an intelligent system used for the detection of flip chips based on vibration. Thirty-four features including 18 time domain features and 16 frequency domain features were extracted from the raw vibration data. The support vector machine was employed to implement the recognition and classification of flip chips. In order to improve the classification accuracy of SVM, cross validation (CV) and genetic algorithm (GA) were utilized to optimize the parameters of SVM respectively. SVM, CV-SVM and GA-SVM were applied to classification separately and the results were obtained. By comparison, GA-SVM can recognize and classify the flip chips rapidly with high accuracy. Thus, GA-SVM is effective for the defect inspection of flip chips.     

Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies

Gold to gold interconnection (GGI) flip chip bonding technology has been developed to bond the drive IC chip on the integrated circuit suspension used in hard disk drives. GGI is a lead free process where the Au bumps and Au bond pads are joined together by heat and ultrasonic power under a pressure head. The use of GGI flip chip assembly process will help to eliminate equipment parts and processing steps of the traditional flip chip C4 process and hence shortens the overall cycle time. With the integrated circuit suspension design, it becomes possible to assemble the drive IC chip close next to the magneto-resistive head slider on the suspension.This paper describes a flip chip bonding method joining the drive IC chip on integrated circuit suspension with GGI bonding. The reliability evaluations are concentrated on thermo-mechanical analysis, robustness and functional performance of the final assembly. GGI bonding for chip on suspension application is still relatively new and has not been achieved for volume use. Work is still being done to establish and extend the limits of the technology with regard to long term reliability.     

提高倒装芯片组装速度的在线测试

倒装芯片是一种性能价格比良好的互连技术 ,要求采用富有创新的操作 ,以满足KGD的测试方法和操作工艺的需要。在基片上贴装好以前应立刻进行测试以确保能够起作用的管芯才能被装配入到倒装芯片或者说印刷电路板上面。在线测试设备是一种能够满足这些性能要求和价格要求的设备     

实施倒装芯片的组装

成功的倒装芯片组装要求在焊剂应用、贴装设备、再流焊接、底部填充、密封剂密封和固化等方面予以特别的考虑.     

Flip chip interconnect systems using copper wire stud bump and leadfree solder

This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy interconnects. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire stud bumping. Cu wire studs were bumped by controlling the ramp rate of ultrasonic power to eliminate the occurrence of under-pad chip cracks that tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu (SnAgCu) alloy was used to interconnect the wire studs and printed circuit board. A comparison was made with conventional eutectic 63Sn37Pb (SnPb) alloy and 60In40Pb (InPb) alloy. Test vehicles were assembled with two different direct chip attachment (DCA) processes. When the basic reflow assembly using a conventional pick and place machine and convection reflow was used, 30% of the lead free test vehicles exhibited process defects. Other lead free test vehicles failed quickly in thermal shock testing. Applying the basic reflow assembly process is detrimental for the SnAgCu test vehicles. On the other hand, when compression bonding assembly was performed using a high accuracy flip chip bonder, the lead free test vehicles exhibited no process defects and the thermal shock reliability improved. Cu stud-SnAgCu test vehicles (Cu-SnAgCu) in particular showed longer mean time to failure, 2269 cycles for the B stage process and 3237 cycles for high temperature bonding. The C-SAM and cross section analysis of the Cu stud bump assemblies indicated less delamination in thermal shock testing and significantly less Cu diffusion into the solder compared to Au stud bumped test vehicles. The Cu stud-SnAgCu systems form stable interconnects when assembled using a compression bonding process. Moreover, Cu wire stud bumping offers an acceptable solution for lead free assembly     

控制贴片质量关键因素的研究

贴片质量的优劣一直困扰着贴片机的使用者,影响贴片质量的因素有很多,诸如贴片机自身硬件软件条件、贴片对象的质量、贴片环境的合适程度、贴片技术的娴熟程度、贴片机操作人的人为因素等等。本文从元器件选择、贴片机结构与性能两个角度阐述了其如何影响贴片质量。以元器件尺寸、端头电极与引线电极、平整度、料带等方面细述如何选择最合适的元器件以提高贴片质量,并以吸嘴为例细述了如何选择与设置贴片机吸嘴和贴片压力来提高贴片质量。对影响贴片质量的贴片位置控制也作了一定的论述。     

Flip Chip Bonding of 68 $times$ 68 MWIR LED Arrays

The flip chip bonding process is optimized by varying the bonding pressure, temperature, and time. The 68times68 mid wave infrared (MWIR) LED array was hybridized onto Si-CMOS driver array with same number of pixels. Each pixel has two indium bumps, one for cathode and another for anode. Both LED array and CMOS drivers have 15-mum-square Indium bump contact pads. We used Karl Suss FC150 flip chip machine for bonding of CMOS driver array onto LED array. From the LED current-voltage characteristics, it is concluded that the optimized flip chip bonding process results in uniform contact and very low contact resistance. Both electrical and optical characteristics of LED array after flip chip bonding are presented.