Parallel High Throughput Soft-Output Sphere Decoding Algorithm

Multiple-Input-Multiple-Output communication systems demand fast sphere decoding with high performance. To speed up the computation, we propose a scheme with multiple fixed complexity sphere decoders to construct a parallel soft-output fixed complexity sphere decoder (PFSD). The proposed decoder is highly parallel and has performance comparable to soft-output list fixed complexity sphere decoder (LFSD) and K-best sphere decoder. In addition, we propose a parallel QR decomposition algorithm to lower the preprocessing overhead, and a low complexity LLR algorithm to allow parallel update of LLR values. We demonstrate that the PFSD algorithm can increase the throughput and reduce bit error rate of a soft-output solution in a 4 × 4 16-QAM system, and has superior performance compared to other soft decoders with comparable throughput and computation complexity. The PFSD algorithm has been mapped onto Xilinx XC4VLX160 FPGA. The resulting PFSD decoder can achieve up to 75 Mbps throughput for 4 × 4 64-QAM configuration at 100MHz with low control overhead.     

Near-optimum decoding of product codes: block turbo codes

This paper describes an iterative decoding algorithm for any product code built using linear block codes. It is based on soft-input/soft-output decoders for decoding the component codes so that near-optimum performance is obtained at each iteration. This soft-input/soft-output decoder is a Chase decoder which delivers soft outputs instead of binary decisions. The soft output of the decoder is an estimation of the log-likelihood ratio (LLR) of the binary decisions given by the Chase decoder. The theoretical justifications of this algorithm are developed and the method used for computing the soft output is fully described. The iterative decoding of product codes is also known as the block turbo code (BTC) because the concept is quite similar to turbo codes based on iterative decoding of concatenated recursive convolutional codes. The performance of different Bose-Chaudhuri-Hocquenghem (BCH)-BTCs are given for the Gaussian and the Rayleigh channel. Performance on the Gaussian channel indicates that data transmission at 0.8 dB of Shannon's limit or more than 98% (R/C>0.98) of channel capacity can be achieved with high-code-rate BTC using only four iterations. For the Rayleigh channel, the slope of the bit-error rate (BER) curve is as steep as for the Gaussian channel without using channel state information     

Low-complexity maximum-likelihood detection of coded signals sentover finite-state Markov channels

We propose a decision-feedback decoder for coded signals transmitted over finite-state Markov channels. The decoder achieves maximum-likelihood sequence detection (in the absence of feedback errors) with very low complexity by exploiting previous bit decisions and the Markov structure of the channel. We also propose a similar decoder, the output-feedback decoder, that does not use previous bit decisions and therefore does not suffer from error propagation. The decoder performance is determined using a new sliding window analysis technique as well as by simulation. Both decoders exhibit excellent bit error rate performance with a relatively low complexity that is independent of the channel decorrelation time     

Group-metric multiuser decoding

We propose the new group metric (GM) soft-decision decoder for convolutionally coded synchronous multiple-access channels. The GM decoder exploits the independently operating encoders of the multiuser channel by making decoding decisions for a subset of the users, but incorporating all the multiuser information in its metrics. For a single user, this decoder will have a reduced complexity that is exponential in the sum of encoder memory and the number of users. The soft-decision maximum-likelihood (ML) joint decoder is well known. This optimal decoder suffers from a high complexity requirement that is exponential in the product of encoder memory and the number of users. The size of the decoded subset is a design parameter which allows a tradeoff between complexity and performance. The performance of the GM decoder, once properly characterized, can be analyzed using standard techniques. In addition, a new analysis technique is presented which considers decomposable sequences for the fading channel. With this analysis, we have a new tool for bounding error probabilities for multiuser decoders. Applying this technique to the GM decoder, we can directly identify sequences that are decomposable some fraction of the time, and obtain a new upper bound. Further, this improved bound can be expressed in closed form. Numerical results show that the actual performance gap between the GM and ML decoders can be quite small     

Nonlinear Programming Approaches to Decoding Low-Density Parity-Check Codes

We consider the decoding problem for low-density parity-check codes, and apply nonlinear programming methods. This extends previous work using linear programming (LP) to decode linear block codes. First, a multistage LP decoder based on the branch-and-bound method is proposed. This decoder makes use of the maximum-likelihood-certificate property of the LP decoder to refine the results when an error is reported. Second, we transform the original LP decoding formulation into a box-constrained quadratic programming form. Efficient linear-time parallel and serial decoding algorithms are proposed and their convergence properties are investigated. Extensive simulation studies are performed to assess the performance of the proposed decoders. It is seen that the proposed multistage LP decoder outperforms the conventional sum-product (SP) decoder considerably for low-density parity-check (LDPC) codes with short to medium block length. The proposed box-constrained quadratic programming decoder has less complexity than the SP decoder and yields much better performance for LDPC codes with regular structure.     

Efficient source decoding over memoryless noisy channels using higher order Markov models

Exploiting the residual redundancy in a source coder output stream during the decoding process has been proven to be a bandwidth-efficient way to combat noisy channel degradations. This redundancy can be employed to either assist the channel decoder for improved performance or design better source decoders. In this work, a family of solutions for the asymptotically optimum minimum mean-squared error (MMSE) reconstruction of a source over memoryless noisy channels is presented when the redundancy in the source encoder output stream is exploited in the form of a /spl gamma/-order Markov model (/spl gamma//spl ges/1) and a delay of /spl delta/,/spl delta/>0, is allowed in the decoding process. It is demonstrated that the proposed solutions provide a wealth of tradeoffs between computational complexity and the memory requirements. A simplified MMSE decoder which is optimized to minimize the computational complexity is also presented. Considering the same problem setup, several other maximum a posteriori probability (MAP) symbol and sequence decoders are presented as well. Numerical results are presented which demonstrate the efficiency of the proposed algorithms.     

Design of Spherical Lattice Space–Time Codes

In this paper, we propose a systematic procedure for designing spherical lattice (space–time) codes. By employing stochastic optimization techniques we design lattice codes which are well matched to the fading statistics as well as to the decoder used at the receiver. The decoders we consider here include the optimal albeit of highest decoding complexity maximum-likelihood (ML) decoder, the suboptimal lattice decoders, as well as the suboptimal lattice-reduction-aided (LRA) decoders having the lowest decoding complexity. For each decoder, our design methodology can be tailored to obtain low error-rate lattice codes for arbitrary fading statistics and signal-to-noise ratios (SNRs) of interest. Further, we obtain fundamental lower bounds on the error probabilities yielded by lattice and LRA decoders and characterize their asymptotic behavior.      

Low Complexity Soft Decoder for Nordstrom-Robinson Code With Application to the Chinese DTTB Standard

Nordstrom-Robinson (NR) code followed by 4 quadrature-amplitude modulation (4QAM) mapping is one of the working modes in the Chinese digital television terrestrial broadcasting (DTTB) standard, where the outer code is a low-density parity-check (LDPC) code. Since LDPC decoders usually accept soft rather than hard inputs for better error performance, soft NR decoders are highly recommended. In this paper, several novel low-complexity soft NR decoders are proposed with excellent error performance. Simulation results show that the proposed algorithm based on the maximum, second and third maximum (MST) cross correlation values achieves very low complexity at the cost of performance loss only about 0.1 dB at bit error rate (BER) of $10^{-6}$ , under both additive white Gaussian noise (AWGN) and independent Rayleigh fading channels, compared to the ideal maximum a posteriori (MAP) decoder.      

Noncoherent demodulation techniques for trellis coded M-DPSKsignals

Considers noncoherent decoding of trellis coded M-DPSK transmission, and attempts to unify and contrast the approaches to this problem which have been previously reported. In the second part of the paper, the maximum likelihood block decoders for the AWGN channel are outlined, first assuming that the decoder has no knowledge of the state of the encoder at the beginning of the block, and then assuming that it knows the state. Because these exhaustive decoders suffer from an exponential growth in complexity with block length, two simplified decoders are proposed that approach the performance of the exhaustive decoders with a much more manageable complexity. Through a union bound analysis and computer simulations, it is shown that it is possible to achieve large gains over uncoded systems with a very reasonable decoder complexity     

Area-efficient high-throughput MAP decoder architectures

Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is recursive and complex, which makes high-speed implementations extremely difficult to realize. In this paper, we present block-interleaved pipelining (BIP) as a new high-throughput technique for MAP decoders. An area-efficient symbol-based BIP MAP decoder architecture is proposed by combining BIP with the well-known look-ahead computation. These architectures are compared with conventional parallel architectures in terms of speed-up, memory and logic complexity, and area. Compared to the parallel architecture, the BIP architecture provides the same speed-up with a reduction in logic complexity by a factor of M, where M is the level of parallelism. The symbol-based architecture provides a speed-up in the range from 1 to 2 with a logic complexity that grows exponentially with M and a state metric storage requirement that is reduced by a factor of M as compared to a parallel architecture. The symbol-based BIP architecture provides speed-up in the range M to 2M with an exponentially higher logic complexity and a reduced memory complexity compared to a parallel architecture. These high-throughput architectures are synthesized in a 2.5-V 0.25-/spl mu/m CMOS standard cell library and post-layout simulations are conducted. For turbo decoder applications, we find that the BIP architecture provides a throughput gain of 1.96 at the cost of 63% area overhead. For turbo equalizer applications, the symbol-based BIP architecture enables us to achieve a throughput gain of 1.79 with an area savings of 25%.     

Art of constructing low-complexity encoders/decoders forconstrained block codes

A rate p : q block encoder is a dataword-to-codeword assignment from 2^p p-bit datawords to 2^p q-bit codewords, and the corresponding block decoder is the inverse of the encoder. When designing block encoders/decoders for constrained systems, often, more than 2^p codewords are available. In this paper, as our main contribution, we propose efficient heuristic computer algorithms to eliminate the excess codewords and to construct low hardware complexity block encoders/decoders. For (0,4/4) and (0,3/6) PRML constraints, block encoders/decoders generated using the proposed algorithms are comparable in complexity to human-generated encoders/decoders, but are significantly simpler than lexicographical encoders/decoders     

Design of Encoder and Decoder for LDPC Codes Using Hybrid H‐Matrix

Low‐density parity‐check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H‐matrices are constructed so that both the semi‐random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog‐HDL and are synthesized using a 0.35 µm CMOS standard cell library.     

Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding

K-best sphere decoding is one of the most popular MIMO (Multi-Input Multi-Output) detection algorithms because of its low complexity and close to Maximum Likelihood (ML) Bit Error Rate (BER) performance. Unfortunately, conventional multi-stage sphere decoders suffer from the inability to adapt to varying antenna configurations, requiring implementation redesign for each specific array structure. In this paper, we propose a reconfigurable in-place architecture that is scalable to an arbitrary number of antennas at run-time, while reducing area significantly compared with other sphere decoders. To improve the throughput of the in-place architecture without any degradation in BER performance, we propose partial-sort-bypass and symbol interleaving techniques, and also exploit multi-core design. Implementation results for a 16-QAM MIMO decoder in a 130 nm CMOS technology show a 41% reduction in area compared to the smallest sphere decoder while maintaining antenna reconfigurability, and better throughput. When implemented for the 802.11n standard, our architecture results in 42% reduction in area compared to the multi-stage architecture.     

同步部分并行结构的准循环LDPC码译码器

该文根据准循环LDPC码的结构特点,提出了一种同步部分并行结构的译码器。在译码器中,校验节点处理单元和变量节点处理单元同时并行工作,使得迭代过程中新产生的软信息能够被提前使用,加快迭代的收敛速度。同时,采用差分演化的方法对各节点处理单元的起始位置进行优化,进一步提高了译码器的性能。仿真结果表明,该方案在译码性能和复杂度上都要优于现有其他方案,适合高速译码器的实现。     

VLSI architectural design tradeoffs for sliding-window log-MAP decoders

Turbo codes have received tremendous attention and have commenced their practical applications due to their excellent error-correcting capability. Investigation of efficient iterative decoder realizations is of particular interest because the underlying soft-input soft-output decoding algorithms usually lead to highly complicated implementation. This paper describes the architectural design and analysis of sliding-window (SW) Log-MAP decoders in terms of a set of predetermined parameters. The derived mathematical representations can be applied to construct a variety of VLSI architectures for different applications. Based on our development, a SW-Log-MAP decoder complying with the specification of third-generation mobile radio systems is realized to demonstrate the performance tradeoffs among latency, average decoding rate, area/computation complexity, and memory power consumption. This paper thus provides useful and general information on practical implementation of SW-Log-MAP decoders.     

Implementation of APP decoders on dual code trellis

For high rate k/n convolutional codes (k/n > 0.5), a trellis based implementation of a posteriori probability (APP) decoders is less complex on the dual code trellis owing to its branch complexity (2^n-k ) being lower than the code trellis (2^k). The log scheme used for APP decoders is not attractive for practical implementation owing to heavy quantisation requirements. As an alternative, presented is an arc hyperbolic tangent (AHT) scheme for implementing the dual- APP decoder. The trellis based implementation of this AHT dual APP decoder is discussed and some fundamental differences between primal APP and dual APP decoders that have an effect on a quantised implementation are reported.     

Convolutional coding for finite-state channels

We propose new decoders for decoding convolutional codes over finite-state channels. These decoders are sequential and utilize the information about the channel state sequence contained in the channel output sequence. The performance of these decoders is evaluated by simulation and compared to the performance of memoryless decoders with and without interleaving. Our results show that the performance of these decoders is good whenever the channel statistics are such that the joint estimate of the channel state sequence and the channel input sequence is good, as, for example, when the channel is bursty. In these cases using even a partial search decoder such as the Fano decoder over the appropriate trellis is nearly optimal. However, when the information between the output sequence and the sequence of channel slates and inputs diminishes, the memoryless decoder with interleaving outperforms even the optimal decoder which knows the channel state     

High-performance VLSI architectures for turbo decoders with QPP interleaver

This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW – SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of ‘mod’ operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.     

Novel Encoder/Decoder Using Subsampled Bragg Grating for a WDM-Compatible OCDMA System

Optical code-division multiple-access (OCDMA) technology is attractive for optical broadband access network. It is very interesting to use the super-structure fiber-Bragg-grating-based en/decoders to construct a wavelength-division-multiplexing (WDM)-compatible OCDMA system. Based on the equivalent phase-shift technique, we have proposed a subsampled-Bragg-grating (S-SBG)-based en/decoder. Based on the proposed method, only a single uniform phase mask can be used to accommodate different WDM channels with relevant central wavelengths and spectrum width. Using the S-SBG-based en/decoder, we can make different WDM channels have similar as well as better encoding efficiency and correlation performance. S-SBG-based en/decoders with 127 chips for two different wavelength channels are fabricated and measured. The experiments indicate the advantages revealed by the theoretical simulation.     

完美空时分组码及其高性能解码算法

根据完美空时分组码（STBC）的结构特点提出了等效的垂直-贝尔实验室空时（V-BLAST）模型，在对该模型进行最小均方误差-判决反馈均衡（MMS-DFE）预处理之后，提出一种有边界约束的Fano解码器。该解码器可达到几乎最大似然（ML）性能，在很大的信噪比区域范围内其复杂度比目前典型的解码器低，而且该解码器可用于发射天线数大于接收天线数的系统。直接在复数域计算和处理，该解码器适用于任何星座形式。该解码器可用于任何能等效成V-BLAST模型的空时系统。仿真结果表明了该解码器的有效性。