AC floating body effects and the resultant analog circuit issues insubmicron floating body and body-grounded SOI MOSFET's

We report the extensive study on ac floating body effects of different SOI MOSFET technologies. Besides the severe kink and resultant noise overshoot and degraded-distortion in partially depleted (PD) floating body SOI MOSFET's, we have investigated the residue ac floating body effects in fully depleted (FD) floating body SOI MOSFET's, and the different body contacts on PD SOI technologies. It is important to note that there is a universal correlation between ac kink effect and Lorentzian-like noise overshoot regardless of whether the body is floating or grounded. In addition, it was found that third-order harmonic distortion is very sensitive to floating body induced kink or deviation on output conductance due to the finite voltage drop of body resistance. These results provide device design guidelines for SOI MOSFET technologies to achieve comparable low-frequency noise and linearity with Bulk MOSFET's     

Gate-induced floating body effect excess noise in partially depleted SOI MOSFETs

Low frequency excess noise associated to gate-induced floating body effect is for the first time reported in Partially Depleted SOI MOSFETs with ultrathin gate oxide. This was investigated with respect to floating body devices biased in linear regime. Due to a body charging from the gate, a Lorentzian-like noise component superimposes to the conventional 1/f noise spectrum. This excess noise exhibits the same behavior as the Kink-related excess noise previously observed in Partially Depleted devices in saturation regime.     

Modeling for floating body effects in fully depleted SOI MOSFETs

A model based on SOI MOSFET and BJT device theories is developed to describe the current kink and breakdown phenomena in thin-film SOI MOSFET drain-source current-voltage characteristics operated in strong inversion. The modulation of MOSFET current by raised floating body potential is discussed to provide an insight for understanding the suppression of current kink in fully depleted thin-film SOI devices. The proposed analytical model successfully simulates the drain current-voltage characteristics of thin-film SOI n-MOSFETs fabricated on SIMOX wafers     

Effects of floating body on double polysilicon partially depleted SOI nonvolatile memory cell

The floating-body effect of nonvolatile memory cells fabricated using partially depleted silicon-on-insulator (SOI) technology has been investigated using two-dimensional numerical device simulation. Compared with similar bulk devices, the floating-body effect of partially depleted SOI MOSFETs introduces instability in the value of the drain current during sensing and extra hot-electron gate current in programming. The effects of the drain-current instability on the error margins in read operation are studied. The floating-body effect is found to be heavily dependent on biasing condition.     

部分耗尽型绝缘体上硅器件体接触结构及新的方法对于对抑制浮体效应的研究

随着SOI CMOS工艺不断缩微,最小栅宽进入几十纳米时,用浮体接触结构抑制浮体效应就越来越无效,这是由于顶层硅的不断减薄带来越来越高的浮体串联电阻,使得堆积在浮体内的载流子越来越难流出体外。文章详细分析了传统体接触结构不能有效抑制浮体效应的原因,并且介绍了新的SOI CMOS结构用来抑制SOI的浮体效应。     

Body-contact self-bias effect in partially depleted SOI-CMOS and alternatives to suppress floating body effect

As SOI-CMOS technology nodes reach the tens of nanometer regime,body-contacts become more and more ineffective to suppress the floating body effect.In this paper,self-bias effect as the cause for this failure is analyzed and discussed in depth with respect to different structures and conditions.Other alternative approaches to suppressing the floating body effect are also introduced and discussed.     

Hot-carrier-induced degradation of drain current hysteresis and transients in thin gate oxide floating body partially depleted SOI nMOSFETs

The impact of hot-carrier degradation on drain current (I_D) hysteresis and switch-off I_D transients of thin gate oxide floating body PD SOI nMOSFETs is analyzed. An extended characterization of these floating body effects (FBEs) is carried out for a wide range of transistor geometries and bias conditions. The results show a link between the hot-carrier-induced damage of the front channel and the reduction of the FBEs. This is further supported by unbiased thermal annealing experiments, which are found to give rise to a partial recovery of the hot-carrier induced damage and FBEs.     

The use of body ties in partially depleted SOI MOSTs operating at cryogenic temperatures

In this paper, the use of a body tie in partially depleted SOI MOSTs operating at 4.2 K is critically discussed. It is shown that there is a considerable improvement in the threshold voltage metastability and the related hysteresis and transient behavior of the drain current. However, the typical floating body effects, like the kink and the parasitic bipolar action are hardly suppressed. This is mainly due to the high series resistance of the body contact, similar as in bulk MOSTs operated at liquid helium temperatures.     

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for     

AC floating-body effects in submicron fully depleted (FD) SOInMOSFETs and the impact on analog applications

We report the impact of submicron fully depleted (FD) SOI MOSFET technology on device AC characteristics and the resultant effects on analog circuit issues. The weak DC kink and high frequency AC kink dispersion in FD SOI still degrade circuit performance in terms of distortion and low-frequency noise requirements. These issues raise concerns about FD devices for mixed-mode applications. Therefore, further device optimization such as source/drain engineering is still necessary to solve the aforementioned issues for FD SOI. On the other hand, partially depleted SOI MOSFET with body contact structures provide an alternative technology for RF/baseband analog applications     

AC behavior of gate-induced floating body effects in ultrathin oxide PD SOI MOSFETs

In this letter we present for the first time an ac analysis of the gate-induced floating body effects (GIFBE) occurring in ultrathin gate oxide partially depleted (PD) silicon-on-insulator (SOI ) MOSFETs due to tunneling gate current. A simple equivalent circuit is proposed, which indicates that the ac behavior of GIFBE is related to the small-signal voltage variations of the floating body region. It also shows that due to the high impedance seen by the body region toward the external nodes, the GIFBE frequency dependence is characterized by a very low cut off frequency (< a few kilohertz), which is consistent with experimental data and circuit simulations performed with BSIMSOI.     

Reducing parasitic BJT effects in partially depleted SOI digital logic circuits

This paper presents four new circuit techniques that reduce the parasitic bipolar junction transistor (BJT) effect in digital dynamic logic circuits in partially depleted silicon-on-insulator (PD-SOI) technology. Simulation results have shown the proposed schemes to be effective at various operating voltages. Fully functional test circuits, incorporating some of the proposed techniques, have been designed, fabricated and tested in a 130 nm IBM PD-SOI technology. The measured silicon hardware data validate the simulation predictions and have demonstrated that the new techniques can be easily incorporated to improve the robustness of PD-SOI dynamic logic circuits.     

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a “C” shape of the threshold voltage corresponding with the second peak in the gm curve.     

Photoluminescence in silicon implanted with erbium ions at an elevated temperature

Photoluminescence spectra of n-type silicon upon implantation with erbium ions at 600°C and oxygen ions at room temperature and subsequent annealings at 1100°C in a chlorine-containing atmosphere have been studied. Depending on the annealing duration, photoluminescence spectra at 80 K are dominated by lines of the Er³⁺ ion or dislocation-related luminescence. The short-wavelength shift of the dislocation-related luminescence line observed at this temperature is due to implantation of erbium ions at an elevated temperature. At room temperature, lines of erbium and dislocation-related luminescence are observed in the spectra, but lines of near-band-edge luminescence predominate.     

Reduced floating body effects in narrow channel SOI MOSFETs

An experimental demonstration is given of the reduction of floating body effects in narrow channel SOI MOSFETs, as manifested by the saturation region subthreshold characteristics, latch-up, and breakdown voltage. The mechanisms responsible for this reduction are explained by original experiments and simulations. These are a deterioration of the carrier lifetime near the channel edges caused by local stress and defects, and a lowering of the source-body built-in potential barrier, resulting from dopant outdiffusion/segregation into the isolation oxide     

Studies of temperature effects in AC thin-film EL devices

The effect of temperature variation of ZnS:Mn AC thin-film EL (ACTFEL device characteristics has been investigated. Systematic observations of electrical and optical properties are used to clarify some of the physical processes in these devices.     

Thermal effects in n-channel enhancement MOSFET's operated at cryogenic temperatures

Thermal effects in n-channel enhancement-mode MOSFET's operated at cryogenic temperatures are discussed. Device heating is identified as the cause of drain current transients and the origin of this phenomenon is considered. Experimental results are presented in which thermal effects are studied as functions of temperature for various gate and drain biases. Drain current is found to be a monitor of device temperature, From an understanding of the thermal behavior of devices, the channel electron mobility can be examined as a function of temperature and gate bias. The observed thermal effects are explained in terms of material and device properties. The implications for future low-temperature CMOS VLSI development are discussed.     

Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI

This study compares the reliability of nMOSFETs with low- and high-doped ultra-thin body and buried oxide (UTBB) with fully depleted (FD) and partially depleted (PD) silicon on insulator (SOI). The high-doped devices display lower off-current leakage performance but more degradation in both hot-carrier stress (HCS) and positive bias temperature instability (PBTI) test at both room temperature and elevated temperature compared with the low-doped devices. The PBTI test indicates that the high-doped devices induce high tunneling leakage and that the degradation is highly associated with temperature. The degradation stabilizes with an increase in stress time. The thinner PD-SOI demonstrates low variation at the threshold voltage and low drive current under HCS. The FD-SOI has better drain leakage control than the PD-SOI.     

A physical model of floating body effects in polysilicon thin film transistors

Based on a closed form of the base–emitter voltage of the parasitic bipolar transistor, a physical model of floating body effects is proposed for polysilicon thin film transistors, which takes into account the polysilicon graded pn junction and the generation rate including the Poole-Frenkel effect. Simulated results by this model are in good agreement with experimental data. It is shown that the action of a parasitic bipolar transistor should be taken into account only when the channel length is short enough due to the much smaller carrier mobility in polysilicon compared with single crystalline silicon. Whereas, the parasitic bipolar transistor gain (β) increases sharply with decreasing the channel length when the channel length is less than 5 μm, which is due to the rapid increase of the base transport factor (_T).     

Clarification of floating-body effects on drive current and shortchannel effect in deep sub-0.25 μm partially depleted SOIMOSFETs

We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 μm floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (V_th) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller V_th-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 μm, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current