A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver

A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR backplane transceiver, and consists of a phase detector, loop filter, phase control logic, and phase interpolator. A unique subsampled architecture makes it possible for a low-power mixed-signal clock recovery loop running at a rate of 6 Gb/s. The proposed architecture has data pattern independent loop bandwidth. Fabricated in a 0.13-/spl mu/m CMOS technology in an area of 280/spl times/100 /spl mu/m/sup 2/, the clock and data recovery loop exhibits a frequency tracking range up to 2000 ppm. The bit error rate is less than 10/sup -12/ with a pseudorandom bit sequence of length 2/sup 31/-1. The power dissipation is 24 mW for clock and data recovery circuits from a single 1.2-V supply.     

Multi-Gb/s silicon bipolar clock recovery IC

A novel clock recovery IC for optical fiber communication systems with data rates up to several Gb/s is presented. It combines nonlinear signal preprocessing directly with a regenerative frequency divider scheme and an external filter in the divider loop. Hence, the center frequency of the filter and the working frequency of the amplifier are halved. The extracted clock frequency corresponds to half the bit rate, as required for many clocked circuit components within fiber optic lines. Two versions of the same IC design, scheduled for two bit rate ranges between 0.3-4 Gb/s, are realized with a conventional Si bipolar process. Clock recovery is demonstrated at 2.2 and 3.52 Gb/s, using both cavity and surface acoustic wave (SAW) filters     

Evaluation of cellular mobile telephone data receivers

Some measurement techniques and results employed to evaluate advanced mobile phone system (AMPS) data receivers being driven by a Rayleigh fading channel are described. These performance measurements were used as a mechanism for comparing the design effectiveness of various bit clock recovery systems. Of five data receiver types evaluated, two models employed a full-wave rectifier in the bit clock recovery system. In this system nominal diode unbalance may cause the derived bit clock to lock 180° from the phase required to properly decode the incoming bit stream. This condition may even occur at high carrier-to-noise ratios when message structures containing long strings of ones or zeros are received. The other data receiver types employed digital signal processing for clock recovery to circumvent this phase ambiguity problem. The performance data of five data receivers are compared to noncoherent frequency-shift keying (FSK) as a model. In most cases, the test results are in good agreement with this model. The performance measurements presented include derived clock jitter and single and average bit error rates as a function of average carrier-to-noise ratios. The implementation of test instrumentation and the interpretation of test results are discussed. The objective is to stress the capability of simulation measurements to evaluate mobile receiver designs in a laboratory environment.     

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/sSONET application

An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV_pp at a bit error rate (BER)=10^-9 . The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply     

A multibitrate burst-mode CDR circuit with bit-rate discriminationfunction from 52 to 1244 Mb/s

We fabricate and assess a clock and data recovery (CDR) circuit with a bit-rate discrimination (BRD) function that can receive burst-mode signals containing packets of different bit rates. The clock recovery circuit in the CDR circuit consists of gated oscillators (GOs) for handling the burst-mode signals, whose bit rates vary with each packet. Moreover, we improve the performance of the clock recovery circuit based on GOs against the bit rate unevenness around each bit rate. By combining an agile clock recovery circuit and a digital BRD circuit, the CDR circuit can handle multiplexed bit rates. Tests show that the circuit offers excellent performance for the multiplexed bit rates of nonreturn-to-zero 52, 155, 622, and 1244 Mb/s     

Bit rate and wavelength transparent all-optical clock recovery scheme for NRZ-coded PRBS signals

All-optical clock recovery from 40-Gb/s nonreturn-to-zero (NRZ) pseudorandom binary sequence data streams based on self-pulsating lasers is presented. A compact preprocessing circuit is utilized to convert an NRZ signal to a pseudoreturn-to-zero sequence before injecting into the optical clock. It comprises a semiconductor optical amplifier followed by a periodical wavelength-division-multiplexing demultiplexer filter. A stable sinusoidal clock signal with a root-mean-square jitter below 700 fs is detected at the output of the self-pulsating laser within data dynamic range of more than 8 dB. The performance of the all-optical clock recovery scheme is investigated by varying the bit rates between 39.81 and 43.02 Gb/s as well as for various wavelengths in the C-band.     

钟控准静态能量回收逻辑电路

钟控准静态能量回收逻辑 (clocked quasi- static energy recovery logic,CQSERL)只在输入信号导致输出状态发生变化的情况下才对电路节点充电 (或者回收 ) ,不需要在每个功率时钟周期循环充电和回收操作 ;CQSERL是单端输入输出逻辑 ,减小了电路实现代价 .设计了 4位 QSERL 串行进位加法器 (RCA)电路 ,和相应的 CMOS电路进行了功耗比较 .功率时钟为 10 MHz时 ,CQSERL 电路功耗是对应 CMOS电路的 35 % .流片实现了一个简单结构的正弦功率时钟产生电路 ,功率时钟的频率和相位与外接系统时钟相同     

10 GHz full-rate clock and data recovery circuit in 0.18 /spl mu/m CMOS without external reference clock

The design of a fully monolithic integrated 10 GHz full-rate clock and data recovery (CDR) circuit in 0.18 /spl mu/m digital CMOS technology, which employs an injection phase-locked loop (PLL) technique is presented. The CDR operating without the external reference exhibits a capture range of 200 MHz while consuming 205 mA current from 1.8 V supply including the output buffer. The recovered clock signal with 250 mV/sub pp/ pseudorandom bit Sequence input data of length 2/sup 31/-1 exhibits 7.9 ps of peak-to-peak (p-p) and 1.1 ps of root-mean-square (RMS) jitter. The measured clock phase noise at 1 MHz offset is approximately -109 dBc/Hz.     

基于FPGA的数字锁相环实现与性能分析

在数字通信系统中,对传输数据的位同步信号提取非常重要.在基于FPGA的数字系统中,通常是设计一个数字锁相环(DPLL)来解决这些问题.文章设计一种新的利用bang-bang鉴相器实现的DPLL,bang-bang鉴相器能直接从接收数据流中提取位时钟信号,且在减少抖动、侪频、时钟恢复和数据同步有很好的优越性.分析了,整个数字锁相环在无高斯白噪声环境下的性能,最后给出了整个锁相环的波形仿真.     

基于随路时钟恢复的多源数据光纤传输系统

针对数据互联网络中多源高速并行数据实时传输的问题,提出了一种基于随路时钟恢复的多源数据光纤传输系统,详细介绍了其工作原理和设计思想.系统将现场可编程逻辑门阵列(FPGA)内部高速收发器与专用数字锁相环相结合,给出了随路时钟恢复与数据流量控制的具体实现过程.相比于现有的各类高速并行数据传输解决方案,该系统具备可软件定义的数据接入能力,也能支持更加灵活的随路时钟动态范围.同时,通过设计精简合理的帧结构,推导数据位宽与随路时钟之间的约束关系,有效提高了系统传输带宽.测试结果表明,该系统工作稳定可靠,实时传输效果好,时钟恢复精度可达100 fs,扩展了串并转换与并串转换技术的应用领域.     

A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter forserial links

A receiver targeting OC-48 (2.488 Gb/s) serial data link has been designed and integrated in a 0.8-μm CMOS process. An experimental receiving front-end circuit demonstrates the viability of using multiple phased clocks to overcome the intrinsic gate-speed limitations in the demultiplexing (receiving) and multiplexing (transmitting) of serial data. To perform clock recovery, data is 3× oversampled so that transitions can be detected to determine bit boundaries. The design of a transmitter for the high-speed serial data is also described. The complete transceiver occupies a die area of ~3×3 mm²     

Word timing recovery in direct detection optical PPM communicationsystems with avalanche photodiodes using a phase lock loop

A technique for word timing recovery in a direct detection optical pulse position modulation (PPM) communication system is described. It tracks on back-to-back pulse pairs in the received random PPM data sequences with the use of a phase locked loop. The experimental system consisted of an AlGaAs laser diode transmitter (λ=833 nm) and a silicon avalanche photodiode photodetector, and its used Q=4 PPM signaling at a source data rate of 25 Mb/s. The mathematical model developed to characterize system performance is shown to be in good agreement with the experimental measurements. Use of this recovered PPM word clock, along with a slot clock recovery system described previously, caused no measurable penalty in receiver sensitivity when compared to a receiver which used common transmitter/receiver clocks. The completely self-synchronized receiver was capable of acquiring and maintaining both slot and word synchronizations for input optical signal levels as low as 20 average detected photons per information bit. The receiver achieved a bit error probability of 10^-6 at less than 60 average detected photons per information bit     

A CMOS 5.4/3.24‐Gbps Dual‐Rate CDR with Enhanced Quarter‐Rate Linear Phase Detector

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter‐rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead‐zone problem of charge pump circuit. A voltage‐controlled oscillator is designed with a ‘Mode’ switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak‐to‐peak jitter is 24.89 ps under 231–1 bit‐long pseudo‐random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm×1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 μm CMOS process.     

A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme

A low-power, single-channel clock-edge modulated serial link has been fabricated in a standard 0.18-mum CMOS technology. The link core size is 343 times 188 mum² for the transmitter and 173 times 83 mum² for the receiver. The link consumes 3.12 mW when operating at 270 Mb/s with a 1.2-V supply. The proposed link transfers all necessary signals between a graphic processor and a mobile display device over a single pair channel, thereby greatly saving the power and cost of the existing full swing parallel lines. The proposed clock edge modulation (CEM) encoding can keep the channel DC-balanced without an additional bit overhead. Since a clock edge is present for each bit, an external reference clock is not needed and its operating frequency can be varied without the possibility of harmonic locking typically found in a referenceless clock and data recovery circuit. A simple DLL-based CEM decoder is described that recovers the data with low power consumption and high jitter tolerance. An analysis of the jitter tolerance to sinusoidal jitter is included along with measured data. The measurement results show jitter tolerance of 20 UI_P-P with 1-MHz sinusoidal jitter. The use of a push-pull voltage-mode driver further reduces the power consumption.     

Dynamics of all-optical clock recovery using two-section index- and gain-coupled DFB lasers

The dynamics of coherent clock recovery (CR) using self-pulsing two-section distributed feedback (TS-DFB) lasers have been investigated. Both simulation and experimental results indicate fast lockup and walk-off of the clock-recovery process on the order of nanoseconds. Phase stability of the recovered clock from a pseudorandom bit sequence (PRBS) signal can be achieved by limiting the detuning between the frequency of free-running self-pulsation and the input bit rate. The simulation results show that all-optical clock recovery using TS-DFB lasers can maintain a better than 5% clock phase stability for large variations in power, bit rate, and optical carrier frequency of the input data and therefore is suitable for applications in optical packet switching.     

Digital burst mode clock recovery technique for fiber-optic systems

We present a clock recovery technique for burst mode systems that performs the functions of clock phase recovery, burst synchronization (to determine the first data bit in the burst), and timing alarm generation (to maintain bursts within their designated time slots). The method is based on the use of a correlation algorithm in which the incoming preamble containing a `0 1 0' bit sequence is sampled with multiple clock phases and correlated with stored, time delayed versions of the same sequence. The method was implemented in a 0.7 μm CMOS Application Specific Integrated Circuit (ASIC). Measurements of the phase tracking characteristics over the frequency range of 38 to 90 MHz are presented. Bit error rate measurements made using the device in a burst mode fiber-optic receiver operating at 51.84 Mb/s were also performed, where it was found that the device performed well and was able to perform clock extraction with a penalty of approximately 2 dB with respect to an ideal clock extraction system     

A 750 MHz semi-digital clock and data recovery circuit with 10~(-12) BER

A semi-digital clock and data recovery（CDR） is presented.In order to lower CDR trace jitter and decrease loop latency,an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13μm standard 1P8M CMOS process,our CDR is integrated into a high speed serial and de-serial（SERDES） chip.Measurement results of the chip show that the CDR can trace the phase of the input data well and the RMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency,while the bit error rate of the recovery data is less than 10×10^-12.     

2.5Gb/s/ch 0.18μm CMOS数据恢复电路

设计了一个应用于SFI-5接口的2.5Gb/s/ch数据恢复电路.应用一个延迟锁相环,将数据的眼图中心调整为与参考时钟的上升沿对准,因而同步了并行恢复数据,并降低了误码率.采用TSMC标准的0.18μm CMOS工艺制作了一个单通道的2.5Gb/s/ch数据恢复电路,其面积为0.46mm2.输入231-1伪随机序列,恢复出2.5Gb/s数据的均方抖动为3.3ps.在误码率为10-12的条件下,电路的灵敏度小于20mV.     

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection

A fully integrated clock and data recovery circuit (CDR) using a multiplying shifted-averaging delay locked loop and a rate-detection circuit is presented. It can achieve wide range and low jitter operation. A duty-cycle-insensitive phase detector is also proposed to mitigate the dependency on clock duty cycle variations. The experimental prototype has been fabricated in a 0.25-/spl mu/m 1P5M CMOS technology and occupies an active area of 2.89 mm/sup 2/. The measured CDR could operate from 125 Mb/s to 2.0 Gb/s with a bit error rate better than 10/sup -12/ from a 2.5-V supply. Over the entire operating frequency range, the maximum rms jitter of the recovered clock is less than 4 ps.     

Data clock jitter in supersampling multiplex transmission

An estimate of the signal/noise ratio (SNR) degradation at the output of a data clock timing recovery circuit for multiplexed transmission using supersampling is presented. Both the effects of sampling clock jitter and data edge uncertainty are accounted for to determine the performance degradation as a function of the sampling frequency/data bit rate ratio D.