基于SOI衬底的射频电感优化设计

比较了SOI RF电感与体硅电感的性能,并根据模拟结果分析了电感中空面积,电感形状结构,金属宽度、间距对SOI电感品质因数Q、自谐振频率、电感量L的影响,最后提出了一种基于SOI衬底RF电感的优化设计原则.以往射频集成电感性能的比较并不固定电感值,而文中全部参数的变化都是在电感值相同的情况下进行比较.     

片上螺旋电感集总模型中衬底因子的分析与拟合

石英、高阻SOI、高阻硅等衬底上实现的电感具有比低电阻率衬底的电感更优的高频性能,因而研究基于不同衬底的电感性能,并在高频模型中进行精确的衬底因子表征就显得十分重要.综合考虑高频下的趋肤效应和邻近效应及衬底电磁损耗对电感性能的影响,实现了片上螺旋电感的集总元件模型,并通过与SOI、石英衬底的电感仿真参数及高阻硅衬底的电感测试参数进行了模型验证,结果表明,该模型拟合的S参数及Q值曲线能与仿真及测试结果吻合,同时模型中衬底因子的提取值与衬底性质相符合,因而该模型适用于片上电感的模拟与设计.     

基于玻璃的高性能电感的设计与实现

作为射频系统中的关键元件,电感的性能会影响整个系统的稳定性,传统的硅基电感由于较大的衬底损耗导致其Q值较低,无法满足射频系统的要求。因此为了提高电感性能,采用性能优良、损耗较低的玻璃作为衬底材料,首先提出了两种结构的电感,分别为埋入玻璃衬底的螺旋电感和基于TGV的三维电感,通过仿真研究了电感性能,并将其与相同结构下的硅基电感的性能进行了比较,并对两种电感分别进行结构优化,最后详细介绍了电感的加工工艺以及实物成果。研究结果表明,采用玻璃作为衬底可以大幅度提高电感的Q值,其Q值可达60以上,相比于硅基电感,其Q值分别提高了137.7%和55%,且通过改善电感自身的结构参数,可以进一步获得高性能的电感。     

50nm SOI-DTMOS器件的性能

利用二维器件模拟软件ISE对5 0nm沟道长度下SOI DTMOS器件性能进行了研究,并与常规结构的SOI器件作了比较.结果表明,在5 0nm沟长下,SOI DTMOS器件性能远远优于常规SOI器件.SOI DTMOS器件具有更好的亚阈值特性,其亚阈值泄漏电流比常规SOI器件小2～3个数量级,从而使其具有更低的静态功耗.同时,SOI DTMOS器件较高的驱动电流保证了管子的工作速度,并且较常规SOI器件能更有效地抑制短沟道器件的穿通效应、DIBL及SCE效应,从而保证了在尺寸进一步减小的情况下管子的性能.对SOI DTMOS器件的物理机制进行了初步分析,揭示了其性能远优于常规结构的物理本质     

短沟道SOI MOSFET栅结构研究与进展

系统比较了几种不同栅结构短沟道SOI MOSFET的性能,包括短沟道效应、电流驱动能力、器件尺寸等特性,获得了栅的数目与短沟道SOI器件的性能成正比的结论.介绍了两种新的短沟道SOI器件栅结构:Π栅和Ω栅,指出了短沟道SOI MOSFET栅结构的发展方向.     

SOI横向双晶体管结构研究

本文首先概括地介绍了体硅、SOI纵向双极晶体管和横向双极晶体管的各自特点，并简要地阐述了SOI横向双极晶体管的发展；其次，对各种SOI横向双极晶体管的结构与性能进行了分析研究；最后，我们认为SOI横向双极晶体管是一种比较理想的双极器件，不失为SOI／BiCMOS的理想选择。     

基于SiGe HBT 的射频有源电感的设计

基于回转器原理,提出利用两个SiGe异质结晶体管,通过采用不同组态构成四种射频有源电感,其中包括两种正电感和两种负电感,并对它们的性能进行了比较.结果表明,共射组态与共集组态构成的有源电感的性能最优异,并就此做了详细讨论.在带宽为1～15.8 GHz的范围内,其电感值可以达到1 nH以上,电感的品质因数最大值达到75.4.通过调节晶体管的偏置电压,有源电感的电感峰值在1.268 nH-1.914 nH范围内变化.电感值的可调谐性对增强电路设计的可复用性及灵活性具有现实意义.     

基于SOI结构的SiGe HBT频率特性研究

基于SOI技术原理,模拟仿真了SOI结构SiGe HBT的频率特性,并与相同条件下体SiGe HBT频率特性进行了比较分析。仿真结果显示,SOI结构中埋氧层BOX的引入,可使SOI结构SiGe HBT集电极-基极电容Ccb和衬底-基极电容Csb最大降幅分别达94.7%和94.6%,且最高振荡频率fmax增加2.7倍。研究结果表明,SOI结构大幅度改善了SiGe HBT的频率性能,适用于高速、高功率集成电路技术。     

RF平面螺旋微电感计算机模拟研究

应用Greenhouse法对RF平面螺旋微电感进行了计算机模拟,探明了微电感品质因数Q值在高频域内的变化规律,得出了微电感金属层厚度、线宽、线间距及线圈数与RF平面螺旋微电感Q值的对应关系。研究发现,RF平面螺旋微电感的Q值在高频域内随频率增加而呈现先升高后下降的趋势,Q值存在峰值;微电感Q值在某一频率范围内随微电感金属层厚度、线宽的增加而增大;随线间距的增加,微电感的低频性能下降而高频(>1GHz)性能升高;当微电感直径一定时,随线圈数的增加,Q值有下降的趋势。     

0.6μm SOI NMOS器件ESD性能分析及应用

ESD设计是SOI电路设计技术的主要挑战之一,文章介绍了基于部分耗尽0.6μm SOI工艺所制备的常规SOI NMOS器件的ESD性能,以及采用改进方法后的SOI NMOS器件的优良ESD性能。通过采用100ns脉冲宽度的TLP设备对所设计的SOI NMOS器件的ESD性能进行分析,结果表明：SOI NMOS器件不适合...     

一种新的SOI射频集成电路结构与工艺

立足于与常规CMOS兼容的SOI工艺，提出了电子束／I线混合光刻制造SOI射频集成电路的集成结构和工艺方案。该方案只使用9块掩模版即完成了LDMOS、NMOS、电感、电容和电阻等元件的集成。经过对LDMOS、NMOS的工艺、器件的数值模拟和体硅衬底电感的初步实验，获得了良好的有源和无源器件特性，证明这一简洁的集成工艺方案是可行的。     

Surface micromachined solenoid on-Si and on-glass inductors for RFapplications

RF performance of surface micromachined solenoid on-chip inductors fabricated on a standard silicon substrate (10 Ω·cm) has been investigated and the results are compared with the same inductors on glass. The solenoid inductor on Si with a 15-μm thick insulating layer achieves peak quality (Q-) factor of 16.7 at 2.4 GHz with inductance of 2.67 nH. This peak Q-factor is about two-thirds of that of the same inductor fabricated on glass. The highest performance has been obtained from the narrowest-pitched on-glass inductor, which shows inductance of 2.3 nH, peak Q-factor of 25.1 at 8.4 GHz, and spatial inductance density of 30 nH/mm². Both on-Si and on-glass inductors have been modeled by lumped circuits, and the geometrical dependence of the inductance and Q-factor have been investigated as well     

Analytical formula for inductance of metal of various widths in spiral inductors

This paper presents an analytical formula for the inductance of an inductor with the layout of variable metal width, based on the quasistatic approximation. Experimental results indicate that the analytical formula is feasible. A layout with metal whose width increases monotonously from the inner turn has a higher Q value than other configurations of the metal with the same inductance. This information will be of help in designing high-performance inductors for RF integrated circuit applications.     

CMOS差分电感和串联电感对的建模与分析

该文分析了基于中芯国际0.18m CMOS工艺的差分电感和串联电感对,提出了电感在射频CMOS差分电路中的应用原则。研究了串联电感对之间的串扰效应,并提出了能准确反映互感效应、衬底容性损耗效应以及线圈间容性耦合的完整串扰模型。最后,通过对一组变间距的电感对进行测量分析,验证了该模型的准确性和适用性。     

Micromachined bridge-shaped spiral inductor on anodised aluminium substrate

Noble micromachined integrated spiral inductors on anodised aluminium substrate are presented. The RF characteristics of the fabricated inductors have been measured. A high peak Q-factor of 82.36 at 4.2 GHz has been achieved with inductance of 2.59 nH (at 2 GHz) and a self-resonant frequency of around 10 GHz. This work demonstrates that an integrated passive device on anodised aluminium substrate has a competitive RF performance compared to that of LTCC technology.     

Investigation of a multigigahertz MOSFET amplifier with an on-chipinductor fabricated on a SIMOX wafer

This paper describes a technology that can be used to integrate multigigahertz RF circuits into large-scale digital circuits. Spiral inductors and a MOSFET amplifier with an inductive load were fabricated on a SIMOX wafer in order to demonstrate the feasibility of SOI technology. With a 1-V supply voltage, peaking of the amplifier gain was observed, as expected from circuit simulations, at 1-4 GHz. These results show that RF circuits with inductors can be implemented on a SIMOX wafer by using the conventional digital CMOS LSI process     

Modeling and Layout Optimization of Differential Inductors for Silicon-Based RFIC Applications

A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential inductance or operating frequency increases, interactions between metallization resistive and substrate losses discourage the use of large widths as it consumes silicon area and degrades device performance.     

A Physical Model for On-Chip Spiral Inductors With Accurate Substrate Modeling

A physical-based analytical model for on-chip inductors is developed. A ladder structure is used to model the skin and proximity effects in metal lines. The substrate electric and substrate magnetic losses are accurately modeled by RC and RL ladder structures, respectively. The effective inductance reduction due to the eddy current in the lossy silicon substrate at high frequency is modeled by a negative mutual inductance between the inductor and the substrate. All the model parameters can be calculated from the layout and process parameters. On-chip inductors with different geometries and substrate resistivities were fabricated for the verifications. The measured results are in very good agreement with the proposed model. This generic model can be applied to various substrate resistivities; thus, it is suitable for different technologies. This model can facilitate the design and optimization of on-chip inductors for RF IC applications     

Equivalent Circuit Analysis of an RF Integrated Inductor with Ferrite Thin-Film

针对已制作并发表的一种新型铁氧体磁膜结构射频集成微电感进行了等效电路分析.阐述了磁性铁氧体薄膜对电感的感值(L)和品质因数(Q)的增强作用.对射频测试结果进行了电路元件参数提取.结果表明,与空气芯无磁膜微电感相比,磁膜结构微电感的L和Q在2GHz处分别提高了17%和40%.等效电路分析和测试结果均证明了铁氧体薄膜的引入对增强射频集成微电感性能的作用显著.     

MEMS技术制作的螺线管微电感

考虑和分析了螺线管微电感的几何结构参数对微电感性能的影响,利用MEMS技术制作了四种不同几何结构的高性能射频螺线管微电感。这些微电感采用铜线圈,以减小线圈寄生电阻,且制作工艺简单,成本低,与IC相兼容。测试结果表明,微电感在较宽的工作频率范围内具有较高的Q值,在频率分别为6 GHz,4.4 GHz,5.8 GHz和5.6 GHz,微电感Q峰值为38,19.1,24.1和21.9,所对应的电感量为1.81 nH,1.07 nH,1.03 nH和1.17 nH。