Chair's Introduction to 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis

Based on the recommendation of ICTD'09 TPC members, this Special Issue of the Journal of Electronic Science & Technology of China (JESTC) contained 22 high quality papers selected from the Proceedings of 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis (ICTD'09) which is fully sponsored by the IEEE Circuits and Systems Society (CASS), and is technically co-sponsored by the University of Electronic Science and Technology of China (UESTC), the Chinese Institute of Electronics (CIE), the China Instrument & Control Society (CIS), and organized by UESTC.     

Characteristic Investigation of New Pathological Elements

A characteristic investigation of the new pathological elements (i.e voltage mirror and current mirror) has been presented. Many nullor-mirror equivalences are explored. The circuit cascadability is discussed with nullor and mirror concepts. Also, the conventional inverse network transformation has been extended for applying to the circuits with current mirror output. To demonstrate the use of presented properties, practical examples have been given. The derived circuits have been verified with HSPICE simulation and the simulation results confirm with our theoretical prediction.Hung-Yu Wang was born in Kaohsiung, Taiwan, Republic of China, on January 4, 1969. He received the Ph.D. degree in optical sciences from National Central University, Chung-Li, Taiwan in 2002.Since 1993 he has worked on promoting the prototyping IC implementation of academic researches, and propelling the collaboration of the academia and industries in Chip Implementation Center (CIC), National Science Council of the Republic of China. In 2003 he became a researcher and the deputy director in Division of Chip Implementation Service of CIC. He is currently working on South Region Office of National Chip Implementation Center, National Applied Research Laboratories as a researcher and the department manager. His research interests are in current-mode circuits design, analog IC design and analog IP design.Ching-Ting Lee was born in Taoyuan, Taiwan, R.O.C., on November 1, 1949. He received his B.S. and M.S. in Electrical Engineering Department of the National Cheng-Kung University, Taiwan, in 1972 and 1974, respectively. He received Ph.D. degree in Electrical Engineering Department from the Carnegie-Mellon University, Pittsburgh, PA, in 1982.He worked on Chung Shan Institute of Science and Technology, before he joined the Institute of Optical Sciences, National Central University, Chung-Li, Taiwan, as a Professor in 1990. He works on National Cheng-Kung University as the dean of Electrical Engineering and Computer Science and the professor or the Institute of Microelectronics, Department of Electrical Engineering in 2003. His current research interests include theory, design, and application of guided-wave structures and devices for integrated optics and waveguide lasers. His research activities have also involved in the research concerning semiconductor lasers, photodetectors and high-speed electronic devices, and their associated integration for electrooptical integrated circuits. He received the outstanding Research Professor Fellowship from the National Science Council (NSC), R.O.C. in 2000 and 2002. He also received the Optical Engineering Medal from Optical Engineering Society and Distinguish Electrical Engineering professor award from Chinese Institute of Electrical Engineering Society in 2003.Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of Department of Electronic Engineering. His biography is included in the 7th Edition (2003–2004) of Who’s Who in Science and Engineering.His current researches include current-mode circuits design, VLSI design, analog IC design and analog IP design.     

Design and implementation of an optimised wireless pressure sensor for biomedical application

This paper presents design and implementation of a wireless pressure sensor system for biomedical application. The system consists of a front-end Micro-Electro- Mechanical System (MEMS) sensing capacitor along with an optimised MEMS-based oscillator for signal conditioning circuit. In this design, vertical fringed comb capacitor is employed due to the advantages of smaller area, higher linearity and larger full scale change in capacitance compared to parallel plate counterparts. The MEMS components are designed in Coventorware design suite and their Verilog-A models are extracted and then imported to Cadence for co-simulation with the CMOS section of the system using AMI 0.6-micron CMOS process. In this paper, an optimisation method to significantly reduce the system power consumption while maintaining the system performance sufficient is also proposed. A phase noise optimisation approach is based on the algorithm to limit the oscillator tail current. Results show that for the pressure range of 0–300 mmHg the device capacitance range of 1.31 pF – 1.98 pF is achieved which results in a frequency sweep of 2.54 GHz – 1.95 GHz. Results also indicate that a 42% reduction of power consumption is achieved when the optimisation algorithm is applied. This characteristic makes the sensor system a better candidate for wireless biomedical applications where power consumption is the major factor. Hai Phuong Le received his B.E. (Hons) degree in Electronic and Computer System Engineering from University of Tasmania, Hobart, Australia in 2000. He received his Ph.D. degree in Microelectronics from Victoria University, Melbourne, Australia in 2005. At present, he is a post-doctoral research fellow and lecturer in the Centre for Telecommunications and Microelectronics, Victoria University. His research and teaching interests include data acquisition system, mixed-signal integrated circuit design and wireless smart sensor systems. Kriyang Shah received his B.E. Degree in Electronics and Communication Engineering from Sardar Patel University, Vallabh Vidyanagar, Gujarat, India and his Master Degree in Microelectronics in 2004. He is currently a Ph.D. research student in the Centre for Telecommunications and Microelectronics, Victoria University, Melbourne, Australia. His research interests include MEMS Sensors, RF MEMS, process integration for MEMS and CMOS and MEMS-CMOS co-simulation. Jugdutt (Jack) Singh received his B.Sc. in Electronics Engineering from University of Brighton, UK and M.Sc. in Electronics Engineering from University of Alberta, Canada in 1978 and 1986 respectively. He completed his Ph.D. at Victoria University, Australia in 1997. Since 1989 he has been at Victoria University, Melbourne, Australia. Currently he is a Professor of Microelectronics in the Centre for Telecommunications and Microelectronics at Victoria University. His major area of research interests are in the RF, analog and mixed signal design, reconfigurable architectures, low power VLSI circuits and systems design. He has published number of articles in education and research in microelectronics and small technologies area. Aladin Zayegh received his B.E. degree in Electrical Engineering from Aleppo University in 1970 and Ph.D. degree from Claude Bernard University, France in 1979. In 1980, he joined the Faculty of Engineering, Tripoli, Libya. Since 1984 he has held lecturing position at Victoria University, Melbourne, Australia. He is currently an Associate Professor and the Head of School in the School of Electrical Engineering, Faculty of Health, Engineering and Engineering and Science at Victoria University. His research interest includes microprocessor-based system, instrumentation, data acquisition and interfacing, and microelectronics.     

Phase Noise Effects and Mitigation in OFDM Systems over Rayleigh Fading Channels

In this paper, we provide an exact analysis of phase-noise effects on orthogonal frequency division multiplexing (OFDM) performance. We focus on the phase-noise inter-carrier interference (ICI) and derive a closed-form expression for the signal-to-interference-noise ratio (SINR), which helps in understanding how system behavior changes with a certain parameter. An ICI reduction (ICIR) scheme was proposed in [14] and the algorithm performance over AWGN channel was thoroughly studied. In this paper, we further extend this work to Rayleigh fading channel and investigate the effects of multipath fading on the phase-noise mitigation. It is shown by the study that the ICIR algorithm reduces the phase-noise ICI a great deal before channel estimation and improves greatly system performance. Finally, numerical results show the effectiveness of the proposed approaches. Guanghui Liu was born in Sichuan, China, in 1976. He received the B.S. degree from Sichuan Teachers College, Nanchong, Sichuan, China in 1999, received the M.Sc. and Ph.D. degrees in electronic engineering from University of Electronic Science and Technology of China (UESTC), Chengdu, Sichuan, China, in 2002 and 2005 respectively. Dr. Liu serves as a reviewer for the IEEE Transactions on Communications, the IEEE Transactions on Broadcasting and the IEEE Transactions on Wireless Communications. As a research engineer, he is now with Samsung Electronics, Suwon, Republic of Korea. His research interests include synchronization, channel estimation and equalization, phase-noise suppression in OFDM communication systems. Weile zhu was born in Sichuan, China, in 1940. Since 1988 he has been a professor of signal processing with University of Electronic Science and Technology of China, Chengdu, China. He was a visiting scholar researching image processing in University of Illinois from 1980 to 1981, researching pattern recognition in Purdue University from 1982 to 1983, and researching intelligent robot in Stanford University from 1990 to 1991. His research interests include digital video codec and transmission, multicarrier modulation, and HDTV etc.     

Analog behavioral modeling by multi-companding and wavelet collocation method

In this paper, we develop a wavelet collocation method with multi-companding for behavioral modeling of analog circuits. In the multi-companding procedure, the nonlinear companding algorithm is developed to control the error distribution continuously, while the adaptive scheme is employed to reduce the number of used wavelets. Consequently, the proposed multi-companding algorithm can not only modify the modeling error distribution continuously but also decrease the number of basis functions efficiently. Moreover, the companding function generation is automatic and can be applied for the behavioral modeling of any analog circuits. Jun Tao received the B.S degree in electrical engineering from Fudan University, China, in 2002. Now she is currently working toward the Ph.D. degree in micro-electronic engineering at the Fudan University. Her research interest includes analog behavioral modeling, analog circuit simulation and DFM. Xuan Zeng (M97) received the B.Sc. and Ph.D. degrees in electrical engineering from Fudan University, Shanghai, China, in 1991 and 1997, respectively. She joined the Electrical Engineering Department, Fudan University in 1997 and became a full professor in Microelectronics Department in 2001. Now she serves as the Vice Director of ASIC & System State key Lab. and the Associate Head of Microelectronics Department Fudan University. She was a visiting professor in the Electrical Engineering Department, Texas A&M University, USA and Microelectronics Department of TU Delft, Netherland in 2002 and 2003 respectively. Her research interests include DFM, analog and mixed signal design automation (behavioral modeling, circuit simulation and analog layout generation), high speed interconnect analysis and design and ASIC design. Dr. Zeng received the Cross-Century Outstanding Scholar Award from the Ministry of Education of China in 2002. She was selected into “IT Top 10” in Shanghai China in 2003. She served in the technical program committee of IEEE/ACM ASP-DAC in 2000 and 2005. Dian Zhou received the B.S degree in physics and M.S degree in electrical engineering from Fudan University, China, in 1982 and 1985, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois in 1990. He joined the University of North Carolina at Charlotte as an assistant professor in 1990, where he became an associate professor in 1995. He joined the University of Texas at Dallas as a full professor in 1999, and joined Fudan university as a Changjiang Professor in 2003 (on-leave from the University of Texas at Dallas). Currently, he serves as the dean of Microelectronics School, director of National Key Lab. on ASICs and Systems, and director of Miro-nano-electronics Innovation Platform at Fudan University. His research interests include: High-speed VLSI systems, CAD tools, mixed-signal ICs, and algorithms. Charles Chiang received his Bachelor degrees from the Department of Political Science, Tunghai University at Taichung, Taiwan in 1980, and Department of Computer Science, New Mexico State University, Las Cruces, New Mexico in 1986. Then he had his Masters and Ph.D. degree from the Department of Electrical Engineering and Computer Science, Northwestern University, Illinois in 1988 and 1991, respectively. After working at IBM and EDA companies for 10 years, he joined the Advanced Technology Group at Synopsys, Inc. in 2001. His research interests include routing, placement, floorplan, and signal integrity. His main research focus is now on design for manufacturability (DFM). Dr. Chiang has been a Senior Member of IEEE since 1998. He received the Superior Design Recognition award and the ADAL award from IBM Rochester in 1993 and 1994, respectively. He is one of the top 15 winners with new patent filing in 2005 and 2006 in Synopsys. He has served on the technical committee of ICCAD from 2004 to 2006, on that of Field Programming Logic (FPL) from 2002 to 2003, as well as on the committee of ASP-DAC in 2007. He has published more than 40 technical papers and filed 10 US patents.     

A Stereo Multi-Rate Audio Front-End Suitable for Mobile Multimedia Applications

A flexible, high quality audio front-end integrated circuit with low power consumption is presented. Targeted for the world-wide (GSM) mobile communication system, it is capable of stereo and mono reception and transmission, supports narrow voice-band as well as wide voice-band modes, FM radio and MP3 stereo play-back. The front-end provides a low-noise bias voltage for microphones as well as hands-free buffers driving 8Ω loads in bridge tied load configuration and two earphone outputs for stereo. The front-end is highly area-efficient, occupying 1.92 mm² in a 0.25-μ m CMOS technology. Measured results show a maximum power consumption of 11.8 mW at 2.65 V analog and 1.65 V digital supply.Barbara Baggini received the Laurea degree (summa cum laude) in electronic engineering from the University of Pavia, Pavia, Italy, in 1987. She joined the Microelectronics Laboratory at the University of Pavia and worked in the field of switched capacitor filters and high-speed data converters sponsored by STMicroelectronics. From 1988 to 1996 she joined Italtel where she was involved in the development of mixed signal front-end ICs for mobile communications.She is currently with Philips Semiconductors, Switzerland. Her main research interests are in the area of analysis and design of analog and digital low-power circuits for mobile communications.Willem H. Groeneweg received a M.Sc. degree in electrical engineering from Delft University of Technology, Delft, The Netherlands, in 1971.After his military service, he joined the RCA Corporation in Zurich, Switzerland, where he developed bipolar integrated circuits and systems for video processing. In 1984 he started working in the Landis {&} Gyr Central Laboratory on CMOS integrated circuits for building automation. From 1989 on he developed bipolar mixed-signal circuits using ASIC’s from Plessey Semiconductors. Since 1993 he is with the Cellular Systems group of Philips Semiconductors in Zurich. One of his tasks there is the development of CMOS integrated circuits for mobile telephones, mainly in the field of analog and mixed signal audio circuits. Mr. Groeneweg holds 13 patents and has two applications pendingClaudio Schaitwas born on October 16, 1972, in Sorengo, Switzerland. He received the Dipl. Ing. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, in 1999.From June 1999 to October 2000 he worked as Radio Access System engineer for Nokia, Switzerland. In November 2000 he joined Philips Semiconductor, Zurich, Switzerland as Development Engineer. His research interests are in design of CMOS Analog Baseband and Audio Signal Processing for telecom applications.     

Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors

Switched current (SI) circuits use analogue memory cells as building blocks. In these cells, like in most analogue circuits, there are hard-to-detect faults with conventional test methods. A test approach based on a built-in dynamic current sensor (BIDCS), whose detection method weights the highest frequency components of the dynamic supply current of the circuit under test, makes possible the detection of these faults, taking into account the changes in the slope of the dynamic supply current induced by the fault. A study of the influence of these faults in neighbouring cells helps to minimize the number of BICS needed in SI circuits as is shown in two algorithmic analogue-to-digital converters. Yolanda Lechuga received a degree in Industrial Engineering from the University of Cantabria (Spain) in April 2000. Since then, she has been collaborating with the Microelectronics Engineering Group at the University of Cantabria, in the Electronics Technology, Systems and Automation Engineering Department. Since October 2000 she has been a post-graduate student, to be appointed as lecturer at this university, where she is working in her Ph.D. She is interested in supply current test methods, fault simulation, BIST and design for test of mixed signal integrated circuits. Román Mozuelos received a degree in Physics with electronics from the University of Cantabria, Spain. From 1991 to 1995 he was working on the development of quartz crystal oscillators. Currently, he is a Ph.D. student and an assistant teacher at the University of Cantabria in the Department of Electronics Technology. His interests include mixed-signal design and test, fault simulation, and supply current monitoring. Miguel A. Allende received his graduate degree in 1985 and Ph.D. degree in 1994, both from the University of Cantabria, Santander, Spain. In 1996, he became an Assistant Professor of Electronics Technology at the same Institution, where he is a member of the Microelectronics Engineering Group at the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. His research interests include design of VLSI circuits for industrial applications, test and DfT in digital VLSI communication circuits, and power supply current test of mixed, analogue and digital circuits. Mar Martínez received her graduate degree and Ph.D. from the University of Cantabria (Spain) in 1986 and 1990. She has been Assistant Professor of Electronic Technology at the University of Cantabria (Spain) since 1991. At present, she is a member of the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. She has participated in several EU and Spanish National Research Projects. Her main research interest is mixed, analogue and digital circuit testing, using techniques based on supply current monitoring. She is also interested in test and design for test in digital VLSI circuits. Salvador Bracho obtained his graduate degree and Ph.D. from the University of Seville (Spain) in 1967 and 1970. He was appointed Professor of Electronic Technology at the University of Cantabria (Spain) in 1973, where, at present, he is a member of the Electronics Technology, Systems and Automation Engineering Department in the Industrial and Telecommunication Engineering School. He has participated, as leader of the Microelectronics Engineering Group at the University of Cantabria, in more than twenty EU and Spanish National Research Projects. His primary research interest is in the area of test and design for test, such as full scan, partial scan or self-test techniques in digital VLSI communication circuits. He is also interested in mixed-signal, analogue and digital test, using methods based on power supply current monitoring. Another research interest is the design of analogue and digital VLSI circuits for industrial applications. Prof. Bracho is a member of the Institute of Electrical and Electronic Engineers.     

Guest Editorial Brain-Computer Interface： Today and Tomorrow

As the invited editor of this special issue on braincomputer interface （BCI）, I am pleased to give a comment on the state-of-the-art with the introduction of recent advances made at the Chengdu BCI Group, University of Electronic Science and Technology of China （UESTC）.     

Design of low noise charge amplifier in sub-micron technology for fast shaping time

A discussion of the noise optimisation of the fast charge sensitive amplifier (CSA) for imaging systems using highly segmented semiconductor detectors is presented. In such systems a limited power dissipation per single channel is available while a good noise performance and a fast signal processing time are required. This paper describes the CSA noise optimisation for several CMOS technology generations with the minimum transistor gate length ranging from 0.13μm to 0.8μm and for a detector capacitance in the range from 0.5 pF to 12 pF. In a well-designed CSA, followed by a fast shaper stage, an equivalent noise charge (ENC) is dominated by the thermal noise of an input MOS transistor. In the applications considered the input transistor usually works in a moderate inversion region where no simple formula for the noise performance exists. Our analyses are made using a simplified EKV model and are compared with HSPICE simulations using BSIM3v3 models. We show several novel aspects of the noise optimisation of the CSA regarding the optimum transistor width and the sensitivity of the ENC to this width. Paweł Gryboś was born in Bielsko-Bielsko, Poland, in 1967. He received M.Sc. degree in electronics in 1991, Ph.D. degree in physics in 1995 and habilitation Ph.D. degree in electronics in 2004 from the AGH University of Science and Technology in Cracow, Poland. His current research interests are in the areas of designing and testing of low noise, multichannel ASICs for physics and neurobiology applications. Marek Idzik graduated in Electronic Engineering (1990) at University of Science and Technology of Cracow and in Theoretical Physics (1991) at Jagiellonian University of Cracow, Poland. Received his Ph.D. in Experimental Physics (1995) at University of Science and Technology of Cracow. Since 1995 Assistant Professor at University of Science and Technology of Cracow. Research activity: design of VLSI electronics, physics of semiconductor detectors, heavy ion physics. Teaching activity in international schools: ICFA (1997) Leon, Mexico, ICFA (2004) Rio de Janeiro, Brasil. More than 50 scientific publications on international journals. Andrzej Skoczeń was born in Cracow, Poland, on February 25, 1962. He is an assistant professor in Nuclear Electronics Department at the Faculty of Physics and Applied Computer Science at the AGH University of Science and Technology in Cracow. He received his Ph.D. in physics in the field of semiconductor devices in May 1993. He is involved with problems concerning project and design of integrated circuits for physics experiments at DESY (Hamburg), GSI (Darmstadt) and CERN (Geneva). He deals with radiation sensors applications, CAD modeling, characterization, and VLSI mixed signal design. At his home institution he works also as a lecturer in the field of introduction to physics and electronics.     

A 3-A CMOS low-dropout regulator with adaptive Miller compensation

A 3-A CMOS low-dropout regulator (LDO) is presented by utilizing adaptive Miller compensation (AMC) technique, which provides high stability, as well as fast line and load transient responses. The proposed LDO has been fabricated in a standard 0.5 μm CMOS technology, and the die area is small as 1330 μm × 1330 μm with the area-efficient waffle layout for power transistors. Both load and line regulation are less than ±0.1%. And the output voltage can recover within 80 μs for full load changes. The power–supply rejection ratio (PSRR) at 20 KHz is −30 dB. Moreover, it is stable enough with a ceramic capacitor small to 2.2 μF, and the added series resistance is not needed. Xinquan Lai received his BSc degree in Technical Physics in 1987, and MSc degree in Electronic Engineering in 1993, both from the Xidian University, Xi’an, China. And he received a PhD degree in Computer Science & Engineering from the Northwestern Polytechnical University (NPU) in 1998. He is currently a professor in Xidian University. His present research interests include mixed signal VLSI/ASIC and SOC design, CMOS Sensor, and power management IC design, validation, test and other relative theories. Jianping Guo was born in Jiangxi, P.R. China in 1981. He received the BSc and MSc degrees in electronic engineering from Xidian University, Xi’an, China, in 2003 and 2006, respectively. He is currently severed as power management IC engineer in Xi’an Deheng Microelectronic Inc. His research interest involves power management IC design such as LDO linear regulator, DC-DC switching regulator etc. Zuozhi Sun was born in Zhejiang, P. R. China in 1978. He received the BSc and MSc degrees in electronic engineering from Xidian University, Xi’an, China, in 2000 and 2003, respectively. He joined Xi’an Deheng Microelectronic Inc. in 2003, where he works on development of power management IC. His research interest involves power management IC, audio amplifier etc. Jianzhang Xie received his BSc and MSc degrees in electronic engineering from Xidian University, Xi’an, China, in 1998 and 2005, respectively. He joined AIWA (Shenzhen) Ltd. as an electronic circuit designer in 1998, and now he is severed as an analog and mixed IC engineer in RENEX Technology (Shanghai) Ltd. His research interest involves power management IC, PLLs and high speed communication circuits.     

A low-cost programmable clock generator for switched-capacitor circuit applications

This paper presents two improved circuit techniques that allow the design of a low-cost programmable clock generator using a ring oscillator for low-frequency switched-capacitor applications. The first technique aims at reducing the frequency of the oscillator with small capacitors by proposing a Miller current-starved inverter ring oscillator. For identical values of integrated components in implementation, the proposed ring oscillator reduces the oscillation frequency by 5 times over the conventional ring oscillator and 3 times over the conventional current-starved inverter ring oscillator. This benefits the relaxation of PSRR requirement and the reduction of substrate noise coupling in mixed-signal circuits. The second technique aims at enhancing the reliability of the programmed data by proposing orthogonal fusible link trimming circuit. The experimental results have verified that the programming range of 56 kHz to 1.042 MHz is achieved using discrete-step tuning on small capacitor values from 0.375 pF to 5.625 pF together with frequency division by four divider stages, whilst the jitter is less than 300 ps at ±10% variation in a 5 V supply in the entire tuning range. Wing Foon Lee was born in Singapore. He had worked as an application engineer for more than two years. He received his B.Eng., M.Eng. and Ph.D. degrees in Electrical & Electronic Engineering from Nanyang Technological University, Singapore in 1996, 1999 and 2005 respectively. His research interest is on low power analog circuit design, high precision readout circuits and signal-conditioning circuits for sensor applications. P. K. Chan was born in Hong Kong. He received the B.Sc. (Hons) degree from the University of Essex, Colchester, U.K., in 1987, the M.Sc. degree from the University of Manchester, Institute of Science and Technology (U.M.I.S.T.), Manchester, U.K., in 1988, and the PhD degree from the University of Plymouth, U.K. in 1992. From 1989 to 1992, he was a Research Assistant with the University of Plymouth, working in the area of MOS continuous-time filters. In 1993, he joined the Institute of Microelectronics (IME) as a Member Technical Staff, where he designed CMOS sensor interfaces for industrial applications. In 1996, He was a Staff Engineer with Motorola, Singapore where he developed the magnetic write channel for Motorola 1st generation hard-disk preamplifier. He joined Nanyang Technological University (NTU), Singapore in 1997, where he is currently an Associate Professor in the School of Electrical and Electronic Engineering and Program Director [analog/mixed-signal IC and applications] for the Center for Integrated Circuits and Systems (CICS). He holds four patents and is an IC Design Consultant to local and multi-national companies in Singapore. He has also conducted numerous IC design short courses to the industrial companies and design centers. His research interests include circuit theory, amplifier frequency compensation techniques, sensing interfaces for integrated sensors, biomedical circuits and systems, integrated filters and data converters.     

Optimization and Performance Analysis of Zero Forcing Decision Feedback Detector for MIMO Block-Fading Channels with Per-Antenna Power Control

In multiple-input multiple-output (MIMO) antenna systems, the zero forcing decision feedback detector (ZF-DFD) is used to recover transmit signals. In this paper, we propose a per-antenna power control (PAPC) scheme based on ZF-DFD for MIMO block-fading channels. The optimal power controlled ZF-DFD can minimize the block error rate (BLER) and maximize the lower bound of the channel’s free distance at high signal-to-noise ratio (SNR) region subject to a power constraint. Additionally, the optimal power controlled ZF-DFD can achieve this BLER performance without any ordering operation at the receiver. The performance analysis among the conventional ZF-DFD without feedback, the optimal power controlled ZF-DFD with power feedback, and the ZF-DFD with full channel state information feedback shows that the optimal ZF-DFD achieves a tradeoff between performance and feedback overhead. We compare the bit error rate (BER) and BLER performance of the optimal ZF-DFD with other detectors without power feedback by simulation. In simulations, the execution times required by these detectors are also reported to compare their complexity. It comes straight that the optimal power controlled ZF-DFD proposed in this paper can achieve good performance with small feedback overhead and have low complexity. Kun Zhao was born in Hefei, China, on 9 October 1979. He received his BS and MS degrees from University of Science and Technology of China (USTC), in 2001 and 2003, all in Electrical Engineering. He is now a Ph.D. candidate at USTC.His research interests are in the area of spread spectrum and CDMA communications, radio resource management in mobile communications, space-time signal processing and multiuser MIMO. Ling Qiu received her BS degree from Southeast University, P. R. China, in 1990. She also received MS and Ph.D. degrees from University of Science and Technology of China (USTC), in 1997 and 1999, all in Electrical Engineering.From 1990 to 1994, she was an engineer in the Institute of Nanjing Electronic Technology. In 1999, she joined the Department of Electronic and Engineering and Information Science, USTC as a lecturer. Since 2002, she has been an Associate Professor. She is a coauthor of two books and over 40 conference/journal papers. Her research interests are in the area of wireless communications, spread spectrum and CDMA communications, wireless access networks and protocols, radio resource management in mobile communications, space-time signal processing and multiuser MIMO. Jinkang Zhu is a professor of Department of Electronic Engineering & Information Science of University of Science and Technology of China (USTC). Now he is director of Personal Communication Network and Spread Spectrum Lab. of USTC, Chair of the Academic Committee of School of Information Science & Technology of USTC, Vice-Chiar of the Academic Committee of USTC.He was Permanent V-President of School of Information Science & Technology of USTC, Chairman of PCN Experts Group of Communication Project of National R & D on High-Technology Programme of China, Member of Information Technology Expert Group of the Chinese Academy of Sciences, Member (Representation of China Mainland) of Technical Forum on Wireless Communications of Asia Pacific Region, Member of Technical Advisory Committee of IEEE VTC'99 Fall, Member of Technical Program Committee of IEEE VTC'2000, Member of Technical Program Committee of SCI'2001.His research area is Wireless and Mobile Communications, CDMA and Spread Spectrum Communications, Signal Process of Communications, and Wireless Networks. He got two awards of Ministry of Science & Technology of China, three awards of Chinese Academy of Science. He published five books and 100 papers, where synchronous CDMA method proposed is used in TD-SCDMA Standard of 3G as basic technology.     

Reconfigurable Coprocessor for Multimedia Application Domain

A new reconfigurable architectural template is presented. Such a template is composed of coarse-grained and fine-grained reconfigurable datapath and control to obtain performances at custom designed chip level. To show the adaptability/performance of such architectural template, the architecture has been customized (i.e. datapath and control features of the template have been properly sized) for multimedia application domain. To evaluate complexity and maximum clock frequency of the proposed architecture, it has been synthesized using Synopsys Design Compiler on a standard-cell 0.18 μ m technology. Estimated number of transistors is 335 K, while maximum allowable frequency is 460 MHz. Performances have been evaluated comparing the number of clock cycles and the processing time required to process application domain dominant kernels with commercial devices: we obtained up to 95% reduction with respect to ARM and up to 94% reduction with respect to TMS320C5510 in terms of clock cycles. Salvatore M. Carta (1997 Electronic Eng. Master. 2002 Electronics and Computer Science PhD) joined the Department of Electrical and Electronics Engineering of the University of Cagliari, Italy in 1998 as PhD student. From 2005 he has been assistant professor in Department of Mathematics and Computer Science of the University of Cagliari. His research interests focus mainly on architectures, software and tools for embedded and portable computing, with particular emphasis on: languages, architectures and compilers for reconfigurable and parallel computing; Networks-on-chip; Operating systems for multiprocessor-systems-on-chip; low power real-time scheduling algorithms. Danilo Pani (2002 Electronic Eng. Master, 2006 Electronics and Computer Science PhD) joined the Department of Electrical and Electronics engineering of the University of Cagliari, Italy in 2002 as Electronics and Computer Science PhD student. His primary research interests are in the area of Digital Signal Processing architectures and systems, Biomedical Engineering, Reconfigurable Systems and Cooperative VLSI architectures for distributed computing. Luigi Raffo (1989 Master, 1994 Electronics and Computer Science PhD) joined Department of Electrical and Electronics Engineering of the University of Cagliari, Italy in 1994 as assistant professor. From 1998 he has been professor of Digital System Design, Integrated Systems Architectures and Microelectronics at the same Department. His research activity is mainly in the design of low-power analog and digital architectures/chips. He has been project manager of many local and international projects. He is author of more than 50 international papers in the field.     

A Broadband Quadrature-Modulator with Integrated Baluns

A broadband direct-conversion quadrature-modulator has been implemented in 0.8 m SiGe with integrated baluns in its RF-signal paths. Measured performance includes IRR-values at better than –40 dBc in 0.75–3.6 GHz with output power levels in excess of –20 dBm. For this performance circuit draws 46 mA from a single 2.5 V supply.Esa Tiiliharju was born in Rovaniemi, Finland, in 1966. He received the M.Sc. degree in Information Technology in 1995, and the Lic.Tech degree in electrical engineering in 1998, both from Helsinki University of Technology, Finland.From 1996 to July 1997 he was employed as assistant at Helsinki University of Technology. He has been holding a position of a research assistant from 1997, and he is currently working towards the Ph.D. degree in the Electronic Circuit Design Laboratory at Helsinki University of Technology.His research interests include the design of integrated low-power circuits for portable telecommunication applications. He has designed and measured several integrated circuits for this application area. He is author or co-author for several international refereed conference and journal publications on analog integrated circuits.Kari A.I. Halonen was born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from the Helsinki University of Technology (HUT) in 1982 and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, Heverlee, Belgium, in 1987.From 1982 to 1984, he was with HUT as an Assistant and with the Technical Research Center of Finland as a Research Assistant. From 1984 to 1987, he was a Research Assistant with the E.S.A.T. Laboratory, Katholieke Universiteit Leuven, with a temporary grant from the Academy of Finland. Since 1988, he has been with the Electronic Circuit Design Laboratory, HUT, as a Senior Assistant from 1988 to 1990, and as the Director of the Integrated Circuit Design Unit of the Microelectronics Center from 1990 to 1993. He was on leave of absence during the academic year 1992–1993, acting as Research and Development Manager with Fincitec Inc., Finland. From 1993 to 1996, he was an Associate Professor, and since 1997, he has been a full Professor with the Faculty of Electrical Engineering and Telecommunications, HUT. He became the Head of Electronic Circuit Design Laboratory year 1998. He was the Technical Program Committee Chairman for the European Solid-State Circuits Conference in 2000. He is the author or coauthor of over 150 international and national conference and journal publications on analog integrated circuits, and holds several patents on analog integrated circuits. His research interests are in CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications.Dr. Halonen was an Associate Editor of the IEEE Transactions on Circuits and Systems–Part I: Fundamental Theory and Applications from 1997 to 1999. He has been a Guest Editor for the IEEE Journal of Solid-State Circuits. He received the BeatriceWinner Award from the IEEE International Solid-State Circuits Conference in 2002.     

A 1 V switchable CMOS LNA for 802.11A/B WLAN applications

A new dual-band, 2.4 and 5.2 GHz, combined LNA, which can operate at 1 V supply only, for WLAN application is presented. The switched transistor technique is used in the LNA. It could match the input port in two frequency bands and reduce one on-chip spiral inductor usage compared with [1, 2]. Theoretical analysis and transistor level simulation results using 0.18 μm CMOS process from Chartered Semiconductor are presented to demonstrate this idea. Wang-Chi Cheng received his B.Eng., M.Phil., and Ph.D. degrees in Electronic Engineering of the Chinese University of Hong Kong (CUHK) in 1999, 2001 and 2004. His research achievements during M.Phil. and Ph.D. studies were in the field of low voltage receiver front-end circuits design with CMOS technology. He joined the Electrical and Electronic Engineering department of Nanyang Technological University (NTU), Singapore, in May 2005 as a Research Fellow. Now, he is a Senior Engineer in charge of the UWB transceiver IC design in Hong Kong Applied Science and Technology Research Institute (ASTRI). His current research interests include 802.11 A/B WLAN and UWB transceiver design. He is also a paper reviewer of the IEEE Microwave and Wireless Components Letters. Jian-Guo Ma received his B.Sc. and M.Sc. in 1982 and 1988 respectively with honors from Lanzhou university of Chain, and Doctoral Degree in Engineering from Gerhard-Mercator University of Germany in 1996. From Jan. 1982 to March 1991, he has worked with Lanzhou university of China on RF & Microwave Engineering. Before he joined Nanyang Technological University in 1997, he was with Technical University of Nova Scotia, Canada. Now, he is a Professor of the University of Electronic Science and Technology of China. His research interests are: RFIC designs for wireless applications; RF characterization and modeling of semiconductor devices; RF interconnects and packaging; SoC and Applications; EMC/EMI in RFICs. He has published more than 150 technical papers and two books in above mentioned areas. He holds 6 patents in CMOS RFICs. He is now Associate Editor for IEEE Microwave and Wireless Components Letters. Kiat-Seng Yeo received his B.E. (Hons.) (Elect) in 1993, and Ph.D. (Elect. Eng.) in 1996 both from Nanyang Technological University, Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore as a Lecturer in 1996, and became an Assistant Professor and an Associate Professor in 1999 and 2002, respectively. Professor Yeo provides consulting to statutory boards and multinational corporations in the areas of semiconductor devices and electronic circuit design. He has been extensively involved in the modeling and fabrication of small MOS/Bipolar integrated technologies for the last ten years. His research interests also include the design of new circuits and systems (based on scaled technologies) for low-voltage low-power applications; radio frequency integrated circuit (RF IC) design; integrated circuit design of BiCMOS/CMOS multiple-valued logic circuits, domino logic, and memories; and device characterization of deep submicrometer MOSFETs. Manh-Anh Do obtained his B.E. (Hons) (Elect.) in 1973, and Ph.D. (Elect. Eng.) in 1977 both from University of Canterbury, New Zealand. Between 1977 and 1989, he held various positions including: R & D engineer and production manager at Radio Engineering Ltd., research scientist at Fisheries Research Centre, New Zealand, and senior lecturer at National University of Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore as a senior lecturer in 1989, and obtained the Associate Professorship in 1996 and the Professorship in 2001. He has been a consultant for many projects in the Singapore electronic industry, and was the principal consultant for the design, testing and implementation of the $200 million Electronic Road Pricing (ERP) island-wide project in Singapore, from 1990 to 2001. His current research is on digital and mobile communications, RF IC design, mixed-signal circuits and intelligent transport systems. Before that, he specialsed in sonar designing, biomedical engineering and signal processing. Since 1995, he has been Head of Division of Circuits and Systems, School of EEE, NTU. He is a Fellow of IEE, UK, a Chartered Engineer (UK) and a Professional Engineer (Singapore).     

A 200 MHz 4.8 mW 3 V Fully Differential CMOS Sample-and-Hold Circuit with Low Hold Pedestal

Wide frequency bandwidth has been internationally allocated for unlicensed operation around the oxygen absorption frequency at 60 GHz. A power amplifier and a low noise amplifier are presented as building blocks for a T/R-unit at this frequency. The fabrication technology was a commercially available 0.15 m gallium arsenide (GaAs) process featuring pseudomorphic high electron mobility transistors (PHEMT). Using on-wafer tests, we measured a gain of 13.4 dB and a +17 dBm output compression point for the power amplifier at 60 GHz centre frequency when the MMIC was biased to 3 volts V_dd. At the same frequency, the low noise amplifier exhibited 24 dB of gain with a 3.5 dB noise figure. The AM/AM and AM/PM characteristics of the power amplifier chip were obtained from the large-signal S-parameter measurement data. Furthermore, the power amplifier was assembled in a split block package, which had a WR-15 waveguide interface in input and output. The measured results show a 12.5 dB small-signal gain and better than 8 dB return losses in input and output for the packaged power amplifier.Mikko Kärkkäinen received the M.Sc. degree in electrical engineering from the Helsinki University of Technology, Espoo, Finland, in 2000, and is currently working toward the Ph.D. degree at the Electronic Circuit Design Laboratory, Helsinki University of Technology. He is interested in millimetre wave circuit design.Mikko Varonen received the M.Sc. degree in electrical engineering from the Helsinki University of Technology, Espoo, Finland, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the Electronic Circuit Design Laboratory, Helsinki University of Technology. His research interests involve millimetre-wave integrated circuits.Pekka Kangaslahti received the M.Sc. and Ph.D. degrees in electrical engineering from the Helsinki University of Technology, Finland, in 1992 and 1999, respectively. Since 1999 he has been a visiting scientist at the NASA Jet Propulsion Laboratory, Pasadena, USA. His research interests include nonlinear microwave and millimetre wave monolithic circuits, especially for signal generation in telecommunication and radar applications.Kari A. I. Halonen was born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from Helsinki University of Technology, Finland, in 1982, and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, in Heverlee, Belgium, in 1987.From 1982 to 1984 he was employed as assistant at Helsinki University of Technology and as research assistant at the Technical Research Center of Finland. From 1984 to 1987 he was a research assistant at the E.S.A.T. Laboratory of the Katholieke Universiteit Leuven, enjoying also a temporary grant of the Academy of Finland. Since 1988 he has been with the Electronic Circuit Design Laboratory, Helsinki University of Technology, as senior assistant (1988–1990), and the director of the Integrated Circuit Design Unit of the Microelectronics Center (1990–1993). He was on leave of absence the academic year 1992–93, acting as R&D manager in Fincitec Inc., Finland. From 1993 to 1996 he has been an associate professor, and since 1997 a full professor at the Faculty of Electrical Engineering and Telecommunications, Helsinki University of Technology. He became the Head of Electronic Circuit Design Laboratory year 1998. From 1997 to 1999 he was an associate editor of IEEE Transactions on Circuits and Systems I. He has been a guest editor for IEEE Journal of Solid-State Circuits and the Technical Program Committee Chairman for European Solid-State Circuits Conference year 2000. He has been awarded the Beatrice Winner Award in ISSCC02 Conference year 2002.     

“互联网+”时代电路课程教学探索

电子科技大学自 2016 年以来,连续五个学期开展电路分析课程的 MOOC 教学,并基于 MOOC 平台进行了新型教学模式尝试。本文首先介绍了电子科技大学电路分析课程所采用的基于 MOOC 的多元教学模型;而后通过 MOOC 后台数据分析、讨论区数据词频分析等手段对该教学模式的不足进行了分析;最后针对现有教学模型的缺陷,提出一种基于多种互联网技术和资源的深层次多元教学模型。     

Accelerating Mobile Video: A 64-Bit SIMD Architecture for Handheld Applications

Providing quality mobile video applications in hand-held mobile devices requires increased computational capability. Using Single Instruction Multiple Data (SIMD) techniques to expose and accelerate the data parallelism inherent in video processing increases performance in handheld and wireless systems. The paper introduces a new 64-bit SIMD coprocessor of the Intel® XScale® microarchitecture which is optimized for low-power handheld applications. The architecture blends the SIMD media processing style with the capabilities of the XScale microarchitecture. This paper provides an overview of the architecture, its instruction set, programming model, the pipeline organization and functional units. The paper also describes how key features of architecture improve the performance of video applications as compared to a scalar implementation. The performance and power improvements based upon measured results are analyzed to show how the opportunities of power savings by reducing the frequency and voltage can be realized.Nigel C. Paver has 13 years experience with the ARM architecture, and in the Intel PCA Components group in Austin, Texas, he is responsible for the architecture and implementation of multimedia coprocessors for the Intel XScale micro-architecture. He is also involved in product architecture and definition of Intel PCA processors. Before Intel, Nigel was one of the lead designers of the early AMULET asynchronous ARM microprocessors at the University of Manchester. He was also vice president in a startup company which used asynchronous design techniques to produce a low-power asynchronous DSP core. Nigel holds a Master of Science degree and Ph.D. in computer science from the University of Manchester and a Bachelor of Science degree in electronics from UMIST.Moinul Khan is a multimedia product architect at Intel Corporation PCA Components group. He is responsible PCA graphics and security architecture. His research interests are virtual prototyping, signal processing algorithms and architecture and communications networking. Before joining Intel he was a technology specialist and founding member of a startup at ATDC, Georgia. He worked on his doctoral research at Georgia Center for Advanced Telecommunications Technology at Georgia Institute of Technology. He received his B.Tech form Indian Insti-ture of Technology and MSEE from Georgia Tech. He also worked as a research member for Canadian Institute for Telecommunications Research and Bell Communications Laboratories.Bradley C. Aldrich joined Intel in 1997 where he is currently an architect within the PCA Components Group. His current work includes the development of coprocessor instruction support in addition to image capture and display technologies for XScale based application processors. He was previously a member of the Intel/Analog Devices joint development architecture team responsible for video enhancements for the Micro Signal Architecture. Prior to that he was a video system architect in Intel’s Digital Imaging and Video Division working on CMOS sensors, still cameras, and tethered PC based video peripherals. He has also worked as a device engineer for Motorola and as a test engineer for Tektronix. He received a BSEE in 1988 and MSEE in 1994 from the University of Texas at San Antonio.Christopher D. Emmons received a Bachelor of Science degree in Computer Science from the University of Texas at Austin in 2003. He joined Intel in 2001 and is currently a multimedia architect responsible for algorithm development and performance optimization for handheld products within the PCA Components Group. Prior to this he worked as an applications engineer providing performance and power analysis in support of product marketing groups. His research interests include video compression, operating system design, and dynamic resource management.     

Researches on Reconfigurable Antenna in CEMLAB at UESTC

This paper summarizes the achievement and progress in the research on reconfigurable antenna since 2001, in Computational Electromagnetics Laboratory （CEMLAB） at University of Electronic Science and Technology of China （UESTC）. Several typical reconfigurable antennas are introduced, which can realize frequency, pattern or frequency-pattern reconfigurability by electrically controlling methods. Some techniques involved in the design and analysis of reconfigurable antennas are reported. At last, the development trend of reconfigurable antenna is predicted in the conclusions.     

Legitimate Skew Clock Routing with Buffer Insertion

In this paper, we propose a new quick and effective legitimate skew clock routing with buffer insertion algorithm. We analyze the optimal buffer position in the clock path, and conclude the sufficient condition and heuristic condition for buffer insertion in clock net. During the routing process, this algorithm integrates buffer insertion and node merging together, and performs them in parallel. Compared with the method of buffer insertion after zero skew clock routing, our method improves the maximal clock delay by at least 48%. Compared with legitimate skew clock routing algorithm with no buffer, this algorithm further decreases the total wire length and gets reductions from 42 to 82% in maximal clock delay. The experimental results show that our algorithm is quick and effective. Xinjie Wei received his B.Sc. degree in Computer Science from the PLA Nanjing Institute of Communications Engineering in 1993, and got M.S. degree in Computer Science from Xidian University in 1998. He is currently pursuing the Ph.D. degree at Tsinghua University. His research interests include computer network security, neural network and design automation for VLSI circuits and systems. And the major research attention is focused on VLSI physical design. Yici Cai received BSc degree in Electronic Engineering from Tsinghua University in 1983 and received in and MS degree in Computer Science & Technology from Tsinghua University in 1986, She has been an associate professor in the Department of Computer Science & Technology, Tsinghua University. Beijing, China. Her research interests include VLSI layout theory and algorithms. Meng Zhao has been an researcher in Semiconductor Industry Association of Beijing. She received her Bachelor of Engineering degree in Electronical Engineering from Tsinghua University, China, in 2000. She received her Master of Science degree in Computer Science from Tsinghua University, China, in 2003. Her research interests include VLSI design and CAD, Electronical material and device, VLSI verification and so on. Xianlong Hong graduated from Tsinghua University, Beijing, China in 1964. Since 1988, he has been a professor in the Department of Computer Science Technology, Tsinghua University. His research interests include VLSI layout algorithms and DA systems. He is the fellow of IEEE and the Senior Member of Chinese Institute of Electronics.