A 24-GHz Transmitter With On-Chip Dipole Antenna in 0.13-$mu$m CMOS

A fully integrated dual-conversion transmitter chain with an on-chip dipole antenna and an integer-N synthesizer operating in the 24-GHz Instrument, Scientific and Medical (ISM) band was fabricated in 0.13-mum CMOS. The choice of 24-GHz operation enables the integration of a 4-mm long antenna on chip. The transmitter chain can support data rate of 100 Mb/s. It provides 6-dBm output power to a 100-Omega load at 22.4 GHz with 152-mW power dissipation including that of a frequency synthesizer. At this output power level, the dual conversion architecture can mitigate the VCO pulling even when an antenna and a power amplifier are integrated on the same substrate as the VCO. The out-of-band emissions due to the modulation side lobes and image have been sufficiently suppressed. The stray emissions of local oscillator can also be reduced using circuit techniques. The signal from the transmitter has been picked up 95 meters away with a horn antenna, which suggests that wireless communications between a single chip radio and a base station 100 meters away is possible.     

A 1.2-GHz Comparator With Adaptable Offset in 0.35- $mu$m CMOS

We apply the technique of floating-gate differential injection to a 1.2-GHz CMOS comparator to achieve arbitrary, accurate, and adaptable offsets. The comparator uses nonvolatile charge storage on floating-gate nodes for either offset nulling or automatic programming of a desired offset. We utilize impact-ionized pFET hot-electron injection to achieve fully automatic offset programming. The design has been fabricated in a commercially available 4-metal, 2-poly 0.35-$mu$m CMOS process. Experimental results confirm the ability to reduce the variance of comparator offset by 3600$times$ and to accurately program a desired offset with maximum observed residual offset of 469 $mu$V and standard deviation of 199 $mu$ V. We achieve controlled injection to accurately program the input offset to voltages uniformly distributed from ${-}1$ to 1 V. The comparator operates at 1.2 GHz with a power consumption of 3.3 mW.      

A Low Voltage 0.35$mu$m CMOS FrequencyDivider With the Body Injection Technique

This letter proposes a new CMOS injection locked frequency divider (ILFD) fabricated in a 0.35 mum CMOS process. The ILFD circuit is realized with a cross-coupled CMOS LC-tank oscillator, and the injecticon is carried out through the bodies of cross- coupled transistors. The self-oscillating ILFD is injection-locked by second-(third-) harmonic input to obtain the division order of two (three). Measurement results show that at the supply voltage of 1.5 V and at the incident power of 10 dBm, the locking range is from the incident frequency 6.94 to 8.41 GHz in the divide-by-3 mode and the operation range is from the incident frequency 4.56 to 5.59 GHz in the divide-by-2 mode.     

A 40-Gb/s Transimpedance Amplifier in 0.18-$mu$m CMOS Technology

A 40-Gb/s transimpedance amplifier (TIA) is realized in 0.18-mum CMOS technology. From the measured S-parameters, a transimpedance gain of 51 dBOmega and a 3-dB bandwidth up to 30.5 GHz were observed. A bandwidth enhancement technique, pi-type inductor peaking (PIP), is proposed to achieve a bandwidth enhancement ratio (BWER) of 3.31. In addition, the PIP topology used at the input stage decreases the noise current as the operation frequency increases. Under a 1.8 V supply voltage, the TIA consumes 60.1 mW with a chip area of 1.17 X 0.46 mm2. The proposed CMOS TIA presents a gain-bandwidth product per DC power figure of merit (GBP/P_de) of 180.1 GHzOmega/mW.     

Low-Threshold 1.3-$mu$m GaInNAs Quantum-Well Lasers Using Quaternary-Barrier Structures

GaInNAs quaternary-barrier structures, where indium is incorporated to achieve the lattice-matched condition, have been employed for 1.3-m GaInNAs-GaAs single- (SQW) and triple-quantum-well (TQW) lasers. Compared to a GaNAs ternary-barrier structure, photoluminescence results from the quaternary-barrier sample show improved optical properties. Threshold current densities have been achieved with the lowest values of 150 and 529 A/cm² for GaInNAs SQW and TQW lasers at room temperature, respectively.     

A 2.4-GHz Resistive Feedback LNA in 0.13-$mu$m CMOS

A $g_{m}$-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of $g_{m}$ -boosting as in inductively degenerated topology. The gain of the LNA increases by the $Q$ -factor of the series RLC input network, and its noise figure (NF) is reduced by a similar factor. By exploiting the $g_{m}$-boosting property, the proposed fully integrated LNA achieves a noise figure of 2.0 dB, S21 of 24 dB, and IIP3 of ${- 11}~ hbox{dBm}$ while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 ${hbox {mm}}^{2}$ in 0.13-$mu{hbox {m}}$ CMOS, which provides the best figure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB.      

Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18-$mu$m CMOS

This paper presents the design and experimental evaluation of a new type of irreversible energy recovery logic (ERL) families called complementary energy path adiabatic logic (CEPAL). It inherits the advantages of quasi-static ERL (QSERL) family, but is with improved driving ability and circuit robustness. The proposed logic style features no hold phase compared to its QSERL counterpart under the same operation conditions; thereupon no feedback keeper is required so that considerable improvements in area and power overheads can be achieved. Moreover, its throughput becomes twice as high as that of QSERL when their frequencies of power clocks (PCs) are identical. Results on the impact of variation on CEPAL are provided. Comparison between CEPAL and other known low-power logic style achieving iso-performance, namely, subthreshold logic is also given. In order to demonstrate workability of the newly developed circuit, an 8-bit shift register, designed in the proposed techniques, has been fabricated in a TSMC 0.18- $mu$m CMOS process. Both simulation and measurement results verify the functionality of such a logic, making it suitable for implementing energy-aware and performance-efficient very-large scale integration (VLSI) circuitry.      

Optical Absorption Glucose Measurements Using 2.3-$mu$m Vertical-Cavity Semiconductor Lasers

Continuous glucose monitoring has been shown to help diabetes mellitus patients stabilize their glucose levels, leading to improved patient health. One promising technique for monitoring blood glucose concentration is to use optical absorption spectroscopy. This letter proposes the use of thermally tunable 2.3-mum vertical-cavity surface-emitting lasers to obtain blood absorption spectra. The partial least squares technique is used to determine the glucose concentration from the spectra obtained in aqueous glucose solutions.     

3-GHz Silicon Photodiodes Integrated in a 0.18-$mu$m CMOS Technology

A new PIN photodiode (PD) structure with deep n-well (DNW) fabricated in an epitaxial substrate complementary metal–oxide–semiconductor (epi-CMOS) process is presented. The DNW buried inside the epitaxial layer intensifies the electric field deep inside the epi-layer significantly, and helps the electrons generated inside the epi-layer to drift faster to the cathode. Therefore, this new structure reduces the carrier transit time and enhances the PD bandwidth. A PD with an area of $70times 70 mu$m $^{2}$ fabricated in a 0.18- $mu$m epi-CMOS achieves 3-dB bandwidth of 3.1 GHz in the small signal and 2.6 GHz in the large signal, both with a 15-V bias voltage and 850-nm optical illumination. The responsivity is measured 0.14 A/W, corresponding to a quantum efficiency of 20%, at low bias. The responsivity increases to 0.4 A/W or 58% quantum efficiency at 16.2-V bias in the avalanche mode.      

A 25–75 GHz Miniature Double Balanced Frequency Doubler in 0.18-$mu$m CMOS Technology

A 25-75 GHz compact double balanced frequency doubler fabricated in standard 0.18-mum CMOS process is demonstrated. The resistive doubler is composed of two identical asymmetric broadside-coupled baluns, and a quad GS-connected diode. The fabricated doubler achieves a radio frequency bandwidth from 25 to 75 GHz with a maximum output power better than +3 dBm; the fundamental signal rejection is ranging from 32 to 59 dB, and only occupies a chip size of 0.24 mm². To the knowledge of the authors, this double balanced frequency doubler is the first demonstration with an operating frequency up to 75 GHz in 0.18-mum CMOS technology and shows this silicon-based frequency doubler can compare with its GaAs counterpart.     

A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized $G_m$–$C$ Biquad in 0.13-$mu$ m CMOS

Fully reconfigurable transceivers are required to answer the low-power high flexibility demand of future mobile applications. This paper presents a fully reconfigurable G_m-C biquadratic low-pass filter which offers a large range of both frequency and performance flexibility. First, a design approach is proposed focusing on linearity properties by extending Volterra analysis from circuit to architectural level in order to optimize the filters performance. Secondly, a novel switching technique is discussed that allows a bandwidth tuning over more than two orders of magnitude starting from 100 kHz up to 20 MHz and which uses only gate transistor capacitance. Fundamental to this technique is that the power consumption can be traded with the desired performance. Furthermore, the quality factor, noise level and linearity are all programmable over a very wide range. The biquad is processed in a 0.13-mum CMOS technology and operates at different supply voltages down to less than 0.8 V. For a 1.2-V supply, the filter consumes between 103 muA (100 kHz) and 11.85 mA (20 MHz) for a low noise setting around 25 to 35 muVrms integrated over the filter bandwidth achieving an third-order intermodulation intercept point of 10 dBVp.     

High-Performance 1.55-$mu$ m Superluminescent Diode With Butt-Coupled Spot-Size Converter

We report the design and fabrication of a novel 1.55-m spot-size converter superluminescent diode (SLD) for optical access networks. The active section of SLD was fabricated by using a planar buried heterostructure to adopt the double-waveguide-core structure for low-threshold and high-output power operation at a low injection current. A ridge-based passive waveguide was employed for an efficient coupling to a planar lightwave circuit. The threshold current was as low as 14 mA, and the maximum output power was as high as 28 mW with ripple less than 3 dB at an injection current of 200 mA.     

Optical Injection-Induced Polarization Switching Dynamics in 1.5-$mu$m Wavelength Single-Mode Vertical-Cavity Surface-Emitting Lasers

We report the first experimental invetigation of the polarization-mode switching dynamics and injection-wavelength-dependent polarization-mode bistability of a 1.5-m wavelength single-mode vertical-cavity surface-emitting lasers (VCSELs) under external laser beam injection. An injection beam with polarization orthogonal to that of the stand-alone VCSEL caused polarization-mode instability and switching of the VCSEL output. By varying the optical injection detuning for fixed injection power observation was made of a novel form of polarization bistability which will have applications in a new type of all-optical flip-flop and signal processing scheme.     

1.3-$mu$m Amplifier-Free All-Optical 2R Regenerator Using Two-Mode Injection-Locked Distributed Feedback Laser Diode

This study presents a novel and cost-effective 1.3-mum all-optical 2R regenerator based on a two-mode injection-locked distributed feedback laser diode. The proposed 2R regenerator, with 14.13-dB small signal gain, has achieved an amplifier-free 10-Gb/s straight line transmission over 60 km while keeping the power penalty less than 0.84 dB at bit-error rate (BER) =10^-9. In addition, properties like BER degradation, output extinction ratio, gain, and data-rate transparency are also experimentally investigated     

Silicon Photonic Nanowire Soliton-Effect Compressor at 1.5 $mu$m

Soliton-effect compression of femtosecond optical pulses in a silicon photonic nanowire at 1.5 mum is numerically investigated. A region of anomalous group velocity dispersion, small third-order dispersion, and large nonlinearity of silicon is used to show compression of 30-fs input pulses to 1 fs. Large nonlinearity of silicon allows for compression of input pulses with subnanojoule energies.     

Fabrication and Performance of 0.25-$mu$m Gate Length Depletion-Mode GaAs-Channel MOSFETs With Self-Aligned InAlP Native Oxide Gate Dielectric

The fabrication and performance of 0.25- mum gate length GaAs-channel MOSFETs using the wet thermal native oxide of InAlP as the gate dielectric are reported. A fabrication process that self-aligns the gate oxidation to the gate recess and metallization to reduce the source access resistance is demonstrated for the first time. The fabricated devices exhibit a peak extrinsic transconductance of 144 mS/mm, an on-resistance of 3.46 Omega-mm, and a threshold voltage of -1.8 V for typical 0.25 -mum gate devices. A record cutoff frequency of 31 GHz for a GaAs-channel MOSFET and a maximum frequency of oscillation f_max of 47 GHz have also been measured.     

Design and Properties of Phototransistor Photodetector in Standard 0.35- $mu$m SiGe BiCMOS Technology

In this paper, without altering any step of the commercial 0.35-mum SiGe BiCMOS process, a novel photodetector named phototransistor photodetector (PTPD) has been realized and demonstrated. The PTPD shows high photoresponsivity and its structure relaxes the tradeoff between sensitivity and speed. Responsivities of 9.5 A/W for 670 nm light and of 5.2 A/W for 850 nm light were achieved. The operation details of the PTPD are introduced in this paper. The device can be readily integrated with other on-chip circuits to form a high-performance optoelectronic IC. The low cost, the high performance, and the flexibility in optical-electrical design allow the SiGe PTPD to be used in many demanding applications.     

Fully Integrated Single Photon Avalanche Diode Detector in Standard CMOS 0.18- $mu$m Technology

Avalanche photodiodes (APDs) operating in Geiger mode can detect weak optical signals at high speed. The implementation of APD systems in a CMOS technology makes it possible to integrate the photodetector and its peripheral circuits on the same chip. In this paper, we have fabricated APDs of different sizes and their driving circuits in a commercial 0.18-mum CMOS technology. The APDs are theoretically analyzed, measured, and the results are interpreted. Excellent breakdown performance is measured for the 10 and 20 m APDs at 10.2 V. The APD system is compared to the previous implementations in standard CMOS. Our APD has a 5.5% peak probability of detection of a photon at an excess bias of 2 V, and a 30 ns dead time, which is better than the previously reported results.     

High-Q Slow-Wave Coplanar Transmission Lines on 0.35 $mu$m CMOS Process

In this letter, experimental results and trends for shielded coplanar waveguide transmission lines (S-CPW) implemented in a 0.35 $mu$m CMOS technology are provided. Because of the introduction of floating strips below the CPW transmission line, high effective dielectric permittivity and quality factor are obtained. Three different geometries of S-CPW transmission lines are characterized. For the best geometry, the measured effective dielectric permittivity reaches 48, leading to a very high slow-wave factor and high miniaturization. In addition, measurements demonstrate a quality factor ranging from 20 to 40 between 10 and 40 GHz, demonstrating state-of-the-art results for transmission lines realized in a low-cost CMOS standard technology.      

A 0.6 V, 4.32 mW, 68 GHz Low Phase-Noise VCO With Intrinsic-Tuned Technique in 0.13 $mu$m CMOS

An intrinsic-tuned, 68 GHz voltage controlled oscillator (VCO) without an extra on-chip accumulation-mode metal oxide semiconductor (MOS)-varactor is demonstrated in a standard, 0.13 mum CMOS technology. This VCO exhibits phase noises of -98.4 dBc/Hz and -115.2 dBc/Hz at 1 and 10 MHz offset, respectively, along with a tuning range of 4.5 % even under a small power consumption of 4.32 mW. Besides, the highest figure-of-merit (taking frequency tuning range into account) of -182 dBc/Hz under the 1 MHz offset condition is achieved among all previously reported >60 GHz CMOS-based VCOs, which is attributed to the proposed intrinsic tuning mechanism.