Ku-Band Power Amplifier MMIC Chipset with On-Chip Active Gate Bias Circuit

We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 μm GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.     

一种基于自适应偏置的2.4 GHz CMOS功率放大器

提出了一种单端自适应偏置电路,该电路能够根据输入信号功率,动态地调整输出直流电压,以提升射频功率放大器(PA)的线性度及功率回退区域的效率。为验证该电路的功能,设计了一种2.4 GHz PA,该电路基于单端三级结构设计,采用0.18 μm CMOS工艺制造,电路输入及输出阻抗匹配网络均集成于片内。测试结果表明,PA的增益为26.8 dB,S11和S22均小于-10 dB,OP1 dB为23.5 dBm,功率回退6 dB点PAE和峰值PAE分别为14%和24%。该PA对WLAN、ZigBee等2.4 GHz设备具有一定的应用价值。     

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.     

一种偏置电流可调节的高效率2.4GHz锗硅功率放大器

基于IBM0.35μm SiGe BiCMOS工艺BiCMOS5PAe实现了一种偏置电流可调节的高效率2.4GHz锗硅功率放大器。该功率放大器采用两级单端结构和一种新型偏置电路,除射频扼流电感外,其它元件均片内集成。采用的新型偏置电路用于调节功率放大器的静态偏置电流,使功率放大器工作在高功率模式状态或低功率模式状态。在3.5V电源条件下,功率放大器在低功率模式下工作时,与工作在高功率模式下相比,其功率附加效率在输出0dBm时提高了56.7%,在输出20dBm时提高了19.2%。芯片的尺寸为1.32mm×1.37mm。     

一种带功率检测和自适应偏置的CDMA功率放大器

设计了一款包含功率检测和自适应线性化偏置电路的CDMA功率放大器,功率检测器能根据输入信号的大小来调整功率管的偏置点,大幅提升低功率输出时的效率,从而提升系统整体效率;自适应线性化偏置能有效抑制功率放大器的增益压缩和相位失真,改善其线性度.采用2 μm InGaP/GaAs HBT晶体管工艺成功流片,测试结果表明,与普...     

A Low Voltage and Low Power Current-Mode Analog Computational Circuit

A new current-mode analog computational circuit is presented. The circuit can be digitally controlled to produce multiplying, squaring and inverse functions. The design is based on using MOSFETs operating in sub-threshold region to achieve ultra low power dissipation. The circuit is operated from a ±0.75 V DC supply. The proposed circuit has been simulated using Tanner in 0.35-μm TSMC CMOS process. Simulation results confirm the functionality of the circuit. The total power consumption is 2.3 μW, total harmonic distortion is 1.1 %, maximum linearity error is 0.3 % and the bandwidth is 2.3 MHz.     

一款用于5G功率放大器的分段线性温度补偿偏置电路

实现了一款用于功率放大器的具有温度补偿特性的偏置电路,首先通过正温度系数(PTAT)电流与负温度系数(NTAT)电流对功率放大器所需的偏置电流进行线性温度补偿,然后在线性补偿的基础上引入分段设计,实现分段线性温度补偿,保证全温范围内功率放大器增益线性化。同时通过分段电流舵型DAC灵活调整偏置电流的大小,将功率放大器偏置在合适工作点的同时降低开关噪声。该偏置电路采用Jazz 0.18μm SOI工艺实现。测试结果表明:在-30～30℃温度区间内,电流补偿斜率为14.9%;在30～90℃温度区间内,电流补偿斜率为29.6%,电流斜率的精度均在1.5%以内;室温下偏置电流的线性调整率为1.4%,输出偏置电流在20.2～1 022.0μA范围内可调。采用该偏置电路的一款功率放大器输出功率典型值为28 dBm,误差矢量幅度(EVM)在-30～90℃温度区间内小于3%。     

The Doherty Power Amplifier With On-Chip Dynamic Bias Control Circuit for Handset Application

A monolithic-microwave integrated-circuit Doherty power amplifier (PA) with an on-chip dynamic bias control circuit for cellular handset application has been designed and implemented. To improve the linearity and efficiency in the operation power ranges, the base and collector biases of the amplifiers, except the drive amplifier of the main path, are controlled according to the average output power. The base biases are controlled using the on-chip circuit and collector biases by the dc/dc chip to reduce the average dc consumption power. The power-added efficiency (PAE) is improved approximately 6% by the base dynamic bias control, and approximately 14% by the collector/base dynamic control from the class AB at Pout=16 dBm, respectively. If the dc/dc converter efficiency is 100%, the PAE could be improved approximately 17.5% from class AB, reaching to 29.2% at Pout=16 dBm. In the intermediate power level from 22 to 28 dBm, the PAE is over 34.3%. The average current consumption of the PA with the dynamic bias control is 22.5 mA in urban and 37.3 mA in suburban code-division multiple-access environments, which are reduced by 36%-46.7%, compared to the normal operation. The adjacent channel power ratio is below 47.5 dBc, and the PAE at the maximum power is approximately 43.3% in the dynamic bias operations     

一种低功耗CMOS可编程模拟延时电路

提出了一种基于65 nm CMOS工艺的5位可编程模拟延时电路。采用1.2 V的电源电压和0.01 V的步进控制电压来实现方波输入信号的延时控制。利用Cadence软件对该延时电路进行了性能分析。仿真结果表明,在典型低阈值工艺角下,该延时电路利用5位延时控制信号达到了0.34 ns/LSB的最高延时分辨率和41.47 ns的最长输出延时,实现了对1 kHz~1 MHz范围的数字方波信号的有效延时控制。该延时电路适用于低频数据采集、数据存储等系统。     

一种新颖的E类功放功率控制电路

基于0.18μm CMOS工艺,采用间接闭环控制方式,设计出一个适用于Class 1蓝牙E类功率放大器的低成本、高集成度输出功率控制电路.输出级电源电压采用类似LDO的结构控制.提出了一种新颖的一阶线性偏置电压结构,实现对输出级偏置电压的控制,极大地改善了功放的功率增益相对于控制电压的线性度,提高了PAE,最终实现了对输出功率2 dBm的步进控制.后仿真结果表明,输出功率控制精度较高,并具有较好的温度特性.     

用于功率放大器的随温度可调负压偏置电路

设计了一种应用于GaN功率放大器栅极调制的随温度可调负压偏置电路。电路由电压基准模块、温度传感器模块、比较器阵列以及误差放大器及其对应的功率管与反馈电阻等组成,通过基准电压与温度传感器输出电压的比较,输出数字控制信号到反馈电阻中的可变电阻模块,改变可变电阻阻值进而改变电路输出电压,实现芯片电压随温度可调。电路结构简单、易于实现、应用方便,同时电路中引入了修调电阻结构,极大提高了基准输出精度。电路芯片面积为1.10 mm×0.64 mm,采用0.5μm CMOS工艺进行了流片并完成了后期测试验证。结果表明,芯片可实现输出电压的随温度可调,有效解决了GaN功率放大器在相同的栅极偏置电压下输出功率随温度升高而减小的问题。     

数字功放的印制线路板设计

本文介绍了以LM4651L/LM4652数字功放为例的PCB设计原则和技术规范,对电路设计中的抗干扰性给出了具体的方案和措施,分析了布线中的电磁干扰问题,并找到了有效的对策.电路设计工程师在电路设计之初运用这些原则和方法能很好地解决布线中出现的问题.     

一种用于5G通信的高稳定双模功率放大器

采用国产40 nm CMOS工艺,设计了一种用于5G通信的28 GHz双模功率放大器。功率级采用大尺寸晶体管,获得了高饱和输出功率。采用无中心抽头变压器,消除了大尺寸晶体管带来的共模振荡问题。在共源共栅结构的共栅管栅端加入大电阻,提高了共源共栅结构的高频稳定性。采用共栅短接技术,解决了大电阻引起的差模增益恶化问题。在级间匹配网络中采用变容管调节,实现了双模式工作,分别获得了高功率增益和高带宽。电路后仿真结果表明,在高增益模式下,该双模功率放大器获得了20.8 dBm的饱和输出功率、24.5%的功率附加效率和28.1 dB的功率增益。在高带宽模式下,获得了20.6 dBm的饱和输出功率、22.6%的功率附加效率和12.2 GHz的3 dB带宽。     

一种模数转换器的采样保持/增益减法电路设计

文章介绍了一种适用于算法型流水线模数转换器（Pipeline ADC）的CMOS全差分采样保持／减法增益电路的设计。该电路的工作电压为3V，在70MHz的采样频率下可达到10位以上的精度：调节型共源共栅运算放大器可在不增加更多的级联器件的情况下就可以获得很高的增益及很大的输出阻抗：专为算法型模数转换器设计的采样保持／增益减法电路通过时序控制可实现校准状态和正常转换状态的转换：通过底极板采样技术和虚拟器件有效地消除了电荷注入及时钟馈通。最后用HSPICE仿真，证明其适用于10bit及以上精度的算法型流水线模数转换器。     

一种交叉耦合低功耗传输门绝热逻辑电路

提出了一种新的能量恢复型电路—— Transmission Gate Adiabatic Logic(TGAL)。该电路由交叉耦合的 CMOS传输门完成逻辑运算与能量恢复 ,对负载的驱动为全绝热过程。TGAL电路输出端始终处于箝位状态 ,在整个输出期不存在悬空现象并具有良好的信号传输效果。分析了 TGAL反相器的能耗 ,并与静态 CMOS电路及部分文献中绝热电路进行了比较。使用 TGAL构成门电路与时序系统的实例被演示。应用 MOSIS的0 .2 5 μm CMOS工艺参数的模拟结果表明 ,与传统 CMOS和 2 N-2 N2 P绝热电路相比 ,TGAL电路在 1 0 0 MHz工作频率时分别节省 80 %与 60 %以上的功耗。     

一种带失真抵消的高增益低噪声放大器

提出了一种用于GPS/BD双频接收机的带失真抵消的低噪声放大器。采用部分源级电感简并结构,相较于传统全部源级简并结构,以极低代价提高了增益。通过噪声特性的理论分析,优化了噪声系数,给出了相应的参数公式。通过增加失真抵消结构,提高了电路的线性度。采用TSMC 0.18 μm CMOS工艺进行设计。仿真结果表明,该放大器的增益达18 dB,噪声系数为1.7 dB,输入3阶交调截点为-1.4 dBm。在电源电压为1.8 V时,消耗电流为4.7 mA。相比传统结构,该放大器的增益提高了2 dB,线性度提高了6 dBm,功耗提高了15%。     

开关电源数模混合测控系统硬件电路设计与实验

采用UCC3895芯片与单片机相结合的方案设计了直流开关电源数模混合测控系统。闭环系统包括电压环与限流环,电压环使输出稳定在设定值上,限流环解决了负载突变问题,调节器和保护电路的设计使系统稳定且安全运行,单片机完成了系统故障的实时监测、显示与保护。最后研制了一套输出为270V的直流开关电源测控系统,实验结果良好。本文网络版地址：http：//www.eepw.com.cn/article/170164.htm     

CMOS音频功率放大器的旁路电压控制电路

基于CSMC0．5umCMOS工艺设计一种带滞回功能的高稳定性电压控制电路,利用迟滞比较器对旁路电压和基准电压进行比较并控制电容的充放电,提高了电压的稳定性。Cadence Spectre仿真结果表明,该电路产生的电压稳定性高,功耗低,且其滞回功能能有效抑制噪声。与普通的旁路电压控制电路相比,具有更高的稳定性和抗噪声能力,可广泛用于各种功率放大器内部。     

Gate Array Versus Standard Cell Realization of an Analog/Digital μC Interface Circuit

An interface circuit containing analog and digital functions was realized in gate array and standard cell design techniques. Realization on gate arrays became possible by using circuit tricks which can also be applied to the standard cell version. Based on this example various aspects of the two design styles are compared. For such designs it is most important to have CAD tools which give sufficient support to the designer, and which do not restrict him into a fixed set of macro cells.     

A High-Efficient CMOS RF Power Amplifier With Automatic Adaptive Bias Control

A 2.4-GHz Doherty power amplifier (PA) is developed in 0.18-mum CMOS technology. An automatic adaptive bias control circuit is integrated with the auxiliary PA to improve the overall performance of the PA. Operated at 3V, the P_{1 dB} and associated power-added-efficiency (PAE) of the PA are 21dBm and 33%, respectively. At the output power 6-dB backoff from P_{1 dB}, the PAE remains 21%. The limited PAE degradation at backoff power levels makes the PA suitable for the applications with high peak-to-average power ratio