以太网物理层中判决反馈均衡器VLSI优化设计

对以太网物理层中的判决反馈均衡器进行了VLSI优化设计,从硬件实现角度提出了两点改进措施,一是采用混合结构实现,二是系数调整单元复用。在0.18μm CMOS工艺下,改进后的判决反馈均衡器相比转置结构实现的判决反馈均衡器,速度提高16%,面积减少36%,功耗降低了39%。     

均衡器的新行业标准--TC Electronic EQ Station

EQ Station是TC Electronic继屡获大奖的1128和6032均衡器之后，在均衡器领域的又一力作。高尖端的48bit DSP处理技术，高品质的AD／DA转换技术和多机联网工作以太网技术，使得EQ Station成为现场扩声领域的新一代数字均衡解决方案。     

光以太网传输速率达到了100Gbps

Lucent Technologies公司宣布：他们采用光技术首次实现了100Gbps的以太网传输速率。该公司的一个研究小组提供了107Gbps的光数据流,这代表了100Gbps的数据传输速率和用于纠错的7％开销。该技术采用双二进制信令和单芯片光均衡器。双二进制信令采用正、负和零信号电平来表示用     

基于MCU与FPAA的均衡器系统硬件设计与测试

基于开关电容技术的FPAA(现场可编程模拟阵列)技术已取得了进一步提高,一些成熟的FPAA芯片相继推出.文中尝试使用FPAA芯片(AN221E04)实现一个全新概念的调节简便、成本低的音频均衡器设计.基于FPAA技术的巴特沃兹开关电容滤波器来实现音频均衡器滤波系统,并利用多个AN221E04芯片构建FPAA,与89S51 MCU(微控制器)及Serial EEPROM构建一个音效调节参数实时静态和动态可调的音频均衡器.     

小生境进化RBF网络在信道均衡中的应用

基于RBF网络的信道均衡器,其性能取决于神经网络的隐层参数.文中采用判决反馈均衡器的结构,RBF网络隐层的结构和参数则由基于小生境技术的混合递阶遗传算法来确定.仿真结果表明,这种RBF网络均衡器性能优良.     

一种用于无线信道的逐幸存处理均衡器

提出了一种适用于无线时变信道的逐幸存处理均衡器。通过训练序列得到信道参数的初始估计值,此后在Viterbi算法进行网格搜索的过程中,使得每一条幸存路径维持各自的信道参数,并在确定幸存分支后利用历史幸存序列对信道参数值进行更新,实现了信道参数的无时延估计。仿真结果表明,在无线时变信道环境下,逐幸存处理均衡器的性能明显优于其他传统均衡器。     

宽带均衡器的研制

宽带均衡器是重要的微波器件之一,介绍了宽带均衡器的工作原理,阐述了宽带均衡器的技术实现及工艺、调试等。     

一类可变参数数字均衡器的设计

对一阶、二阶可变参数数字均衡器的设计进行了研究,给出了数字均衡器的数学模型,得出了数字均衡器的频响特性曲线,分析了参数变化对数字均衡器频响的影响,并进行了实例分析。结果表明,对音乐信号处理,按照频响要求设定好均衡器的可变参数,就可很方便地设计出满足要求的数字均衡器,达到改善音质的目的。     

应用粒子滤波器实现混沌通信系统的盲信道均衡

粒子滤波器(Particle filter,PF)是一种结合重要性权重抽样的序贯蒙特卡罗方法,能够应用到任意状态空间模型,并且能较好地估计经过非线性变化后的随机变量的统计特性.本文应用粒子滤波器和信号建模技术研究混沌通信系统的盲信道均衡问题,发展基于混沌的通信系统的盲均衡技术.仿真结果证实了,当Logistic映射作为混沌发生器和通信场景为固定参数与时变衰落信道时,该盲信道均衡器与基于扩展卡尔曼滤波算法的盲均衡器和基于无先导变换的自适应盲均衡器相比,有较好的均衡实现.此外,利用本文的盲均衡算法,实现了一种混沌调制通信系统的解调.     

基于混合遗传算法及最低误码率准则的几何特征均衡器

针对高效调制通信系统中带内干扰抑制问题,提出一种基于最低误码率准则的非线性几何特征均衡器,并用径向基函数神经网络来实现.为优化非线性均衡器的参数训练,本文构造了一种新的遗传随机梯度混合算法.仿真表明:对于扩展的二元相移键控信号,在相对强的窄带干扰下,匹配滤波器及线性均衡器已失效,而基于最低误码率准则的几何特征均衡器仍能表现出良好的性能,也大大优于基于最小均方误差准则的非线性均衡器.     

A Simplified Two-Stage Equalizer with a Reduced Number of Multiplications for Data Transmission over Voiceband Telephone Links

The paper presents an equalization scheme based on the two-stage equalizer originally introduced by Proakis. Mostly additions are required for implementation of the equalizer structure and the adaptation algorithm. The equalizer can be applied to data transmission Systems which use four-phase modulation, especially in 1200/2400 bit/s modems, thus replacing the fixed equalizer recommended by CCITT. The results presented in the paper deal with the analog and digital implementation of the proposed equalizer. Its performance is compared to the performance of the conventional transversal equalizer, a decision-feedback equalizer, an ideal linear canceller, and an ideal QPSK system.     

一个用于背板通信的24Gb/s高速自适应组合均衡器

本文介绍了应用于背板通信系统中均衡器的设计与实现.该均衡器采用连续时间线性均衡器（Continuous Time Linear Equalizer,CTLE）和2抽头判决反馈均衡器（Decision Feedback Equalizer,DFE）的组合结构来消除信道码间干扰中的前标分量和后标分量.在设计中,CTLE采用双路均衡器结构补偿信道不同频率的损耗,减小了电路的面积和功耗;DFE采用半速率预处理结构来缓解传统DFE结构中关键反馈路径的时序限制,并采用模拟最小均方（Least Mean Square,LMS）算法电路控制DFE系数的自适应.电路采用IBM 0.13μm BiCMOS工艺设计并实现,测试结果表明对于经过18英寸背板后眼图完全闭合的24Gb/s的信号,均衡后的眼图水平张开度达到了0.81UI.整个均衡器芯片包括焊盘在内的芯片面积为0.78×0.8mm²,在3.3V的电源电压下,功耗为624mW.     

TURBO EQUALIZATION WITH JOINTLY GAUSSIAN EQUALIZER

A Jointly Gaussian (JG) equalizer is derived for turbo equalization based on an augmented real matrix representation of channel model and a Gaussian approximation of the received symbol sequence. Using matrix inversion lemma and Cholesky decomposition, a lowcomplexity implementation of JG equalizer is also presented. The simulation results and complexity comparison confirm that turbo equalization with JG equalizer has a better performance and a lower complexity than the existing turbo equalization with linear minimum mean squared error equalizer.     

分数间隔判决反馈盲均衡器的设计与仿真

卫星高速数传的速率已经数百Mb/s甚至上Gb/s的量级,码间干扰和群时延影响已不可忽视。采用易于高速实现的LMS算法,和有利于提高接收机的性能的分数间隔和判决反馈均结构,设计出了一种高性能盲均衡器。该均衡器的设计目标立足于具有较好性能和易于工程上现场可编程门阵列（FPGA）实现。通过仿真均衡前后误码增益,得到4种情况下均衡器的性能理论曲线。所设计的均衡器和仿真的性能理论曲线,可以为工程设计提供有益参考。     

QAM均衡器的设计与实现

通过对QAM均衡算法和均衡器结构的分析,总结了如何根据系统的需要来选择算法和均衡器实现的结构.本文采用CMA DDLMS算法,并对算法进行了简化和FPGA实现的逻辑优化,取得了较好的性能和FPGA资源的折中.     

A Hardware Efficient Passband Equalizer Structure for Data Transmission

A passband digital equalizer is proposed which combines the functions of bandpass filtering and phase splitting with that of adaptive equalization. The new equalizer also provides the in-phase and quadrature outputs required for demodulation. Although input sampling is required at several times the symbol rate (for voice-grade channel applications), outputs need be computed only once per baud. This structure economizes either on front-end analog (phase splitter) filtering or on the number of multiplications required in a digital implementation of a phase splitter and an equalizer. The performance of a receiver incorporating the new equalizer is compared, experimentally, with a receiver using a conventional fractionally spaced (T/2) equalizer.     

An adaptive analog noise-predictive decision-feedback equalizer

In this paper, an adaptive noise-predictive decision-feedback equalizer (NPDFE) is presented. The NPDFE architecture and its implementation are described. The NPDFE consists of an analog finite-impulse-response (FIR) forward equalizer, a recursive analog equalizer for noise prediction, and a decision-feedback equalizer (DFE). The recursive equalizer reduces noise enhancement and improves the signal-to-noise ratio (SNR) at the decision slicer input. The prototype targets a magnetic recording channel modeled by a Lorentzian impulse response. Measured results show that compared to a conventional DFE with FIR forward equalizer, the NPDFE achieves a SNR improvement of about 2 dB with PW₅₀=2.5T. The NPDFE consumes 130 mW at a data rate of 100 Mb/s and occupies 1.3 mm² of die area in a 0.5-μm CMOS process     

一种用于水声信道的稀疏权超指数迭代盲均衡算法研究

超指数算法的迭代算法便于跟踪时变信道,但是,其计算量与权长的平方成比例,不利于工程实现.该文利用水声信道的稀疏性,采用超指数算法的部分步骤,估计权向量并进行稀疏处理,初始化超指数迭代算法,不但减小了算法的计算量,而且加快了算法的收敛速度.计算机仿真证明了该方法的有效性.     

An LSI Implementation of an ISDN Echo Canceller: Design and Network Aspects

This paper describes a single/chip VLSI implementation of aU-interface system component called transceiver with echo cancelling (TEC). The transceiver is implemented with the adaptive echo cancelling method and is combined with a decision feedback equalizer. The algorithms are based on the sign algorithm, but have been considerably improved by using an adaptive reference level. Besides the transceiver functions, functions for activation/deactivation, maintenance, and test are also included in the chip.     

Design of a Charge Equalizer Based on Battery Modularization

The charge equalizer design for a series-connected battery string is very challenging because it needs to satisfy many requirements, such as implementation possibility, equalization speed, equalization efficiency, controller simplicity, size and cost issues, voltage and current stress, and so on. Numerous algorithms and circuits were developed to meet the foregoing demands, and some interesting results have been obtained. However, for a large number of cells, for example, 80 or more batteries, the previous approaches might not easily satisfy the foregoing requirement. To overcome these difficulties, we propose a charge equalizer design method based on a battery modularization technique. In this method, a very long battery string is divided into several modules, and then, an intramodule equalizer and an outer-module equalizer are designed. This battery modularization scheme effectively reduces the number of cells that we consider in an equalizer design procedure; thus, the design of a charge equalizer becomes easier. Furthermore, by applying the previously verified charge equalizers to the intramodule and the outer module, we can make the equalizer design more flexible. Several examples and experimental results are presented to demonstrate the usefulness of the charge equalizer design method.