磁场中布里曼法生长碲镉汞晶体的缺陷腐蚀分析

用化学腐蚀方法研究了磁场中布里曼法生长碲镉汞晶体的位错和亚晶界，在施加磁场的样品中观察到分布较为均匀的位借和较少的亚晶界，这可能是由于在生长过程中施加了磁场对组分分凝和组分过冷起到了一定的抑制作用。     

位错对布里奇曼HgCdTe体晶结构完整性的影响

本文根据Ｘ射线形貌相、扫描电镜和金相显微镜的实验结果和有关位错、相图的理论，分析了位错和亚晶界、亚晶界和Ｘ射线形貌相的关系以及住错对布里奇曼技术生长的ＨｇＣｄＴｅ体晶结构完整性的影响。因位错降低能量的要求，ＨｇＣｄＴｅ体晶中的密度位错要形成亚晶界和三维位错网络等亚结构。在Ｘ射线形貌相中，亚结构的取向衬度是比位错直接象更强的成象机构。正常凝固长晶过程中ＨｇＣｄＴｅ材料的组分要变化，并使其固液界面的温度梯度也发生相应变化，由此引入的热应力在结晶过程中会在ＨｇＣｄＴｅ晶体中产生高密度位错。位错形成的亚晶界和三维位错网络等亚结构严重破坏了ＢｒｉｄｇｍａｎＨｇＣｄＴｅ体晶结构完整性，这使其Ｘ射线形貌相往往不好。     

铌酸锂单晶体的缺陷检测

本文介绍了[001]生长的铌酸锂单晶体中有关位错、亚晶界、包果体、组分过冷等缺陷的检测方法,以及[110]生长的铌酸锂晶体中有关孪晶的检测方法.并对有些缺陷作了一些分析.     

碲镉汞晶体结构性质的电子显微术研究

采用扫描电子显微术对布里奇曼法、固态再结晶法和碲溶剂法生长的Ｈｇ１－ｘＣｄｘＴｅ晶体的结构性质进行了研究，结果表明位错和亚晶界是三种方法所得晶体的主要缺陷，而位错和亚晶界的形态与分布则取决于被研究面的结晶学取向。实验还观察到经过长期高温退火的晶体中单个位错成规则的点阵分布，或排列成位错墙。此外也观察到孪晶，多晶以及第二相等结构缺陷。     

红外材料器件

采用红外显微镜、X射线双晶回摆衍射法、X射线貌相术对CdZnTe衬底中的沉淀相、亚结构、组分偏析等缺陷进行了研究,并对用此衬底液相外延的HgCdTe薄膜作了测试。结果显示: CdZnTe衬底中亚晶界处聚集的位错在外延生长中呈发散状向薄膜中延伸,造成了薄膜形成亚晶界和更大面积的由位错引起的晶格畸变应力区域,影响了薄膜结构的完整性。     

碲锌镉衬底缺陷对液相外延碲镉汞薄膜结构的影响

采用红外显微镜、X射线双晶回摆衍射法、X射线貌相术对CdZnTe衬底中的沉淀相、亚结构、组分偏析等缺陷进行了研究,并对用此衬底液相外延的HgCdTe薄膜作了测试。结果显示：CdZnTe衬底中亚晶界处聚集的位错在外延生长中呈发散状向薄膜中延伸,造成了薄膜形成亚晶界和更大面积的由位错引起的晶格畸变应力区域,影响了薄膜结构的完整性。     

类单晶硅锭中的亚晶粒结构分析

当前类单晶硅锭生长技术已能容易地获得尺寸数倍于太阳电池硅片的<001>取向的超大"晶粒",但在其硅片中存在亚晶粒。采用位错刻蚀与显微观察、X射线双晶衍射和背散射电子衍射(EBSD),研究了该类硅片的亚晶粒及亚晶界结构。结果表明:硅片中亚晶粒尺寸为3～6 mm,其中的亚晶界对位错刻蚀十分敏感,为密排位错列组成,亚晶粒内部同时也存在与普通多晶硅锭中平均密度相当的位错;亚晶粒之间相互取向差别小于10°,而且基本是以<001>为轴的旋转位向差,故能够保证(001)面特有的金字塔型碱腐蚀制绒效果;类单晶硅锭的结晶质量有待于进一步提高,应尽量避免亚晶粒的产生。     

08F钢亚晶界位错网络的弱束暗场显示

本文利用弱束暗场技术显示了08F铜经50％室温形变后,560℃加热10小时晶粒处于回复状态时,亚晶界的位错网络。结果表明:α-Fe经形变回复后,亚晶界位错成规则整齐的排列。明场象中虽能见到位错的规则排列,但位错线细节不够清楚(见图a);而弱束暗场象则清晰地显示出亚晶界位错网络的各种形态(见图b、c、d),位错线的象宽度降低到20～30A,充分显示了弱束暗场技术在复杂位错网络显示中的特殊作用。根据弱束成象时,衍射花样中菊池线的位置计算了偏移参量|sg|,结果表明,用g=110成弱     

几种氧化物晶体的缺陷检测

本文用化学腐蚀法和光轴干涉图法研完了几种氧化物晶体的位错和亚晶界的分布,探讨了LiNbO_3晶体中的各种晶界以及TeO_2、PbMoO_4和Bi_(12)GeO_(20)晶体中的位错和亚晶界的分布对其光学性能的影响。     

合金铁素体的位错结构与疲劳断裂

合金铁素体中存在倾斜和扭转亚晶界。合金铁素体在循环拉伸应力作用下主要以条纹状断裂方式进行疲劳裂纹扩展。疲劳裂纹扩展的断裂单元为铁素体的晶粒,铁素体的原始亚晶界和疲劳塑性变形时形成的位错胞。     

The formation of subgrain boundaries in GaAs single crystals

The formation of subgrain boundaries is observed in GaAs wafers grown by a variety of methods. After heating, subgrain boundaries are revealed both by enhanced oxidation and chemical etching. The mechanism of the subgrain boundary formation apparently is the relief of surface stress by dislocation glide on the application of heat. Temperatures as low as 300 degrees appear sufficient for the formation of surface polygonization. The amount of polygonization appears to be related to the growth procedure.     

Reduction of Dislocation Density in HVPE-Grown GaN Epilayers by Using In Situ-Etched Porous Templates

In this paper, a method was demonstrated to reduce the dislocation density of GaN film grown by hydride vapor phase epitaxy (HVPE) on an in situ selective hydrogen-etched GaN/sapphire template. The dislocations regions were etched by hydrogen to form cavities. The porous structure was formed on the GaN template grown by metal organic chemical vapor deposition after in situ hydrogen etching. The etching condition was optimized by modulating the etching temperature, pressure, and etching time. Two-step buffer layer growth and high temperature GaN film deposition were carried on the porous template. The growth parameters were optimized to keep the porous structure unfilled. The dislocations originally located in etched cavities could not propagate to the next layer grown by HVPE. Therefore, the dislocation density could be significantly reduced. High crystal quality of GaN is obtained with a low dislocation density. The full width at half-maximum FWHM of (002) is 35 arcs, and the FWHM of (102) is 48 arcs.     

Direct growth of CdZnTe/Si substrates for large-area HgCdTe infrared focal plane arrays

Direct epitaxial growth of high-quality 100lCdZnTe on 3 inch diameter vicinal {100}Si substrates has been achieved using molecular beam epitaxy (MBE); a ZnTe initial layer was used to maintain the {100} Si substrate orientation. The properties of these substrates and associated HgCdTe layers grown by liquid phase epitaxy (LPE) and subsequently processed long wavelength infrared (LWIR) detectors were compared directly with our related efforts using CdZnTe/ GaAs/Si substrates grown by metalorganic chemical vapor deposition (MOCVD). The MBE-grown CdZnTe layers are highly specular and have both excellent thickness and compositional uniformity. The x-ray full-width at half-maximum (FWHM) of the MBE-grown CdZnTe/Si increases with composition, which is a characteristic of CdZnTe grown by vapor phase epitaxy, and is essentially equivalent to our results obtained on CdZnTe/GaAs/Si. As we have previously observed, the x-ray FWHM of LPE-grown HgCdTe decreases, particularly for CdZnTe compositions near the lattice matching condition to HgCdTe; so far the best value we have achieved is 54 arc-s. Using these MBE-grown substrates, we have fabricated the first high-performance LWIR HgCdTe detectors and 256 x 256 arrays using substrates consisting of CdZnTe grown directly on Si without the use of an intermediate GaAs buffer layer. We find first that there is no significant difference between arrays fabricated on either CdZnTe/Si or CdZnTe/GaAs/Si and second that the results on these Si-based substrates are comparable with results on bulk CdZnTe substrates at 78K. Further improvements in detector performance on Si-based substrates require a decrease in the dislocation density.     

异质衬底外延碲镉汞薄膜位错抑制技术进展

分子束外延碲镉汞技术是制备第三代红外焦平面探测器的重要手段,基于异质衬底的碲镉汞材料具有尺寸大、成本低、与常规半导体设备兼容等优点,是目前低成本高性能红外探测器发展中的研究重点。对异质衬底上碲镉汞薄膜位错密度随厚度的变化规律进行了建模计算,结果显示ρ～1/h 模型与实验结果吻合度好,异质衬底上原生碲镉汞薄膜受位错反应半径制约,其位错密度无法降低至 5×10⁶cm^-2以下,难以满足长波、甚长波器件的应用需求。为了有效降低异质外延的碲镉汞材料位错密度,近年来出现了循环退火、位错阻挡和台面位错吸除等位错抑制技术,本文介绍了各技术的原理及进展,分析了后续发展趋势及重点。循环退火和位错阻挡技术突破难度大,发展潜力小,难以将碲镉汞位错密度控制在 5×10⁵cm^-2以内。台面位错吸除技术目前已经显示出了巨大的发展潜力和价值,后续与芯片工艺融合后,有望大幅促进低成本长波、中长波、甚长波器件的发展。     

Effects of twin grain boundaries on the subgrain rotation of the solder joint during thermal shock

The ball grid array (BGA) component was selected as the specimen with the outmost edge row cross-sectioned to investigate subgrain rotation behavior influenced by grain boundaries under thermal shock cycles condition. To study the subgrain rotation, the crystal orientation was obtained by electron backscattered diffraction(EBSD). The results showed that a lot of subgrains were generated in the solder joints due to cyclic stress caused by the high mismatched coefficient of thermal expansion (CTE) under the thermal shock cycles condition. And the subgrains near the chip-side and the twin grain boundaries were analyzed in detail to estimate the impact of the grain boundaries on the subgrain rotation behavior. The results showed that a large number of subgrain boundaries and several newly generated subgrains appeared at the tilted twin grain boundaries and the chip-side in the solder joint after 200 thermal shock cycles. Meantime, the subgrain rotation axes and misorientation angles were both calculated, and the dislocation slip was recognized to closely relate to subgrain rotation by comprehensively analyzing the rotation axes and misorientation angles. The subgrain rotation axes of the chip-side was about Sn [101] and [001], while the subgrains rotation near the tilted grain boundaries in the same dominant grain was different from that of the subgrains near the chip-side, and subgrain rotation axes were [101], [100] and [110]. There were also a large difference in the direction of subgrain rotation between the chip-side and the tilted twin grain boundaries. The subgrain rotation axes at both sides of twin grain boundaries were similar, but the rotation directions were opposite.     

生长压力对MOCVD GaN材料晶体质量的影响

使用氮化物MOCVD外延生长系统,采用传统的两步生长法在76.2 mm c面蓝宝石衬底上生长了不同压力的GaN薄膜样品.研究发现提高高温GaN的生长压力,初期的三维生长时间增长,有利于提高GaN薄膜的晶体质量.同时采用XRD、PL谱和湿化学腐蚀方法研究了样品的位错特性,结果表明高压生长的样品能够降低位错密度,起到改善G...     

New surface treatment method for improving the interface characteristics of CdTe/Hg1−xCdxTe heterostructure

This paper presents a new simple method of HgCdTe surface treatment which consists of chemical oxidation of HgCdTe with nitric acid and removal of the oxide with ammonium hydroxide. The electrical properties of the electron-beam deposition CdTe passivation of Hg_0.7Cd_0.3Te are investigated with regard to the effects of HgCdTe surface etching, exposure to nitric acid, and the new surface treatment method. As the HgCdTe surface is progressively etched with bromine in methanol (Br-MeOH), the surface becomes rougher and a higher density of fixed charge is induced at the interface between CdTe and HgCdTe. Exposure to HNO₃ results in a very high density of fixed charge and performance degradation in metal insulator semiconductor (MIS) capacitors, which is due to the chemical oxide grown by HNO₃. The oxide growth rate is enhanced as the concentration of HNO₃ increases or as more H₂O is added. This oxide can be removed with NH₄OH. After the new surface treatment, MIS capacitors of Hg_0.7Cd_0.3Te show substantial improvement in electrical properties, such as low density of fixed charge and reduced hysteresis width, regardless of previous surface etching.