SILC dynamics in MOS structures subject to periodic stress

This work investigates stress-induced leakage current (SILC) in thin-oxide MOS capacitors subject to (quasiperiodic) ac voltage stress, under the condition of fixed charge fluence through the oxide. It shows that both trap creation and spontaneous trap annealing play a significant role when the duration of, and the time between, high-voltage pulses are comparable with characteristic times of trap dynamics. A phenomenological model is introduced that is able to accurately represent the main physical phenomena due to pulsed voltage stress under conditions of interest for unconventional programming schemes for fast programming nonvolatile memories (NVMs) with acceptable oxide degradation.     

Read disturb in flash memories: reliability case

It is known that program/erase cycling of Flash memories induces a degradation of the tunnel oxide insulating property usually referred to as Stress-Induced Leakage Current (SILC). An issue related to SILC is the read disturb, affecting cells in an addressed word-line, which can cause electron injection through tunnel oxide in the floating gate of erased cells during read operation. Read disturb can also be present in Flash memory with a weak tunnel oxide quality: aim of this paper is to discuss in detail the effect of this read disturb phenomena. Cell Failure Density (CDF) extrapolation from experimental data using statistical method is able to estimate defect probability and application’s failure rate for both SILC and weak tunnel oxide quality cases.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化.实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系.为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

The degradation of device under GIDL(gate-induced drain leakage current)stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides.Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg.The characteristics of the GIDL current are used to analyze the damage generated during the stress.It is clearly found that the change of GIDL current before and after stress can be divided into two stages.The trapping of holes in the oxide is dominant in the first stage,but that of electrons in the oxide is dominant in the second stage.It is due to the common effects of edge direct tunneling and band-to-band tunneling.SILC(stress induced leakage current)in the NMOSFET decreases with increasing stress time under GIDL stress.The degradation characteristic of SILC also shows saturating time dependence.SILC is strongly dependent on the measured gate voltage.The higher the measured gate voltage,the less serious the degradation of the gate current.A likely mechanism is presented to explain the origin of SILC during GIDL stress.     

Role of positive trapped charge in stress-induced leakage current for flash EEPROM devices

The transient behavior of hot hole (HH) stress-induced leakage current (SILC) in tunnel oxides is investigated. The dominant SILC mechanism is positive oxide charge-assisted tunneling (PCAT). The transient effect of SILC is attributed to positive oxide charge detrapping and thus the reduction of PCAT current. A correlation between SILC and stress-induced substrate current is observed. Our study shows that both SILC and stress-induced substrate current have power law time-dependence t/sup -n/ with the power factor n about 0.7 and 1, respectively. Numerical analysis for PCAT current incorporating a trapped charge caused Coulombic potential in the tunneling barrier is performed to evaluate the time- and field-dependence of SILC and the substrate current. Based on our model, the evolution of threshold voltage shift with read-disturb time in a flash EEPROM cell is derived. Finally, the dependence of SILC on oxide thickness is explored. As oxide thickness reduces from 100 /spl Aring/ to 53 /spl Aring/, the dominant SILC mechanism is found to change from PCAT to neutral trap-assisted tunneling (TAT).     

High-field-induced leakage in ultrathin N2O oxides

Stress-induced leakage current (SILC) is studied in ultrathin (~50 Å) gate oxides grown in N₂O or O₂ ambient, using rapid thermal processing (N₂O oxide or control oxide, respectively). MOS capacitors with N₂O oxides exhibit much suppressed SILC compared to the control oxide for successive ramp-up, constant voltage DC, and AC (bipolar and unipolar) stresses. The mechanism for SILC is discussed, and the suppressed SILC in N₂O oxide is attributed to suppressed interface state generation due to nitrogen incorporation at the Si/SUO₂ interface during N₂O oxidation     

Reliability improvements in 50 nm MLC NAND flash memory using short voltage programming pulses

For the first time, an innovative programming methodology based on the use of ultra-short voltage pulses is applied in NAND flash architecture. The methodology starts from the physics of SILC dynamics and oxide damage, and relies on the trade-off between duration and amplitude of short voltage programming pulses, minimizing the creation of new traps in the tunnel oxide. The short pulses programming technique is applied on a small 50 nm NAND array designed for multibit application. Benefits of the short-pulse operation lie in that data retention and endurance which show meaningful improvements. The result is relevant for application in multibit technology, and opens the way to more aggressive cell scaling rules.     

Reliability of erasing operation in NOR-Flash memories

The erase operation in NOR-Flash memories intrinsically gives rise to a wide threshold voltage distribution causing various reliability issues: read margin reduction; increase of total bitline leakage current and electrical stress during reading and programming. This paper will address and review the erasing operation by analyzing the causes, the reliability issues and the possible solutions of the erased threshold voltage distribution width, the presence of ultrafast bits, the erratic erase phenomenon, the presence of a significant tail (extrinsic behavior) in the erased distribution and the intrinsic oxide degradation during cycling (oxide aging).     

Mechanism of stress-induced leakage current in MOS capacitors

Stress-induced leakage current (SILC) is examined both below and above the voltage at which the preexisting Fowler-Nordheim tunneling current dominates. Based on these results, it is argued that SILC is the result of inelastic rather than elastic trap-assisted tunneling. This clarification explains the well-known thickness dependence of the SILC at low fields that has identified it as a scaling limitation for nonvolatile memory tunnel oxide. It also explains a newly observed different thickness dependence at high fields and facilitates modeling of the electric field/voltage and trap density dependencies of the SILC     

Study of stress-induced leakage current (SILC) in HfO2/Dy2O3 high-κ gate stacks on germanium

In the present work we study reliability issues of Pt/HfO₂/Dy₂O₃/n-Ge MOS structures under various stress conditions. The electrical characteristics of the micro-capacitors are very good probably due to the presence of a rare earth oxide as interfacial layer. It is shown that the injected charge (Q_inj) at high constant voltage stress (CVS) conditions induces stress-induced leakage current (SILC) that obeys a power-law. We also observe a correlation between the trapped oxide charge and SILC, which is, at low stress field, charge build-up and no SILC, while at high stress field SILC but few trapped charges. Results show that the present bilayer oxides combination can lead to Ge based MOS devices that show acceptable degradation of electrical properties of MOS structures and improved reliability characteristics.     

Statistical profiling of SILC spot in flash memories

A new experimental technique for evaluating the position of the oxide weak spot responsible for the stress-induced leakage current (SILC) in flash memories is presented. The oxide field along the channel is modified by drain biasing, and the gate current is then monitored. The position of the leakage spot can be determined by the shift in the gate current-voltage (I-V) characteristics. Experimental results on flash memory arrays reveal a strong localization of SILC in correspondence of the drain junction, due to the cooperation effects of program/erase (P/E) operations. The technique can be used to optimize the P/E conditions for maximum device reliability.     

Characterization of hot-hole injection induced SILC and relateddisturbs in flash memories

In this paper, we have proposed a new method for the study of disturb failure mechanisms caused by stress induced leakage current (SILC) in source-side erased flash memories. This method is able to directly separate the individual components of SILC due to either carrier charging/discharging in the oxide or the positive charge/trap assisted electron tunneling into the floating gate. In addition, the present method is very sensitive with capability of measuring ultralow current (<10^-19 A). Results show that, at low oxide field, the disturb is mainly contributed by the so-called charging/discharging of carriers into/from the oxide due to the capacitance coupling effect. While at high oxide field, the positive charge/trap assisted electron tunneling induced floating-gate charge variation is the major cause of disturb failure     

Relation between defect generation, stress induced leakage current and soft breakdown in thin (<5 nm) oxides

The normalized stress induced leakage current (SILC) measured when the oxide is subjected to low level constant-current stresses shows a tendency towards saturation at large charge fluences. To investigate the origin of this saturation, the degradation of the oxide has been analyzed using two independent methods: SILC data analysis and a two-step stress test. The results show that, although under low stress currents the SILC saturation is observed, the degradation (i.e., the generation of defects) proceeds until the soft breakdown (SBD) event takes place. The implications for the use of SILC data as degradation monitor are analyzed.     

Monitoring the degradation that causes the breakdown of ultrathin(<5 nm) SiO2 gate oxides

The degradation of ultrathin oxides subjected to constant-current stresses is analyzed using two independent procedures. First, the injected charge to breakdown is estimated from the stress-induced leakage current (SILC) evolution during the stress. Second, the degradation that leads to the breakdown is directly measured using a two-step stress test. The evolution of the SILC during constant-current stresses proceeds at a rate that decreases with time. Moreover, under low current density stress conditions the normalized SILC at breakdown is no longer constant. However, our two-step test methodology shows that the degradation of the oxide evolves roughly linearly until the breakdown. These apparently contradictory results can be reconciled assuming that the degradation at breakdown is independent of the stress conditions and using the initial SILC generation rate to calculate the charge-to-breakdown by linear extrapolation. The implications for the use of SILC data as a degradation monitor are discussed     

On stress induced leakage current in 5 and 3 nm thick oxides

The stress induced leakage current (SILC) in Si/SiO₂ structures with thin gate oxides has a steady-state component which increases drastically when the oxide thickness decreases. It is generally agreed that the SILC is due to electron tunnelling trough stress-induced traps. However, it was observed that the SILC, created by Fowler–Nordheim injection, decays continuously when, after stress, the samples are positively or negatively biased at a low voltage. The decay is irreversible as long as the gate oxide is not biased at a high voltage. The present article adds complementary observations. It shows, first that the above phenomenon is observed in 3.5 nm thick oxides, secondly, that this phenomenon is stable as long as the temperature stays below 200°C, and thirdly, that during the SILC decay, the interface state density does not diminish.     

Reversibility of charge trapping and SILC creation in thin oxides after stress/anneal cycling

The reversibility of charge buildup and SILC generation in thin oxides subjected to successive stress/anneal cycles is investigated. It is demonstrated that in thin oxides both electron trapping and SILC are nearly fully reversible degradation processes having a generation kinetics almost unchanged after several stressing/annealing cycles. The annealing kinetics of the SILC is likely associated to the out diffusion of charged defects (possibly trapped holes or H+) whose characteristics (diffusivity, activation energy) are independent of the oxide thickness. Moreover correlation between electron trapping and SILC generation has been studied.     

Numerical confirmation of inelastic trap-assisted tunneling (ITAT)as SILC mechanism

This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time τ, the neutral electron trap density N_t, and the trap energy level E_t. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are thoroughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build N _t explicitly as a function of the stress electron fluence. Then the overall tunneling probability is calculated, with which a best fitting to SILC I-V furnishes τ of 4.0×10^-13 s and E_t of 3.4 eV. The extracted τ is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well     

Constant current stress of lightly Al-doped Ta2O5

The response of lightly Al-doped Ta₂O₅ stacked films (6 nm) to constant current stress (CCS) under gate injection (current stress in the range of 1 to 30 mA/cm² and stressing time of 50–400 s) has been investigated. The stress creates positive oxide charge, which is assigned to oxygen vacancies but it does not affect the dielectric constant of the films. The most sensitive parameter to the stress is the leakage current. Different degradation mechanisms control the stress-induced leakage current (SILC) in dependence on both the stress conditions and the applied measurement voltage. The origin of SILC is not the same as that in pure and Ti- or Hf-containing Ta₂O₅. The well known charge trapping in pre-existing traps operates only at low level stress resulting in small SILC at accumulation. The new trap generation plays a key role in the SILC degradation and is the dominant mechanism controlling the SILC in lightly Al-doped Ta₂O₅ layers.     

SILC-related effects in flash E2PROM's-Part I: Aquantitative model for steady-state SILC

In this paper a quantitative model for the steady-state component of the stress induced leakage current (SILC) is developed. The established model is based on the observation of basic degradation monitors on conventional, thermal SiO₂ gate dielectrics in the thickness range of 6.8-7.1 nm. From a systematic, experimental study, it has been found for the first time that the steady-state SILC, observed after a wide range of constant current stress (CCS) conditions (gate injection polarity), can be uniquely described by a simple, semi-empirical relation, which consists of two parts: 1) the dependence on the measurement field is described as Fowler-Nordheim (FN) tunneling through an oxide barrier of reduced but fixed height (i.e., 0.9 eV), and 2) the level of the SILC at a fixed oxide field is given by the density of neutral bulk oxide traps. Except for a calibration, depending on the oxide thickness and processing, no model parameters have to be adjusted in order to describe all our data. Also, based on bake experiments it has been concluded that interface traps are not causally related to the steady-state SILC in spite of the linear relation which exists between both. Furthermore, these bake experiments provide new evidence that bulk oxide traps play a crucial role in the SILC conduction mechanism