Distortion cancellation by polyphase multipath circuits

It is well known that in balanced (or differential) circuits, all even harmonics are canceled. This cancellation is achieved by using two paths and exploiting phase differences of 180/spl deg/ between the paths. The question addressed in this paper is: what distortion products (harmonics and intermodulation products) are canceled if more than two paths (and phases) are used? These circuits are called polyphase multipath circuits. It turns out that the more paths (and phases) are used, the more distortion products are canceled. Unfortunately, some intermodulation products cannot be canceled without also canceling the desired signal. An analysis of the impact of mismatch between the paths shows that the suppression of distortion products will be larger if more paths are used. As an application example, the design of an upconversion mixer with a clean output spectrum is presented.     

MIMO satellite communication with accelerated dual paths asynchronous design

This paper presents a novel asynchronous design approach for multiple input multiple output (MIMO) satellite communication (SatCom) systems. One of the main challenges for MIMO SatCom systems is that these are prone to transient faults that typically are attributable to radiation hazards. Hence, instead of using conventional synchronous circuits, we conceive our design using asynchronous circuits since it inherently has a high tolerance to transient fault. Additionally, we adopt accelerated dual paths (ADP) design into our system. By carefully arranging the data flow between the two paths, the ADP design approach can help to further accelerate the asynchronous system and increase the reliability of the system by circumventing transient faults induced delay, as well as tolerating latch-ups and other permanent faults. The numerical results show that this design approach provides promising results. For example, the proposed design can decrease the delay overhead of the entire system from 43.5 to 19.8 % at the fault rate of 400/clock cycle.     

对全局控制信号设置多周期路径的方法

在数字集成电路(Integrated Circuit,IC)设计中,一些流水运行、分级计算的电路,使用全局控制信号(Global Control Signal,GCS)来进行设计是易于实现的一种方法。对于时序紧张的全局控制信号,通过在逻辑设计阶段,降低全局控制信号控制优先级;在逻辑综合阶段,加入多周期路径设置的指令,可以将全局控制信号设置为具有多周期路径特性的信号,能够有效地改善时序,降低后期物理设计的布线难度,从而达到设计目的。     

Design error diagnosis in digital circuits with stuck-at fault model

In this paper we describe in detail a new method for the single gate-level design error diagnosis in combinational circuits. Distinctive features of the method are hierarchical approach (the localizing procedure starts at the macro level and finishes at the gate level), use of stuck-at fault model (it is mapped into design error domain only in the end), and design error diagnostic procedure that uses only test patterns generated by conventional gate-level stuck-at fault test pattern generators (ATPG). No special diagnostic tests are used because they are much more time consuming. Binary decision diagrams (BDD) are exploited for representing and localizing stuck-at faults on the higher signal path level. On the basis of detected faulty signal paths, suspected stuck-at faults at gate inputs are calculated, and then mapped into suspected design error(s). This method is enhanced compared to our previous work. It is applicable to redundant circuits and allows using incomplete tests for error diagnosis. Experimental data on ISCAS benchmark circuits shows the advantage of the proposed method compared to the known algorithms of design error diagnosis.     

Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits

Through-silicon-via (TSV) interconnect is one of the main technologies for three-dimensional integrated circuits production (3-D ICs). Based on a parasitic parameters extraction model, first order expressions for the TSV resistances, inductances, and capacitance as functions of physical dimension and material characteristic are derived. Analyzing the impact of TSV size and placement on the interconnect timing performance and signal integrity, this paper presents an approach for TSV insertion in 3D ICs to minimize the propagation delay with consideration to signal reflection. Simulation results in multiple heterogeneous 3D architectures demonstrate that our approach in generally can result in a 49.96% improvement in average delay, a 62.28% decrease in the reflection coefficient, and the optimization for delay can be more effective for higher non-uniform inter-plane interconnects. The proposed approach can be integrated into the TSV-aware design and optimization tools for 3-D circuits to enhance system performance.     

基于比较器的四值电流型CMOS加减电路设计

该文通过对电流型CMOS电路的阈值控制引入了多值电流型比较器。与2值逻辑电路相比,多值逻辑电路的单条导线允许更多的信息传输。相较于电压信号,电流信号易实现加、减等算术运算,在多值逻辑的设计上更加方便。同时提出了基于比较器的4值基本单元设计方法,实现了4值取大、取小以及反向器的设计,在此基础上设计实现了加法器和减法器。该设计方法在2值、3值以及n值逻辑上同样适用。实验结果表明所设计的电路具有正确的逻辑功能,较之相关文献电流型CMOS全加器有更低的功耗和更少的晶体管数。     

A novel method for multipath routing using cross layer approach in vehicular adhoc networks

Vehicular Adhoc Network (VANET) is playing a vital role in recent research. Designing an effective routing protocol for VANET is a challenging task as the VANET nodes move very fast. The design of the routing protocol normally is particular to the specific topology. This paper proposes CLMR, a multipath routing protocol based on cross layer design and also using Redundant Array Inexpensive Disks (RAID). Cross layer is designed among application, network, Media Access Control, and physical layers. It is employed to reduce the end to end delay in network, and RAID is used to minimize the number of re‐transmissions. Three variations of RAID 1 are implemented—Distributed Parity along Single path, Double Distributed Parity, and Distributed Parity among Multiple paths. Multipath routing protocol based on cross layer‐Distributed Parity along Single path recovers 1 packet loss per parity packet along the corresponding path, CLMR‐Double Distributed Parity recovers 2 packets per parity packet along the corresponding path, and CLMR‐Distributed Parity among Multiple paths recovers the packets of the failed path. The evaluation is carried out to test the Quality of Service parameters‐end to end delay, throughput, packet delivery ratio, and number of retransmissions. The results projected show that the CLMR performs better when compared with the legacy protocol Adhoc On‐demand Multipath Distance Vector Routing.     

基于FPGA的激光引信信号处理单元设计

分析了多象限激光引信系统的组成和工作原理。现场可编程门阵列(FPGA)具有体积小,集成度高和接口资源丰富的特点,有利于实现信号处理电路小型化设计和引信复杂算法设计。通过软件算法仿真和整机测试,基于FPGA的信号处理电路满足引信实时性要求,并给出了信息处理流程。针对阳光和云雾干扰的抗干扰算法及目标识别算法提高了引信抗干扰能力。     

混合模式下详细布局算法的时延优化策略

在集成电路物理设计中,布局是提升电路时延性能的关键阶段。对混合单元模式的详细布局采取二段式的时延优化策略,以此提高布局质量。在合法化阶段,代价函数中采用增加时延权重因子的方法来调整单元的移动策略,使单元分布更有利于时延。在优化阶段,对关键路径上单元的位置进行评价,试探性地对这些单元进行位置微调,在减少关键路径时延的同时避免对布局产生大的扰动,进一步优化了时延。实验结果表明,二段式时延优化策略能够在线长代价较小的情况下有效地提升电路性能。     

静态时序分析及其在IC设计中的应用

讨论了静态时序分析算法及其在IC设计中的应用。首先，文章讨论了静态时序分析中的伪路径问题以及路径敏化算法，分析了影响逻辑门和互连线延时的因素。最后通过一个完整的IC设计流程介绍了静态时序分析的应用。     

Efficient logic-level timing analysis using constraint-guidedcritical path search

As the operating speed of digital circuits dramatically increases with the advance of VLSI technology, it is becoming more critical to ensure that the circuits are free from timing-related design errors. In a traditional static timing approach nonfunctional paths cannot be distinguished from functional ones since the functionality of a circuit is ignored. This often results in overestimation of circuit delay and can degrade the circuit performance. In today's design methodology where the use of automated logic synthesis and module-based design are popular, circuits with a very large number of nonfunctional (false) paths are common. This paper describes an efficient logic-level timing analysis approach that can provide an accurate delay estimate of a digital circuit which may have many long false paths. By using logic incompatibilities in a circuit as constraints for critical path search, the algorithm determines the longest sensitizable path without explicit path enumeration. Since the number of false paths that can be implicitly eliminated is potentially exponential to the number of path constraints, performance improvement is significant     

Microminiature solid-state imaging system utilizing hybrid LSI techniques

The authors describe the design, construction, and performance characteristics of a low-resolution 50/spl times/80 element solid-state imaging system that has been fabricated using multichip large-scale integration. Techniques used to fabricate the substrate that contains 117 MOS and low-power bipolar integrated circuits plus the 4000-element phototransistor mosaic sensor array are discussed. Also, the methods used to mount and provide interdevice signal paths, including the use of advanced multilayer flexible interconnection techniques are shown.     

基于时间结构的短样本信号盲提取

 为提高盲提取算法在恢复短样本信号时的质量,本文提出基于时间结构的盲提取方法.该方法以多个延时量上统计得出的自相关平方和取代负熵来作为目标函数,并引入了输出信号与参考信号的近似测度和输出信号方差作为非线性规划的约束条件,结合拟牛顿迭代法,推导出新的单路盲信号提取迭代表达式.另外,本文还提出了衡量短样本程度的量化标准.仿真实验表明,不论所观测的各路信号长度如何,只要其包含短潜伏期的源成分,本文方法均能高质量地完成有用信号的提取.     

Monitoring of aging in integrated circuits by identifying possible critical paths

Aging of integrated circuits can no longer be neglected in advanced process technologies. Especially the strong dependence of the delay degradation of digital circuits on the workload is still an unsolved problem. If the workload is not known exactly, only a worst-case design can guarantee that the circuit works correctly during the entire specified lifetime. We propose a method that enables a better-than-worst-case design. To assure that this design still works correctly during the specified lifetime, the circuit is monitored periodically and countermeasures are taken if the circuit degrades too much. Our main contribution is an algorithm to identify all paths that might become critical during the specified lifetime. These are called possible critical paths (PCPs). This is the first approach that also considers local process variations for finding the PCPs. Without considering process variations, it is not guaranteed that all possible critical paths are found. In addition, we could reduce the number of paths that have to be monitored by 2.7× compared to a state-of-the-art approach.     

A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits

The correlation between the physical paths of a digital circuit has important implications in various design automation problems, such as timing analysis, test generation and diagnosis. When considering the complexity and tight timing constraints of modern circuits, this correlation affects both the design process and the testing approaches followed in manufacturing. In this work we quantify the diversity of a set of paths (or path segments), let these be critical I/O paths, error propagation paths for various fault models, or paths traced for diagnostic purposes. Circuit paths are encoded using Zero-Suppressed Binary Decision Diagrams (ZBDDs); the proposed method consists of a sequence of standard ZBDD operations to provide a measure of the overlap of the paths under consideration. The main contribution of the presented method is that, path or path segment enumeration is entirely avoided and, hence, a large number of paths can be considered in practical time. Experimentation using standard benchmark circuits demonstrates the effectiveness of the approach in showing the difference in path correlation between various critical I/O path sets as well as propagation paths during test application.     

Interconnect accelerating techniques for sub-100-nm gigascale systems

This work describes new circuits called capacitor coupling trigger and capacitor coupling accelerator (CCA) circuits used to reduce the long interconnect RC delay in sub-100-nm processes. The proposed circuits use capacitors to split the output driving paths to eliminate the short-circuit current and thus improve the signal transition time. Besides, the capacitor coupling technique is applied to adjust the gate threshold voltage of the proposed circuits and isolate the input signal from the output driving transistors. The proposed circuits are faster than the prior circuits. Furthermore, the CCA can be applied to bi-directional interface, multiports bus, field-programmable gate array interconnections, and complex dynamic logic circuits.     

电流返回路径分解的信号完整性分析方法

提出了一种适用于高速互连电路的信号完整性快速仿真方法。根据电流返回路径 不同,该方法将有过孔的三维互连结构分解为电源平面对阻抗模型和微带线模型,先单独分 析两种模型特性,再级联以求解整个互连结构特性。与全波仿真方法相比,本方法在保证准 确度的前提下可将仿真时间从95 min降低至1 min以内。分析了电路板参数、去耦电容和短 路孔对信号完整性的影响,结果表明插入损耗由电源平面结构在过孔位置处的自阻抗决定。 在工程设计中,可采用减小电源平面对结构厚度、添加去耦电容和选择适当的过孔位置等方 法提高信号完整性     

Design for testability of analog/digital networks

The testing of analog/digital integrated circuits is difficult since they allow direct access to relatively few signals. Since the probing of component pins is the fundamental chip production test technique (and possibly that of board test as well, i.e. in-circuit test), methods must be found to enhance the controllability and observability of internal signal networks. The authors provide a set of design for testability (DFT) principles that enhance their ability to test these networks when combined with the requisite analog test plans     

动态电路的混合时序分析方法

 本文基于四事件周期波形模型,提出了一般动态门、LO-CMOS、NTP动态门和N-C²MOS锁存器正确工作的时序约束.将混合时序分析方法应用于动态电路的延时计算,提出了动态门延时测试波形的生成算法,能有效处理多个输入同时翻转对延时的影响.本文的研究成果已在SpiceTime中实现,并且应用于一个32位动态加法器的设计,取得了良好效果,如果不考虑伪路径的影响,求值延时和预充延时的最大误差分别为3.62%和8.26%.     

Modeling single event crosstalk speedup in nanometer technologies

With advances in CMOS technology, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. In addition, coupling effects among interconnects can cause SE transients to spread electronically unrelated circuit paths which may increase the SE Susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work reports on the signal speedup effects caused by SE crosstalk and then proposes a best-case delay estimation methodology for use in design automation tools for the first time to our knowledge. The SE coupling speedup expressions derived show very good results in comparison to HSPICE results. Results show an average error of about 8.42% for best-case delay while allowing for very fast analysis in comparison to HSPICE.