Aladin: A Layout Synthesys Tool for Analog Integrated Circuits

This paper presents a layout synthesis tool called ALADIN for analog integrated circuits. It is developed especially for analog circuit designers who can bring their special knowledge and experience into the synthesis process to create high quality layouts. The layout generation is based on relatively complex sub-circuits rather than non-optimal single devices. A flexible module generator environment is developed for designers to write and maintain technology and application independent module generators of sub-circuits. Based on the thorough study of simulated annealing and genetic algorithm applications in the analog module placement, a genetic placement approach with simulated annealing and a very fast simulated re-annealing placement approach have been developed. A two-stage placement technique is proposed. Analog module routing consists of two phases including global routing and detailed routing. The minimum-Steiner-tree based global routing can be integrated into the placement procedure to improve the routability of placement solutions. The compaction based constructive detailed routing finally realizes the layout of the whole circuit. This tool is integrated into commercial software with convenient interfaces provided. The benefit of ALADIN providing layouts comparable to expert manual ones is demonstrated with several circuits showing its competition compared to other existing tools.     

High-Speed Si-Bipolar and GaAs Technologies

Improvements in the design and fabrication of the basic transistor devices and improvements in circuit layout and design techniques have dramatically increased the performance of high-speed bipolar integrated circuits. Refinement of standard processes like lithography and the introduction of new processes such as low-pressure epitaxy and dry-etching techniques have largely contributed to the advancement of the device technology. GaAs int&égrated circuit technologies have rapidly developed over the last few years so that both analog and digital integrated circuits are now commercially available. These circuits all use the GaAs MESFET as the basic switching or modulating transistor. Integrated circuits based on more sophisticated heterostructure components, such as the heterojunction bipolar transistor or the modulation doped FET, are currently being developed. This paper will try to give an overview of present state of the art high-speed silicon bipolar technology and compare it to competing GaAs technologies. The most recent advances in oxide isolation technology which have led to the availability of 2.6 GHz dividers and the trend to self-aligned processes which can be used to achieve even smaller geometries will be described. On the GaAs side, the various GaAs-MESFET logic technologies and the heterojunction transistor technologies will be looked at regarding their present status and what can be expected in the near future. Most of the data will relate to monolithically integrated frequency dividers where a requirement for higher input frequencies combined with low power consumption exists.     

CAD techniques for microwave circuits

In little more than 10 years computer-aided design (CAD) of microwave circuits has moved from dumb terminals on mainframe computers to PCs, and now to powerful RISC workstations. Commercial CAD software now integrates the various stages of microwave circuit design: schematic capture, simulation and layout. This paper reviews the different CAD packages that are available for microwave circuit design. The basic principles employed in the modelling of microstrip circuits are introduced and the reasons for the extensive use of frequency-domain simulations are explored. The developments in nonlinear, electromagnetic and system-level simulation methods are described     

A Signal-Flow Driven Automatic Physical Synthesis Methodology for Analog Circuits

This paper introduces a novel automatic physical synthesis methodology for analog circuits based on the signal-flow analysis.Circuit analysis sub-system adopts the newly advanced methodology,circuit topology analysis,and circuit sensitivity analysis to generate layout constraints and control performance degradations.Considering the heuristic information about signalflow，complexity of the methodology is less than the pure performance-driven methodology.And then these constraints are implemented in device generation,placement，and routing sub-systems separately,which makes the different constraints be satisfied at most easily implemented stages.Excellent circuit performance obtained by the methodology is demonstrated by practical circuit examples.     

信号流驱动的模拟电路版图综合方法

提出了一种新的基于信号流分析的模拟电路版图综合方法.电路分析子系统采用新提出的信号流分析方法再结合已有的电路拓扑分析和电路灵敏性分析方法生成布图约束控制电路性能的衰减.由于考虑了电路中有关信号流的启发式信息,该方法的复杂性较一般的纯粹性能驱动方法小.然后分别在器件生成子系统、布图子系统和布线子系统中实现这些约束,使得这些约束在最容易实现的阶段得到满足.实际的电路例子已经证明了这一方法可以获得出色的电路性能.     

ALGA: Automated layout generator for analog CMOS circuits

A computer-aided design (CAD) system called ALGA for an analog circuit layout is presented. The main contribution of this paper is to construct a weight graph that represents the topological connectivity of a given analog circuit. By using the weight graph, some efficient techniques can be designed to avoid devices mismatch and place all devices according to the device size constraints. Moreover, an algorithm is presented to perform the device placement step and propose an effective approach to reduce noise coupling in the routing step. A design method has been implemented in several Complementary Metal Oxide Semiconductor (CMOS) analog circuits. It is seen that the proposed system can generate good analog circuit design.     

两种新型无源OLED显示列驱动电路的研究与设计

针对两种采用不同灰度调制方式和预充方法的新型无源OLED显示列驱动电路进行研究和设计。阐述了脉冲宽度调制和脉冲幅度调制两种灰度显示方式的一致性,提出相对应两种灰度调制方式的列驱动电路,从电路设计到版图实现上比较了这两种电路。阐述了电压和电流两种预充方式,设计出两种新型预充方法,并且应用到OLED显示驱动芯片中。Hspice仿真和版图实现后表明,两种列驱动电路中前者的版图面积约是后者的1/2,采用省电模式预充方法的后者的功耗约是前者的1/3。     

带寄生及匹配约束的CMOS模拟电路模块的STACK生成优化方法

模拟电路的性能紧密依赖于版图的寄生参数和匹配特性 .提出了用以描述分布式的寄生电容和由于工艺梯度变化而产生的寄生参数不匹配以及 STACK内连线的不匹配的模型 .基于该模型 ,一种新的 STACK生成方法用来控制版图的寄生参数和匹配特性 ,优化 STACK的形状和确保为所给出的模拟电路模块生成相映的欧拉图 .一个 OPA电路的例子说明了所提出的版图优化方法可以提高诸如单位增益带宽和相位余量等电路性能     

带寄生及匹配约束的CMOS模拟电路模块的STACK生成优化方法

模拟电路的性能紧密依赖于版图的寄生参数和匹配特性．提出了用以描述分布式的寄生电容和由于工艺梯度变化而产生的寄生参数不匹配以及STACK内连线的不匹配的模型．基于该模型,一种新的STACK生成方法用来控制版图的寄生参数和匹配特性,优化STACK的形状和确保为所给出的模拟电路模块生成相映的欧拉图．一个OPA电路的例子说明了所提出的版图优化方法可以提高诸如单位增益带宽和相位余量等电路性能．     

模拟电路阵列及其半定制专用集成电路实现

与门海数字电路阵列相类似 ,模拟电路阵列也是半定制集成电路设计的母体形式的一种。首先介绍了母体单元结构布局 ,然后描述了其电路的实现。在以上模拟电路阵列母体上 ,成功地实现了很多专用的模拟电路     

Compact $$3\times 3$$ wavelength routing for photonic integrated circuits

Photonic integrated circuits are the future of optical communication networks. The demand for high bandwidth has added a remarkable increase in the capacity of transmission and routing techniques for optical networks. With massive growth in photonic integrated circuits, communication within them (PIC) is an area that needs to be explored and addressed. The signal path between different components in the circuit has to be established for an optimal path with high transmission efficiency. This could be achieved using routers. With this being the intention, this paper proceeds with a design of two \(3\,\times \,3\) optical passive wavelength routers using photonic crystal ring resonators. The designed router connects three transmitters to three receivers with desired characteristics such as low crosstalk, less propagation delay, low insertion loss and can be easily fabricated because of its less complex design. The routers are designed to operate in third transmission window wavelength with basic building blocks of \(1\,\times \,2\) routers. The designed layout of routers exhibits good performance which can be used for all optical communication networks and has a good technological compatibility for chip level integration in PIC. The layout is simulated using finite difference time domain and plane wave expansion methods.     

Architectural Design Issues in a Clockless 32‐Bit Processor Using an Asynchronous HDL

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart.     

多TDI CCD拼接遥感相机异速成像抗干扰设计

多TDI CCD拼接相机在异速工作模式下,不同通道的CCD图像间会存在相互干扰现象,不同行频差会在图像上产生不同斜率、不同宽度的干扰斜条纹。为了解决此问题,文中对原设计电路系统进行了详细分析和优化设计。首先,从异速时序在不同行周期的相位差别上进行分析,异速模式下不同CCD成像电路时序间存在行频差异,导致各个行周期内CCD个别像元上与其他像元叠加的干扰不一致,是干扰斜条纹产生的原因。然后,采取优化关键信号布线方式、系统地和电源布置、去耦电容接地方式等多方面对电路系统进行了改进,优化多TDI CCD成像系统电路抗异速干扰设计。最后,对改进后的电路系统进行测试,去除干扰斜纹,并将图像均方根噪声水平由21.5 mV降低到4.2 mV。结果表明:采用抗干扰技术,有效地去除了通道间干扰斜纹,提高了图像质量。     

PCB设计中的电磁兼容性

在设计电子产品时,除了满足特定的功能要求外,还必须考虑产品的电磁兼容性,这对产品的质量和性能技术指标起着非常关键的作用。介绍了电磁兼容性的基本概念、设计技术以及一些常用的解决电磁兼容性问题的措施,重点就印制电路板设计中的板层设置和元器件布局进行详细说明。     

MASHER: An automatic VLSI layout system

This paper describes a system for the automatic layout of VLSI circuits designed using Path Programmable Logic (PPL) methodology. A formal model has been developed which serves as a framework for the manipulation of PPL circuits. This model supports two basic operations: wire folding and wire splitting. User specified constraints guide the PPL layout process. External wires, those which reach outside of the circuit, may be routed to a particular edge, ordered, or placed adjacently. Heuristics are used to select folds. A heuristic has been developed which chooses those folds which place the fewest restrictions on the circuit. The MASHER system has been fully implemented and a number of real circuits have been laid out. Examples are presented comparing MASHER layouts with both hand layouts and other computer generated layouts.     

Applications of asynchronous circuits

A comparison with synchronous circuits suggests four opportunities for the application of asynchronous circuits: high performance, low power; improved noise and electromagnetic compatibility (EMC) properties, and a natural match with heterogeneous system timing. In this overview paper each opportunity is reviewed in some detail, illustrated by examples, compared with synchronous alternatives, and accompanied by numerous pointers to the literature. Conditions for applying asynchronous circuit technology, such as the existence and availability of computer-aided design (CAD) tools, circuit libraries, and effective test approaches, are discussed briefly. Asynchronous circuits do offer advantages for many applications, and their design methods and tools are now starting to become mature     

An effective thermal circuit model for electro-thermal simulation of SOI analog circuits

A physics-based thermal circuit model is developed for electro-thermal simulation of SOI analog circuits. The circuit model integrates a non-isothermal device thermal circuit with interconnect thermal networks and is validated with high accuracy against finite element simulations in different layout structures. The non-isothermal circuit model is implemented in BSIMSOI to account for self-heating effect (SHE) in a Spice simulator, and applied to electro-thermal simulation of an SOI cascode current mirror constructed using different layouts. Effects of layout design on electric and thermal behaviors are investigated in detail. Influences of BOX thickness are also examined. It has been shown that the proposed non-isothermal approach is able to effectively account for influences of layout design, self-heating, high temperature gradients along the islands, interconnect temperature distributions, thermal coupling, and heat losses via BOX and interconnects, etc., in SOI current mirror structures. The model provides basic concepts and thermal circuits that can be extended to develop an effective model for electro-thermal simulation of SOI analog ICs.