Analysis of traps effect on AlGaN/GaN HEMT by luminescence techniques

The study is carried out on AlGaN/GaN HEMTs presenting current collapse effect at V_ds lower than 6 V. This effect is completely recovered by illuminating the component with light of 710 nm wavelength (1.75 eV). The spectral analysis of the light emission in the visible near infrared spectrum shows a bell-shape with superimposed distinct emission peaks. These features suggest that the electroluminescence (EL) signal is due to the direct intraband of electrons and inelastic intraband transition of electrons due to scattering by charged centres. Photoionisation experiments have been conducted to determine the light wavelengths/energies that separately change the drain current and the gate leakage current.     

A 24 W Ku band GaN based power amplifier with 9.1 dB linear gain

A Ku-band power amplifier is successfully developed with a single chip 4.8 mm AlGaN/GaN high electron mobility transistors (HEMTs). The AlGaN/GaN HEMTs device, achieved by E-beam lithography г-gate process, exhibited a gate-drain reverse breakdown voltage of larger than 100 V, a cutoff frequency of f_T=30 GHz and a maximum available gain of 13 dB at 14 GHz. The pulsed condition (100 μs pulse period and 10% duty cycle) was used to test the power characteristic of the power amplifier. At the frequency of 13.9 GHz, the developed GaN HEMTs power amplifier delivers a 43.8 dBm (24 W) saturated output power with 9.1 dB linear gain and 34.6% maximum power-added efficiency (PAE) with a drain voltage of 30 V. To our best knowledge, it is the state-of-the-art result ever reported for internal-matched 4.8 mm single chip GaN HEMTs power amplifier at Ku-band.     

Field- and current-driven degradation of GaN-based power HEMTs with p-GaN gate: Dependence on Mg-doping level

Within this paper we investigate the degradation of GaN-HEMTs with p-GaN gate submitted to stress at forward gate bias. We studied the effect of both constant-voltage stress and short-pulse stress (induced by TLP, Transmission Line Pulser); devices having three different Mg-doping levels (ranging from 2.1 · 10¹⁹/cm³ to 2.9 · 10¹⁹/cm³) were used for the study.We demonstrated the existence of two different degradation mechanisms, depending on the stress conditions: (i) when submitted to TLP stress (100 ns pulses with increasing amplitude), the failure occurs through a field-driven process, i.e. the breakdown of the metal/p-GaN Schottky junction, which is reversely biased when the gate is at positive voltage. Failure voltage decreases with increasing Mg doping, since higher acceptor levels result in a higher electric field. (ii) Conversely, during constant-voltage stress, the long-term stability is undermined by a current-driven process, namely the accumulation of positive charges at the p-GaN/AlGaN interface, which promotes an increase of the leakage current, first gradual and then catastrophic. Increasing Mg-concentration in the p-GaN results in a reduction of the gate leakage at high forward gate bias. As a consequence, devices with higher Mg doping have long TTF (more than two orders of magnitude with respect to the samples with lower Mg doping).     

Electron transport in passivated AlGaN/GaN/Si HEMTs

AlGaN/GaN/Si high electron mobility transistors (HEMTs) grown by molecular beam epitaxy are investigated using direct-current and radio-frequency measurements. As has been found, the maximum of drain current achieves 881 mA/mm with an extrinsic current gain cutoff frequency of 37 GHz for a 0.25 µm gate length. Pulsed characteristics also showed a reduction of trapping centers that improves the quality of the epilayers.     

Study on mobility enhancement in MOVPE-grown AlGaN/AlN/GaN HEMT structures using a thin AlN interfacial layer

Al_0.26Ga_0.74N/AlN/GaN high-electron-mobility transistor (HEMT) structures with AlN interfacial layers of various thicknesses were grown on 100-mm-diameter sapphire substrates by metalorganic vapor phase epitaxy, and their structural and electrical properties were characterized. A sample with an optimum AlN layer thickness of 1.0 nm showed a highly enhanced Hall mobility (μ_Hall) of 1770 cm²/Vs with a low sheet resistance (ρ_s) of 365 Ω/sq. (2DEG density n_s = 1.0 × 10¹³/cm²) at room temperature compared with those of a sample without the AlN interfacial layer (μ_Hall = 1287 cm²/Vs, ρ_s = 539 Ω/sq., and n_s = 0.9 × 10¹³/cm²). Electron transport properties in AlGaN/AlN/GaN structures were theoretically studied, and the calculated results indicated that the insertion of an AlN layer into the AlGaN/GaN heterointerface can significantly enhance the 2DEG mobility due to the reduction of alloy disorder scattering. HEMTs were successfully fabricated and characterized. It was confirmed that AlGaN/AlN/GaN HEMTs with the optimum AlN layer thickness show superior DC properties compared with conventional AlGaN/GaN HEMTs.     

Reliability of 100 nm AlGaN/GaN HEMTs for mm-wave applications

The effect of gate metallization and gate shape on the reliability and RF performance of 100 nm AlGaN/GaN HEMTs on SiC substrate for mm-wave applications has been investigated under on-state DC-stress tests. By replacing the gate metallization from NiPtAu to PtAu the median time to failure at T_ch = 209 °C can be improved from 10 h to more than 1000 h. Replacing the PtAu T-gate by a spacer gate further reduces the degradation rate under on-state stress, but decreases the current-gain cut-off frequency from 75 GHz to 50 GHz. Physical failure analysis using electroluminescence and TEM cross-section revealed pit and Ni void formation at the gate foot as the main degradation mechanisms of devices with NiPtAu T-gate. High resolution EDX mapping of stressed devices indicates that the formation of pits is caused by a local aluminium oxidation process. Simulation of the stress induced changes of the input characteristics of devices with NiPtAu gate further proves the formation of pits and Ni voids.     

Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process

The breakdown failure mechanisms for a family of power AlGaN/GaN HEMTs were studied. These devices were fabricated using a commercially available MMIC/RF technology with a semi-insulating SiC substrate. After a 10 min thermal annealing at 425 K, the transistors were subjected to temperature dependent electrical characteristics measurement. Breakdown degradation with a negative temperature coefficient of ?0.113 V/K for the devices without field plate was found. The breakdown voltage is also found to be a decreasing function of the gate length. Gate current increases simultaneously with the drain current during the drain-voltage stress test. This suggests that the probability of a direct leakage current path from gate to the 2-DEG region. The leakage current is attributed by a combination of native and generated traps/defects dominated gate tunneling, and hot electrons injected from the gate to channel. Devices with field plate show an improvement in breakdown voltage from ～40 V (with no field plate) to 138 V and with lower negative temperature coefficient. A temperature coefficient of ?0.065 V/K was observed for devices with a field plate length of 1.6 μm.     

Field and hot electron-induced degradation in GaN-based power MIS-HEMTs

We investigate the degradation of AlGaN/GaN MIS-HEMTs submitted to gate step-stress experiments, and demonstrate the existence of field- and hot-electron induced processes. When the devices are submitted to gate-step stress with high V_DS > 50 V, four different regimes are identified: (i) for V_GS < − 10 V, no significant degradation is observed, since the devices are in the off-state; (ii) for − 10 V < V_GS < 0 V, hot electrons flow through the channel, as demonstrated by the (measurable) electroluminescence signal. These hot electrons can be trapped within device structure, inducing an increase in the threshold voltage. (iii) for V_GS > 0 V, the density of hot electrons is significantly reduced, due to the increased interface scattering and device temperature. As a consequence, EL signal drops to zero, and the electrons trapped during phase (ii) are de-trapped back to the channel, where they are attracted by the high 2DEG potential. (iv) Finally, for V_GS > 5 V, a significant increase in threshold voltage is detected. This effect is observed only for high positive voltages, i.e. when a significant leakage current flows through the gate. Such gradual degradation is ascribed to the injection of electrons from the 2DEG to the gate insulator, which is a field-driven effect. These results were obtained by combined electrical and optical characterization carried out at different voltages during the step stress.     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

The role of surface barrier oxidation on AlGaN/GaN HEMTs reliability

Reliability of AlGaN/GaN HEMTs processed with different surface oxidation levels was studied using electrical and optical methods. It was found that HEMTs with more surface oxide content are more susceptible to degradation in terms of gate leakage and trapping characteristics, although this oxide layer initially passivates surface traps. In the degraded devices, trap level with activation energy of 0.45–0.47 eV was observed and attributed to surface related traps. This indicates that oxygen may play a crucial role for AlGaN/GaN HEMT reliability.     

GaN-based HEMTs tested under high temperature storage test

In this work, the impact of 1000 h thermal storage test at 325 °C on the performance of gallium nitride high electron mobility transistors grown on Si substrates (GaN-on-Si HEMTs) is investigated. The extensive DC- and pulse-characterization performed before, during and after the stress did not reveal degradation on the channel conduction properties as well as formation of additional trapping states. The failure investigation has shown that only the gate and drain leakage currents were strongly affected by the high temperature storage test. The physical failure analysis revealed a Au inter-diffusion phenomenon with Ni at the gate level, resulting in a worsening of the gate–AlGaN interface. It is speculated that this phenomenon is at the origin of the gate and drain leakage current increasing.     

La2O3 gate dielectrics for AlGaN/GaN HEMT

The annealing temperature dependent electrical characteristics of La₂O₃ gate dielectrics for W gated AlGaN/GaN high electron mobility transistors (HEMTs) have been characterized. The threshold voltage (V_th) has been found to shift to positive direction with higher temperature annealing, exceeding those of Schottky HEMTs, presumably attributed to the presence of negative fixed charges at the interface between La₂O₃ and AlGaN layers. At a high temperature annealing over 500 °C, a high dielectric constant (k-value) of 27 has been achieved with poly-crystallization of the La₂O₃ film, which is useful to limit the reduction in gate capacitance. A high k-value for La₂O₃ gate dielectrics and the presence of negative charges at the interface are attractive for AlGaN/GaN HEMTs with low gate leakage and normally-off operation.     

Device characteristics of AlGaN/GaN MIS–HEMTs with high-k HfxZr1−xO2 (x = 0.66, 0.47, 0.15) insulator layer

This study investigates the characteristics of AlGaN/GaN MIS–HEMTs with Hf_xZr_1−xO₂ (x = 0.66, 0.47, and 0.15) high-k films as gate dielectrics. Sputtered Hf_xZr_1−xO₂ with a dielectric constant of 20–30 and a bandgap of 5.2–5.71 eV was produced. By increasing the Zr content of HfZrO₂, the V_TH shifted from −1.8 V to −1.1 V. The highest Hf content at this study reduced the gate leakage by approximately one order of magnitude below that of those Zr-dominated HFETs. The maximum I_DS currents were 474 mA/mm, 542 mA/mm, and 330 mA/mm for Hf content of 66%, 47%, 15% at V_GS = 3 V, respectively.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

New degradation mechanism observed for AlGaN/GaN HEMTs with sub 100 nm scale unpassivated regions around the gate periphery

AlGaN/GaN HEMTs with low gate leakage current in the μA/mm range have been fabricated with a small-unpassivated region close to the gate foot. They showed considerably higher critical voltage values (average VCR = 60 V) if subjected to step stress testing at OFF-state conditions and room temperature as compared to standard devices with conventional gate technology. This is due to the fact that electrons injected from the gate can be accumulated at the unpassivated region and thus builds up negative charge. The lower gate leakage is due to virtual gate formation, which is reducing local electric field in the vicinity of the gate. In contrast to devices with standard gate technology, degradation during step stressing is not associated with a simultaneous gate leakage and drain leakage current increase but with a strong increase of drain current at OFF-state conditions while the gate leakage is practically not affected. Then a relatively higher critical voltage of around 60 V is achieved. An abrupt increase of subthreshold drain current implies the formation of a conductive channel bypassing the gate region without influencing gate leakage. It is believed that hopping conductivity via point defects formed during device stressing creates this channel. Once this degradation mode takes place, the drain current of affected devices significantly drops. This can be explained by negative trap formation in the channel region affecting the total charge balance in 2DEG region. Electroluminescence measurements on both fresh and degraded devices showed no hot spots at OFF-state conditions. However, there is additional emission at ON-state bias, which suggests additional energetic states that lead to radiative electron transition effects in the degraded devices, most possibly defect states in the buffer.     

Effects of post-annealing on the passivation interface characteristics of AlGaN/GaN high electron mobility transistors

We examined the effects of post-annealing in forming-gas ambient on the spin-on-dielectric (SOD)-buffered passivation as well as the conventional plasma-enhanced chemical vapor deposition (PECVD) Si₃N₄ passivation structure in association with the quantitative analysis of defects at the passivation interfaces of AlGaN/GaN high electron mobility transistors (HEMTs). Before the annealing, the interface state densities (D_it) of the PECVD Si₃N₄ are one-order higher (10¹²–10¹³ cm⁻² eV⁻¹) than those of the SOD SiO_x (10¹¹–10¹² cm⁻² eV⁻¹) as derived from C–V characterization. Clear reduction in D_it from the PECVD Si₃N₄ is extracted to a level of 10¹¹–10¹² cm⁻² eV⁻¹ with a stronger absorption from Si–N peak in Fourier transform infrared spectroscopy spectra after the post-annealing. On the other hand, negligible difference in D_it value is obtained from the SOD SiO_x. In this paper we propose that much lower measurement levels (~156 mA/mm) before the annealing and substantial recovery (~13% increase) after the annealing in maximum drain current density of the AlGaN/GaN HEMTs with Si₃N₄ passivations are due to the original higher density before the annealing and greater reduction in D_it of the PECVD Si₃N₄ after the annealing. Significant reduction after the annealing in gate–drain leakage current (from ~10⁻³ to ~10⁻⁵ A, 100-μm gate width) of the HEMTs with the Si₃N₄ passivation is also supposed to be attributed to the reduction of D_it.     

Similarities of lag phenomena and current collapse in field-plate AlGaN/GaN HEMTs with different types of buffer layers

We make a two-dimensional transient analysis of field-plate AlGaN/GaN high electron mobility transistors (HEMTs) with a Fe-doped semi-insulating buffer layer, which is modeled that as deep levels, only a deep acceptor located above the midgap is included (E_C − E_DA = 0.5 eV, E_C: energy level at the bottom of conduction band, E_DA: deep acceptor's energy level). And the results are compared with a case having an undoped semi-insulating buffer layer in which a deep donor above the midgap (E_C − E_DD = 0.5 eV. E_DD: the deep donor's energy level) is considered to compensate a deep acceptor below the midgap (E_DA − E_V = 0.6 eV, E_V: energy level at the top of valence band). It is shown that the drain-current responses when the drain voltage is lowered abruptly are reproduced quite similarly between the two cases with different types of buffer layers, although the time region where the slow current transients occur is a little different. The lags and current collapse are reduced by introducing a field plate. This reduction in lags and current collapse occurs because the deep acceptor's electron trapping is reduced under the gate region in the buffer layer. The dependence of drain lag, gate lag and current collapse on the field-plate length and the SiN layer thickness is also studied, indicating that the rates of drain lag, gate lag and current collapse are quantitatively quite similar between the two cases with different types of buffer layers when the deep-acceptor densities are the same.     

Ultraviolet photoresponse of ZnO nanostructured AlGaN/GaN HEMTs

We present the first active visible blind ultraviolet (UV) photodetector based on zinc oxide (ZnO) nanostructured AlGaN/GaN high electron mobility transistors (HEMTs). The ZnO nanorods (NRs) are selectively grown on the gate area by using hydrothermal method. It is shown that ZnO nanorod (NR)-gated UV detectors exhibit much superior performance in terms of response speed and recovery time to those of seed-layer-gated detectors. It is also found that the best response speed (~10 and~190 ms) and responsivity (~1.1×10⁵ A/W) were observed from detectors of the shortest gate length of 2 µm among our NR-gated devices of three different gate dimensions, and this responsivity is about one order higher than the best performance of ZnO NR-based UV detectors reported to date.     

Silicon on insulator avalanche-impact-ionization transistor with very low switching voltage from ON state to OFF state

A transistor with ON/OFF switching voltage much lower than the theoretical limit of conventional FETs is demonstrated. The basic concept is to use the gate-induced modulation of the longitudinal component of the electric field directly in the drain p–n⁺ junction of a thin film SOI FET. This modulation enables the gate to remarkably control the avalanche-impact-ionization of electrons and holes in the junction. Experimental results and a theoretical model are presented. The strong dependence of avalanche-impact-ionization current on the electric field intensity results in an extremely low switching voltage (6 mV/decade at 300 K).