Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer

Using nanometer-resolution characterization techniques, we present a study of the local structural and electrical properties of grain boundaries (GBs) in polycrystalline high-κ (HK) dielectric and their role on the reliability of underlying interfacial layer (IL). A detailed understanding of this analysis requires characterization of HK/IL dielectrics with nanometer scale resolution. In this work, we present the impact of surface roughness, thickness and GBs containing high density of defects, in polycrystalline HfO₂ dielectric on the performance of underlying SiO_x (x ⩽ 2) IL using atomic force microscopy and simulation (device and statistical) results. Our results show SiO_x IL beneath the GBs and thinner HfO₂ dielectric experiences enhanced electric field and is likely to trigger the breakdown of the SiO_x IL.     

32 × 32 Crossbar Array Resistive Memory Composed of a Stacked Schottky Diode and Unipolar Resistive Memory

Various array types of 1‐diode and 1‐resistor stacked crossbar array (1D1R CA) devices composed of a Schottky diode (SD) (Pt/TiO₂/Ti/Pt) and a resistive switching (RS) memory cell (Pt/TiO₂/Pt) are fabricated and their performances are investigated. The unit cell of the 1D1R CA device shows high RS resistance ratio (≈10³ at 1.5 V) between low and high resistance state (LRS and HRS), and high rectification ratio (≈10⁵) between LRS and reverse‐state SD. It also shows a short RS time of <50 ns for SET (resistance transition from HRS to LRS), and ≈600 ns for RESET (resistance transition from LRS to HRS), as well as stable RS endurance and data retention characteristics. It is experimentally confirmed that the selected unit cell in HRS (logically the “off” state) is stably readable when it is surrounded by unselected LRS (logically the “on” state) cells, in an array of up to 32 × 32 cells. The SD, as a highly non‐linear resistor, appropriately controls the conducting path formation during the switching and protects the memory element from the noise during retention.     

Temperature-dependent resistive switching characteristics for Au/n-type CuAlOx/heavily doped p-type Si devices

Bipolar switching phenomenon is found for Au/n-type CuAlO_x/heavily doped p-type Si devices at temperatures above 220 K. For high or low resistive states (HRS or LRS), the electrical resistance is decreased with increasing temperature, indicating a semiconducting behavior. Carrier transport at LRS or HRS is dominated by hopping conduction. It is reasonable to conclude that the transition from HRS to LRS due to the migration of oxygen vacancies (V_O) is associated with electron hopping mediated through the V_O trap sites. The disappearance of the resistive switching behavior below 220 K is attributed to the immobile V_O traps. The deep understanding of conduction mechanism could help to control the device performance.     

Thickness effect on the bipolar switching mechanism for nonvolatile resistive memory devices based on CeO2 thin films

Impact of switching layer thickness on the bipolar resistive memory performance, stability and uniformity has been investigated in Ti/CeO₂/Pt devices. XRD and FTIR analyses demonstrate polycrystalline nature of CeO₂ films and the formation of a TiO interface layer. The bipolar switching characteristics like HRS and LRS dispersion are found to be dependent on the thickness of CeO₂ layer. As it is noted that forming as well as SET voltages gradually increase with increasing CeO₂ layer thickness however RESET voltages are slightly affected. Oxygen gettering ability of Ti causes the formation of TiO layer, which not only extracts oxygen ions from the ceria film but also acts as ion reservoir, hence plays a key role in stable functioning of the memory devices. Current transport behavior is based upon Ohmic and interface modified space charge limited conduction. Based on unique distribution characteristics of oxygen vacancies in CeO₂ films, a possible mechanism of resistive switching in CeO₂ RRAM devices has been discussed.     

Control of Switching Modes and Conductance Quantization in Oxygen Engineered HfOx based Memristive Devices

Hafnium oxide (HfO_x)‐based memristive devices have tremendous potential as nonvolatile resistive random access memory (RRAM) and in neuromorphic electronics. Despite its seemingly simple two‐terminal structure, a myriad of RRAM devices reported in the rapidly growing literature exhibit rather complex resistive switching behaviors. Using Pt/HfO_x/TiN‐based metal–insulator–metal structures as model systems, it is shown that a well‐controlled oxygen stoichiometry governs the filament formation and the occurrence of multiple switching modes. The oxygen vacancy concentration is found to be the key factor in manipulating the balance between electric field and Joule heating during formation, rupture (reset), and reformation (set) of the conductive filaments in the dielectric. In addition, the engineering of oxygen vacancies stabilizes atomic size filament constrictions exhibiting integer and half‐integer conductance quantization at room temperature during set and reset. Identifying the materials conditions of different switching modes and conductance quantization contributes to a unified switching model correlating structural and functional properties of RRAM materials. The possibility to engineer the oxygen stoichiometry in HfO_x will allow creating quantum point contacts with multiple conductance quanta as a first step toward multilevel memristive quantum devices.     

Experimental evidence of suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation

Experimental evidence of suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation is provided by using modified charge-pumping (CP) techniques. The original distribution of interface traps and bulk traps of pure HfO₂ and HfO₂/LaOx dielectric stack are extracted and compared by CP techniques. It is found that devices with HfO₂/LaOx dielectric stack have higher interface trap but lower bulk trap density than those with pure HfO₂. Especially, device with HfO₂/LaOx dielectric stack is highly resistant to constant voltage stress, which can be attributed to the suppression on oxygen vacancy formation in Hf based high-κ gate dielectrics with La incorporation.     

High‐Mobility ZnO Thin Film Transistors Based on Solution‐processed Hafnium Oxide Gate Dielectrics

The properties of metal oxides with high dielectric constant (k) are being extensively studied for use as gate dielectric alternatives to silicon dioxide (SiO₂). Despite their attractive properties, these high‐k dielectrics are usually manufactured using costly vacuum‐based techniques. In that respect, recent research has been focused on the development of alternative deposition methods based on solution‐processable metal oxides. Here, the application of the spray pyrolysis (SP) technique for processing high‐quality hafnium oxide (HfO₂) gate dielectrics and their implementation in thin film transistors employing spray‐coated zinc oxide (ZnO) semiconducting channels are reported. The films are studied by means of admittance spectroscopy, atomic force microscopy, X‐ray diffraction, UV–Visible absorption spectroscopy, FTIR, spectroscopic ellipsometry, and field‐effect measurements. Analyses reveal polycrystalline HfO₂ layers of monoclinic structure that exhibit wide band gap (≈5.7 eV), low roughness (≈0.8 nm), high dielectric constant (k ≈ 18.8), and high breakdown voltage (≈2.7 MV/cm). Thin film transistors based on HfO₂/ZnO stacks exhibit excellent electron transport characteristics with low operating voltages (≈6 V), high on/off current modulation ratio (～10⁷) and electron mobility in excess of 40 cm² V^?1 s^?1.     

A Review on Dielectric Breakdown in Thin Dielectrics: Silicon Dioxide,High‐k,and Layered Dielectrics

Thin dielectric films are essential components of most micro‐ and nanoelectronic devices, and they have played a key role in the huge development that the semiconductor industry has experienced during the last 50 years. Guaranteeing the reliability of thin dielectric films has become more challenging, in light of strong demand from the market for improved performance in electronic devices. The degradation and breakdown of thin dielectrics under normal device operation has an enormous technological importance and thus it is widely investigated in traditional dielectrics (e.g., SiO₂, HfO₂, and Al₂O₃), and it should be further investigated in novel dielectric materials that might be used in future devices (e.g., layered dielectrics). Understanding not only the physical phenomena behind dielectric breakdown but also its statistics is crucial to ensure the reliability of modern and future electronic devices, and it can also be cleverly used for other applications, such as the fabrication of new‐concept resistive switching devices (e.g., nonvolatile memories and electronic synapses). Here, the fundamentals of the dielectric breakdown phenomenon in traditional and future thin dielectrics are revised. The physical phenomena that trigger the onset, structural damage, breakdown statistics, device reliability, technological implications, and perspectives are described.     

Resistive switching characteristics of MIM structures based on oxygen-variable ultra-thin HfO2 and fabricated at low temperature

We report the resistive switching characteristics of Metal-Insulator-Metal (MIM) structures fabricated at low temperature and having different concentrations of oxygen vacancies in the insulator. The oxygen modulation in HfO₂ is promoted by a very simple variation of standard thermal Atomic-Layer Deposition (ALD), so that different exposure times to H₂O during each half-cycle of the hafnium oxide deposition are used (being Tetrakis Dimethylamino Hafnium–TDMAH the other precursor). We show the correlation of the stoichiometry with the forming voltage, conduction mechanisms and resistance windows of memory devices. All structures present a bipolar operation mode in which the resistive switching mechanism is related to the migration of oxygen vacancies inside the dielectric. These MIM devices have a simple structure, low power consumption and they are fabricated using a very low thermal budget of only 250 °C, thus enabling their integration at the Back-End of Line (BEOL) stage of an integrated circuit in order to increase the density of memory arrays in at least one order of magnitude.     

Resistance change in memory structures integrating CuTCNQ nanowires grown on dedicated HfO2 switching layer

The present paper deals with the bipolar resistive switching of memory elements based on metal-organic complex CuTCNQ (copper-7,7’,8,8’-tetracyanoquinodimethane) nanowires grown on a dedicated HfO₂ oxide switching layer. Switching characteristics are explored either at millimeter scale on pad-size devices or at nanoscale by using conductive atomic force microscopy. Whatever the investigation scales, the basic memory characteristics appear to be controlled by copper ionic transport within a switching layer. This latter corresponds to either HfO₂ layer in pad-size devices or nanogap formed at nanoscale between the atomic force microscopy conductive tip and CuTCNQ surface. Depending upon the observation scale, the switching layer (either HfO₂ oxide or nanogap) acts as a matrix in which copper conductive bridges are formed and dissolved thanks to redox processes controlled in alternating applied bias voltages.     

Effect of sweeping voltage and compliance current on bipolar resistive switching and white-light controlled Schottky behavior in epitaxial BaTiO3 (111) thin films

Bipolar resistive switching (RS) phenomenon without required electroforming has been observed in epitaxial (111)-oriented BaTiO₃ (BTO) thin films deposited by PLD technique on conducting Nb-doped substrate of SrTiO₃ (NSTO). Negative differential resistance (NDR) is observed at about −5 V when the maximum of positive voltage exceeds 7 V and the compliance current is more than 1.5 mA. And bipolar resistive switching has also been observed. In addition, the resistance of LRS decreases with increasing compliance current or the maximum of positive voltage while that of HRS barely changes, and the resistance of HRS increases with increasing the absolute of maximum of negative voltage while that of LRS scarcely changes. A typical rectifying behavior is observed when the maximum of positive voltage is less than 4 V (such as 2 V). In this case, the reverse biased current is strongly enhanced under illumination of white-light, and vice versa. The resistance of LRS and HRS can be controlled by the applied voltage or the compliance current. The rectifying behavior can be controlled by the white-light. The transition from rectifying behavior to bipolar resistive switching can be controlled by the applied voltage. The above results were discussed by considering the oxygen vacancies that can trap or release electrons as a trapping layer at the Pt/BTO interface.     

Bipolar Ni/ZnO/HfO2/Ni RRAM with multilevel characteristic by different reset bias

The authors report the fabrication and characterization of resistive random access memory (RRAM) with Ni/ZnO/HfO₂/Ni structure at room temperature. It was found that the proposed device exhibited bipolar switching behavior with multilevel characteristics in a reset process. It was found that the device exhibited two-step reset stage under high reset bias. By applying a 2nd reset stage after the transformation of the 1st reset stage, it was found that the RRAM could return to the initial state. From I–V curves measured in these two reset stages, it was found that the current conduction was dominated by Schottky emission due to the migration of oxygen ions and recombination with oxygen vacancies. This reaction could break the conducting filament so as to transform carrier transport mechanism to Schottky emission. This also results in the simultaneous transformation from low resistance state (LRS) to high resistance state (HRS).     

Intrinsic bonding defects in transition metal elemental oxides

Gate dielectrics comprised of nanocrystalline HfO₂ in gate stacks with thin SiO₂/SiON interfacial transition regions display significant asymmetries with respect to trapping of Si substrate injected holes and electrons. Based on spectroscopic studies, and guided by ab initio theory, electron and hole traps in HfO₂ and other transition metal elemental oxides are assigned to O-atom divacancies, clustered at internal grain boundaries. Three engineering solutions for defect reduction are identified: i) deposition of ultra-thin, <2 nm, HfO₂ dielectric layers, in which grain boundary formation is suppressed by effectively eliminating inter-primitive unit cell π-bonding interactions, ii) chemically phase separated high HfO₂ silicates in which inter-primitive unit cell p-bonding interactions are suppressed by the two nanocrystalline grain size limitations resulting from SiO₂ inclusions, and iii) non-crystalline Zr/Hf Si oxynitrides without grain boundary defects.     

Resistance switching in HfO2-based OxRRAM devices

We have investigated the origins of the resistivity change during the forming of HfO₂ based resistive random access memories. The high and low resistive states of HfO₂ were investigated using electrical measurements, TEM, XPS, and AES. TEM and XPS show that the HfO₂/TiN interface is free from TiO_xN_y oxi-nitride states. Electrical measurements show that voltage threshold magnitude required for the formation of the conductive paths through the HfO₂ layer depends on the polarity. The AES measurements show that HfO₂ and HfO_x or Hf metallic may coexist in the low resistive state.     

Effect of fluorinated silicate glass passivation layer on electrical characteristics and dielectric reliabilities for the HfO2/SiON gate stacked nMOSFET

The superior characteristics of the fluorinated hafnium oxide/oxynitride (HfO₂/SiON) gate dielectric are investigated comprehensively. Fluorine is incorporated into the gate dielectric through fluorinated silicate glass (FSG) passivation layer to form fluorinated HfO₂/SiON dielectric. Fluorine incorporation has been proven to eliminate both bulk and interface trap densities due to Hf-F and Si-F bonds formation, which can strongly reduce trap generation as well as trap-assisted tunneling during subsequently constant voltage stress, and results in improved electrical characteristics and dielectric reliabilities. The results clearly indicate that the fluorinated HfO₂/SiON gate dielectric using FSG passivation layer becomes a feasible technology for future ultrathin gate dielectrics applications.     

Layered (C6H5CH2NH3)2CuBr4 Perovskite for Multilevel Storage Resistive Switching Memory

Although there have been attempts to use non‐lead based halide perovskite materials as insulating layers for resistive switching memory, the ratio of low resistance state (LRS) to high resistance state (HRS) ( = ON/OFF ratio) and/or endurance is reported to be mostly lower than 10³. Resistive switching memory characteristics of layered (BzA)₂CuBr₄ (BzA = C₆H₅CH₂NH₃) perovskite with high ON/OFF ratio and long endurance are reported here. The X‐ray diffraction (XRD) pattern of the deposited (BzA)₂CuBr₄ layer shows highly oriented (00l) planes perpendicular to a Pt substrate. An Ag/PMMA/(BzA)₂CuBr₄/Pt device shows bipolar switching behavior. A forming step at around +0.5 V is observed before the repeated bipolar switching at the SET voltage of +0.2 V and RESET voltage of ‐0.3 V. The ON/OFF ratio as high as =10⁸ is monitored along with an endurance of ≈2000 cycles and retention time over 1000 s. The high ON/OFF ratio enables multilevel storage characteristics as confirmed by changing the compliance currents. Ohmic conduction at the LRS and Schottky emission at HRS are involved in electrochemical metallization process. The bipolar resistive switching property is retained after storing the device at ambient condition under relative humidity of about 50% for 2 weeks, which indicates that (BzA)₂CuBr₄ is stable memory material.     

Dispersion improvement of unipolar resistive switching Ni/CuxO/Cu device by bipolar operation method

Thermally grown Cu_xO thin films were adopted to fabricate a Ni/Cu_xO/Cu structure and investigate its resistive switching properties. The resistance of the device can reversibly switch between the high-resistance-state (HRS) and the low-resistance-state (LRS) by dc voltages. The device with the unipolar switching behavior can be either operated by dc voltages in the same direction (unipolar operation method) or in the opposite directions (bipolar operation method). The switching dispersions when using the bipolar operation method were smaller than those when using the unipolar operation method. This may be attributed to the compensation of defect migration during switching cycles. The switching behaviors of the bipolar operation method and of the unipolar operation method were similar. The conducting filament model with the thermochemical effect was suggested to explain the resistive switching behaviors.     

High-κ dielectric breakdown in nanoscale logic devices – Scientific insight and technology impact

Dielectric breakdown is one of the key failure mechanisms in front-end silicon-based complementary metal oxide semiconductor (CMOS) technology. With the advent of HfO₂-based high-κ dielectrics replacing SiO₂ and metal gate replacing polysilicon and silicides, the physics of defect generation and breakdown of the oxide has changed significantly, although the mechanisms governing operation of the transistor remain essentially the same. Given the progression towards ultra-thin dielectric films with physical thickness ∼1–2 nm, the overall breakdown process has shifted from a single catastrophic hard breakdown (HBD) event to include various regimes such as soft breakdown (SBD) and progressive (post) breakdown (PBD) which in itself consists of a digital phase with random telegraph noise (RTN) fluctuations and stable average leakage current and an analog phase with gradual wear-out and lateral dilation of the percolation path resulting in a monotonic increase in leakage current. In order to better design and optimize the logic gate stack for enhancing its robustness and immunity to breakdown, it is essential to understand the driving forces and physical mechanisms behind the different phases of dielectric failure. This review is dedicated to the scientific understanding of the various regimes of breakdown in high-κ gate stacks using electrical, physical and statistical techniques along with an application of these findings to predict the impact they will have from a technology perspective.     

Reliability and gate conduction variability of HfO2-based MOS devices: A combined nanoscale and device level study

The electrical properties and reliability of MOS devices based on high-k dielectrics can be affected when the gate stack is subjected to an annealing process, which can lead to the polycrystallization of the high-k layer. In this work, a Conductive Atomic Force Microscope (C-AFM) has been used to study the nanoscale electrical conduction and reliability of amorphous and polycrystalline HfO₂ based gate stacks. The link between the nanoscale properties and the reliability and gate conduction variability of fully processed MOS devices has also been investigated.     

Ferroelectricity-modulated resistive switching in Pt/Si:HfO2/HfO2-x/Pt memory

It is investigated for the effect of a ferroelectric Si:HfO₂ thin film on the resistive switching in a stacked Pt/Si:HfO₂/highly-oxygen-deficient HfO_2-x/Pt structure. Improved resistance performance was observed. It was concluded that the observed resistive switching behavior was related to the modulation of the width and height of a depletion barrier in the HfO_2-x layer, which was caused by the Si:HfO₂ ferroelectric polarization field effect. Reliable switching reproducibility and long data retention were observed in these memory cells, suggesting their great potential in non-volatile memories applications with full compatibility and simplicity.