Channel width dependence of NMOSFET hot carrier degradation

The channel width dependence of hot carrier reliability on NMOSFETs from 0.4-/spl mu/m to 0.13-/spl mu/m technology has been studied at both I/sub b,peak/ and V/sub g/ = V/sub d/ conditions. Enhanced degradation on narrow width devices happens on most technologies. The I/sub b//I/sub d/ value and vertical electric field are proposed to be the reasons for enhanced degradation on narrow width NMOSFETs.     

Channel length and width dependence of hot-carrier hardness influorinated MOSFETs

A study of the interface degradation caused by channel-hot-electron (CHE) and substrate-hot-electron (SHE) injection in fluorinated MOSFETs and in unfluorinated control over a wide range of channel lengths and widths is discussed. In all cases, the fluorinated MOSFETs are more resistant to hot-electron-induced interface damage, although the beneficial effect of fluoride becomes less significant for submicrometer devices. For nonfluorinated control devices, a significant gate-size dependence of the transconductance degradation is observed after either CHE or SHE injection. In contrast, the fluorinated devices exhibit almost no gate-length dependence in the range of 0.6-10.0 μm or gate-width dependence in the range of 1.6-10.0 μm after SHE injection, in which the injected hot electrons assume much better areal uniformity than in CHE injection. However, significant gate-size dependence was observed in fluorinated devices after CHE injection, primarily due to the spatial nonuniformity of the CHE damage. The beneficial effect of F and its influence on the gate-size dependence in response to SHE injection may be attributed to the local strain relaxation near the SiO₂/Si interface where F is incorporated in the Si-O network. These results also suggest that the development of local-strain relaxed isolation technology will be important for deep-submicrometer MOSFETs     

Tensile CESL-induced strain dependence on impact ionization efficiency in nMOSFETs

Process-induced strain dependence of impact ionization efficiency (IIE) in nMOSFETs with a tensile contact etch stop layer (CESL) is presented for the first time. From the universal relationship between the IIE and the electric field in the pinch-off region, a difference in the IIE of nMOSFETs between without and with the tensile CESL is found. This result can be mainly attributed to the narrowing effect of the bandgap energy caused by the tensile CESL-induced strain into the channel, i.e., the reduced threshold energy for impact ionization. In addition, the wafer-bending experiments can further provide strong evidence for the bandgap energy narrowing. It means that the IIE measurement could serve as a reliable monitor of the process-induced strain into the channel.     

应变硅电子迁移率解析模型

提出了一个应变硅沟道电子迁移率解析模型.模型以应变张量为对象研究应变硅沟道电子迁移率,因此与工艺相独立;适用于施加双轴应力及<100>/<110>方向单轴应力,沟道方向为<100>/<110>的器件;易于嵌入常用仿真工具中.     

应变硅电子迁移率解析模型

提出了一个应变硅沟道电子迁移率解析模型.模型以应变张量为对象研究应变硅沟道电子迁移率,因此与工艺相独立;适用于施加双轴应力及<100>/<110>方向单轴应力,沟道方向为<100>/<110>的器件;易于嵌入常用仿真工具中.     

Reduced temperature dependence of hot carrier degradation in deuterated nMOSFETs

Deuterated oxides exhibit prolonged hot carrier lifetimes at room temperature. We report evidence that this improved hot carrier hardness exists over the temperature range between −25 °C and 200 °C. However, the benefit of deuterium incorporation deceases with increasing stress temperature. Furthermore the V_T-shift shows a remarkable absence of temperature dependence for the deuterated samples. The results are compared to the existing vibration-relaxation model.     

Electrical stress on irradiated thin gate oxide partially depleted SOI nMOSFETs

The effect of hot-carrier stress on 60 MeV proton irradiated thin gate oxide partially depleted SOI nMOSFETs has been studied. The results are compared with those from the electrical stress of non-irradiated devices. Whereas no significant differences are observed for the front channel degradation, hot-electron trapping in the buried oxide is found to be enhanced in the irradiated devices. This hot-electron trapping leads to a compensation or neutralization of the effects caused by the radiation-induced positive trapped charges. It is shown that a similar hot-electron trapping enhancement can be achieved in non-irradiated devices stressed under certain back gate bias conditions.     

The dependence of stress induced voiding on line width studied by conventional and high resolution resistance measurements

The degradation due to stress induced voiding of nitride passivated Al-1 wt.% Si and Ti/TN/ Al-1wt.% Si-0.5 wt. % Cu/Ti/TN interconnects with widths ranging between 0.4 and 1.2 μm was studied by in-situ conventional high resolution resistance measurements (HRRM) during storage at temperatures between 168 and 240°C. The conventional measurements on Al-Si lines, which lasted more than one year, clearly showed that the interconnect lifetime decreases with decreasing line width. With HRRM the degradation due to stress induced voiding can be detected much sooner and with much more detail. From the HRRM it is clear that the resistance changes during storage often happen in jumps and that the degradation has a rather complex alloy, line width and temperature dependence. Both for 0.4 and 0.6 μm wide Al---Si lines more degradation occurred for storage at 175 °C compared to storage at 200 °C. For the Al---Si---Cu stacks the degradation of 0.4 μm wide lines was worse for storage at 240°C compared to storage at 200 °C, but the opposite was true for the 0.6 μm wide lines.     

Measurement of Channel Stress Using Gate Direct Tunneling Current in Uniaxially Stressed nMOSFETs

We measure the conduction-band electron direct tunneling current through the 1.27-nm gate oxide of nMOSFETs transistors that undergo longitudinal stress via a layout technique. With known process parameters and published deformation potential constants as input, fitting of the measured direct tunneling current versus gate voltage leads to the channel stress of around 0, -100, and -300 MPa for a gate-to-trench isolation spacing of 2.4, 0.495, and 0.21 mum, respectively. To examine the accuracy of the method, a link with the mobility and threshold voltage measurements on the same device is conducted. The resulting piezoresistance coefficient and band offset are in good agreement with the literature values. The layout technique used is also validated.     

Transconductance increase due to charge trapping during hot-carrier stress of nMOSFETs

An unusual hot-carrier degradation mode characterised by a transconductance increase during hot-carrier ageing of nMOS transistors is analysed. By measuring the effects of hot-carrier stress on drain and substrate characteristics and applying alternate static injection phases performed at different gate regimes, it is proved that the degradation is mainly due to negative charge trapping in a localised region near the drain. The transconductance increase is explained in terms of an exchange of the dominant role between the damaged and undamaged portions of the channel. This model is fully corroborated by 2D device electric simulation results.     

Effect of FN stress and gate-oxide breakdown on high-frequency noise characteristics in deep-submicrometer nMOSFETs

The impact of Fowler-Nordheim (FN) stress and oxide breakdown on high-frequency noise characteristics in 0.18 /spl mu/m nMOSFET has studied. Noise characteristics of the devices at different leakage levels and breakdown hardness are compared. The results have shown a strong dependence of degradation of noise parameter on the gate leakage. The degradation mechanisms are analyzed by extraction of the channel and gate noise using a noise equivalent circuit model. It has been found that gate shot noise, which is commonly ignored in the as-processed nMOSFET, plays a dominant role in determining the high frequency noise in the post-oxide breakdown nMOSFET. The effect of FN stress and oxide breakdown is negligible.     

Channel width dependence of hot electron injection program/hot hole erase cycling behavior in silicon-oxide-nitride-oxide-silicon (SONOS) memories

The channel width dependence of hot electron injection program/hot hole erase cycling behavior in silicon-oxide-nitride-oxide-silicon (SONOS) memories is investigated. While the trapped charge profile-dependent overerasure is observed in 10-μm-wide device, it is suppressed in 0.22-μm-wide device. Both the overerasure suppression and gradual positive threshold voltage shift in narrow device are explained as an elevated hot hole injection efficiency followed by more pronounced redistribution of the hole profile in the channel-center and the suppression of the lateral migration of injected holes in the channel-edge, by combining the measured endurance characteristics and TCAD simulation results. Main physical mechanisms are three-dimensional distribution of the electric field by gate/drain voltage, increasing interface states, and their trapped charge with cycling in the channel-edge.     

多信道车载网络带宽调制算法

针对固定带宽车载网络频谱利用率低的问题,将半定规划法应用于多信道车载自组网带宽调制问题中,提出了一种车载自组网信道带宽调制算法.该算法首先在有频谱竞争的网络中测量相邻车辆间的距离,以确定网络冲突图;然后通过半定规划松弛来协调频谱的争用,最后以此为基础根据链路负载采用比例压缩策略求得频谱调制方案.仿真分析表明,该算法适用于多信道车载自组网,在动态拓扑环境下表现出较好的性能.     

Temperature dependence of hot-carrier-induced degradation in 0.1μm SOI nMOSFETs with thin oxide

This letter investigates hot-carrier-induced degradation on 0.1 μm partially depleted silicon-on-insulator (SOI) nMOSFETs at various ambient temperatures. The thermal impact on device degradation was investigated with respect to body-contact nMOSFETs (BC-SOI) and floating-body SOI nMOSFETs (FB-SOI). Experimental results show that hot-carrier-induced degradation on drive capacity of FB-SOI devices exhibits inverse temperature dependence compared to that of BC-SOI devices. This is attributed to the floating-body effect (FBE) and parasitic bipolar transistor (PBT) effect     

Voltage and current stress reduction in single-stage power factorcorrection AC/DC converters with bulk capacitor voltage feedback

Single-stage power factor correction (PFC) AC/DC converters integrate a boost-derived input current shaper (ICS) with a flyback or forward DC/DC converter in one single stage. The ICS can be operated in either discontinuous current mode (DCM) or continuous current mode (CCM), while the flyback or forward DC/DC converter is operated in CCM. Almost all single-stage PFC AC/DC converters suffer from high bulk capacitor voltage stress and extra switch current stress. The bulk capacitor voltage feedback with a coupled winding structure is widely used to reduce both the voltage and current stresses in practical single-stage PFC AC/DC converters. This paper presents a detailed analysis of the bulk capacitor voltage feedback, including the relationship between bulk capacitor voltage, input current harmonics, voltage feedback ratio, and load condition. The maximum bulk capacitor voltage appears when the DC/DC converter operates at the boundary between CCM and DCM. This paper also reveals that only the voltage feedback ratio determines the input current harmonics under DCM ICS and CCM DC/DC operation. The theoretical prediction of the bulk capacitor voltage as well as the predicted input harmonic contents is verified experimentally on a 60 W AC/DC converter with universal-line input     

The dependence of carrier lifetime on spectral width in multimode semiconductor lasers

Comprehensive measurements of the dependence of the carrier lifetime, eye pattern, and power penalty on the spectral width in multimode semiconductor lasers for a gigabit lightwave transmission system are presented. The results show that the carrier lifetime, eye pattern, and power penalty caused by mode partition noise (MPN) are strongly dependent on the source spectral width. The lasers with shorter carrier lifetimes exhibit a narrow spectral width, and hence show less MPN, a better eye opening, and a lower power penalty. A theoretical calculation of the MPN-induced power penalty is in good agreement with the measured system penalties. The likely cause for narrow spectral width with shorter carrier lifetime of the lasers is due to the smaller linewidth enhancement factor a caused by a higher doping concentration in the lasers.     

Channel potential and channel width in narrow buried-channel MOSFET's

A new method is described for determining the effective width over which incremental charge spreads in a narrow buried-channel transistor. The method is based on the transconductance in the buried-channel mode. Experimental results for effective widths and channel potential shifts are presented for MOSFET's with effective channel widths from 2 to 10 µm. Two-dimensional numerical calculations verify the experimental results.     

Pulse waveform dependence on AC bias temperature instability in pMOSFETs

In this letter, the waveform effects on the degradation enhancement of pMOSFETs under high-frequency (/spl ges/10/sup 4/ Hz) bipolar-pulsed bias-temperature (BT) stresses were systematically studied. The enhancement was found to be mainly governed by the fall time (t/sub F/) of the pulse waveform, namely, the transition time of the silicon surface potential from strong accumulation to strong inversion, rather than the pulse rise time (t/sub R/) and the pulse duty factor (D). The enhancement decreases significantly with t/sub F/ increasing, and is almost eliminated when t/sub F/ is larger than /spl sim/60 ns. This new finding is consistent with our newly proposed assumption that the recombination of free holes and trapped electrons at the SiO/sub 2//Si interface and/or near-interface states can enhance the interface trap generation.     

绝缘体上硅动态阈值nMOSFETs特性研究

基于绝缘体上硅技术,提出并研制动态阈值nMOSFETs结构.阐述了动态阈值nMOSFETs的工作原理.动态阈值nMOSFETs的阈值电压从VBS=0 V时的580 mV动态变化到VBS=0.6 V时的220 mV,但是这种优势并没有以增加漏电流为代价.因此动态阈值nMOSFETs的驱动能力较之浮体nMOSFETs在低压情况下,更具有优势.工作电压为0.6 V时,动态阈值nMOSFETs的驱动能力是浮体的25.5倍,0.7 V时为12倍.而且浮体nMOSFETs中的浮体效应,诸如Kink效应,反常亚阈值斜率和击穿电压降低等,均被动态阈值nMOSFETs结构有效抑制.     

Single event transient pulse width measurement of 65-nm bulk CMOS circuits

Heavy ion results of a 65-nm CMOS SET pulse width testchip are given. The influences of device threshold voltage, temperature and well separation on pulse width are discussed. Experimental data implied that the low device threshold, high temperature and well speraration would contribute to wider SET. The multi-peak phenomenon in the distribution of SET pulse width was first observed and its dependence on various factors is also discussed.