Improved interfacial properties of GaAs MOS capacitor with NH3-plasma-treated ZnON as interfacial passivation layer

The GaAs MOS capacitor was fabricated with HfTiON as high-k gate dielectric and NH₃-plasma-treated ZnON as interfacial passivation layer (IPL), and its interfacial and electrical properties are investigated compared to its counterparts with ZnON IPL but no NH₃-plasma treatment and without ZnON IPL and no plasma treatment. Experimental results show that low interface-state density near midgap (1.17×10¹² cm^-2eV^-1) and small gate leakage current density have been achieved for the GaAs MOS device with the stacked gate dielectric of HfTiON/ZnON plus NH₃-plasma treatment. These improvements could be ascribed to the fact that the ZnON IPL can effectively block in-diffusion of oxygen atoms and out-diffusion of Ga and As atoms, and the NH₃-plasma treatment can provide not only N atoms but also H atoms and NH radicals, which is greatly beneficial to removal of defective Ga/As oxides and As-As band, giving a high-quality ZnON/GaAs interface.     

ZrON/GeON 双钝化层改善Ge MOS器件的界面特性和电特性

本文研究了利用等离子体氮化形成ZrON/GeON双钝化层制备Ge MOS器件的界面特性和电特性。结果发现,相比于N2等离子处理,NH3等离子处理制备的双钝化层显著改善了器件的界面和电特性,获得了低的界面态密度 (Dit = 1.64×1011 cm-2 eV-1)和栅极漏电流(Jg = 9.32×10-5 A cm-2@Vfb +1 V),小的电容等效厚度 (CET = 1.11 nm)以及高的k值 (32). XPS分析表明,由NH3等离子体分解出的H原子和NH基团可以有效促进Ge表面不稳定低k GeOx的挥发,从而形成了高质量的GeON钝化层;且NH3等离子体氮化导致更多氮在ZrON/GeON中结合,能更有效阻止O、Ti、Ge等元素间的相互扩散,从而获得好的界面质量和电特性。     

Electrical properties and barrier modification of GaAs MIS Schottky device based on MEH-PPV organic interfacial layer

We report fabrication and electrical characterization of GaAs based metal-interfacial layer-semiconductor (MIS) device with poly[2-methoxy-5-(2^/-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV), as an interfacial layer. MEH-PPV raises the barrier height in Al/MEH-PPV/p-GaAs MIS device as high as to 0.87 eV. A Capacitance-Voltage (C–V) characteristic exhibits a low hysteresis voltage with an interface states density of 1.69×10¹¹ cm⁻² eV⁻¹. Moreover, a high transition frequency (f_c) of about 50 kHz was observed in the accumulation mode. The photovoltaic response of Al/MEH-PPV/p-GaAs device was measured under the air masses (AM) 1.0 and 1.5. The open circuit voltage (V_OC), short circuit current (I_SC), fill factor and the efficiency of the Al/MEH-PPV/p-GaAs device were found to be 1.10 V, 0.52 mA, 0.65, and 5.92%, respectively, under AM 1.0 condition.     

Investigation on interfacial and electrical properties of Ge MOS capacitor with different NH3-plasma treatment procedure

The effects of different NH₃-plasma treatment procedures on interfacial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HfTiON/TaON were investigated. The NH₃-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric, i.e. before or after interlayer (TaON) deposition, or after deposition of high-k dielectric (HfTiON). It was found that the excellent interface quality with an interface-state density of 4.79×10¹¹ eV^-1cm^-2 and low gate leakage current (3.43×10^-5A/cm² at V_g=1 V) could be achieved for the sample with NH₃-plasma treatment directly on the Ge surface before TaON deposition. The involved mechanisms are attributed to the fact that the NH₃-plasma can directly react with the Ge surface to form more Ge-N bonds, i.e. more GeO_xN_y, which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeO_x interfacial layer, and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH₃-plasma.     

0.6nm-EOT high-k gate stacks with HfSiOx interfacial layer grown by solid-phase reaction between HfO2 and Si substrate

We have developed a process for forming an ultra-thin HfSiO_x interfacial layer (HfSiO_x-IL) for high-k gate stacks. The HfSiO_x-IL was grown by the solid-phase reaction between HfO₂ and Si-substrate performed by repeating the sequence of ALD HfO₂ deposition and RTA. The HfSiO_x-IL grown by this method enables the formation of very uniform films consisting of a few mono-layers, and the dielectric constant of the HfSiO_x-IL is about 7. The FUSI-NiSi/HfO₂ gate stacks with HfSiO_x-IL have achieved 0.6 nm EOT, a very low gate leakage currents between 1 A/cm² and 5 × 10⁻² A/cm², an excellent subthreshold swing of 66mV/dec, and a high peak mobility of 160 cm²/Vs compared to the reference samples without HfSiO_x-IL. These results indicate that the HfSiO_x-IL has a good quality compared to the SiO₂ interfacial layer grown by oxygen diffusion through HfO₂ films.     

Characterization of MIS structures and thin film transistors using RF-sputtered HfO2/HIZO layers

MIS structures using HfO₂ and HIZO layers, both deposited by room temperature RF magnetron sputtering are fabricated for TFTs application and characterized using capacitance-voltage. The relative dielectric constant obtained at 1 kHz was 11, the charge carrier concentration of the HIZO was in the range of (2–3) × 10¹⁸ cm^− 3 and the interface trap density at flat band was smaller than 2 × 10¹² cm^− 2. The critical electric field of the HfO₂ layer was higher than 5 × 10⁵ V/cm, with a current density in the operating voltage range below 4 × 10^− 8 A/cm². The hysteresis and bias stress behavior of RF-sputtered HfO₂/HIZO MIS structures is presented. Fabricated HfO₂/HIZO TFTs worked in the operation voltage range below 8 V.     

Structural,optical and transport properties of SxZnO

In this paper, S-doped ZnO (S_xZnO) was prepared using sol-gel method at different S amounts. The structural, optical and transport properties were investigated. The introduction of S atoms into the ZnO network was found to lower the crystallization level which results in reducing the crystallite size up to x=0.3. The doping process is confirmed by the observed peak at ~610 cm⁻¹ in the ATR spectrum related to the Zn-S linking. EDX mapping shows a homogeneous distribution of S atoms on the particles surface. The best compromise between the band gap (Eg=2.96 eV), the charge carriers (N_A=2.139×10²² cm⁻³), the conductivity (σ=5.56×10⁻⁴ Ω⁻¹ m⁻¹) and the mobility (µ=16.26×10⁻¹⁴ m² V⁻¹ s⁻¹) is obtained for x=0.1. The conduction mechanism is assumed by small hopping polaron. The S-doping has impacted positively the photocatalytic activity of ZnO, with particularly high performance for S_0.2ZnO.     

Effect of interface traps for ultra-thin high-k gate dielectric based MIS devices on the capacitance-voltage characteristics

The impact of states at the Al₂O₃/Si interface on the capacitance-voltage C-V characteristics of a metal/insulator/semiconductor heterostructure (MIS) capacitor was studied by a numerical simulation, by solving Schrodinger-Poisson equations and taking the electron emission rate from the interface state into account. Efficient computation and accurate physics based capacitance model of MOS devices with advanced ultra-thin equivalent oxide thickness (EOT) (down to 2.5 nm clearly considered here) were introduced for the near future integrated circuit IC technology nodes. Due to the importance of the interface state density for a low dimension and very low oxide thickness, a high frequency C-V model has been developed to interpret the effect of interface state density traps which communicate with the Al₂O₃/Si and their influence on the C-V characteristics. We found that these states are manifested by jumping capacity in the inversion zone, for a density of interface, higher than 1 × 10¹¹ cm^− 2 eV^− 1 during a p-doping of 1 × 10¹⁸ cm^− 3. This behavior has been investigated with various doping, temperature, frequency and energy levels on the C-V curves, and compared with the MIS structure that contains a standard SiO₂ insulator.     

Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications

Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiO_xN_y metal oxide NPs embedded in the HfO_xN_y high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O₂/N₂ ambient. Well-isolated TiO_xN_y NPs with a diameter of 5–20 nm, a surface density of ～3 × 10¹¹ cm^?2, and a charge trap density of around 2.33 × 10¹² cm^?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping.     

In-situ MBE Si as passivating interlayer on GaAs for HfO2 MOSCAP’s: effect of GaAs surface reconstruction

We report a study of MOS capacitors having a dielectric of HfO₂ and an interlayer of Si deposited in-situ, by MBE on GaAs surfaces prepared with various surface-reconstructions. Interface state densities of about 1 × 10¹² eV⁻¹cm⁻² have been obtained. Capacitors on the Ga-rich surface, measured with peripheral illumination, show signs of a possible inversion layer.     

Study on mobility enhancement in MOVPE-grown AlGaN/AlN/GaN HEMT structures using a thin AlN interfacial layer

Al_0.26Ga_0.74N/AlN/GaN high-electron-mobility transistor (HEMT) structures with AlN interfacial layers of various thicknesses were grown on 100-mm-diameter sapphire substrates by metalorganic vapor phase epitaxy, and their structural and electrical properties were characterized. A sample with an optimum AlN layer thickness of 1.0 nm showed a highly enhanced Hall mobility (μ_Hall) of 1770 cm²/Vs with a low sheet resistance (ρ_s) of 365 Ω/sq. (2DEG density n_s = 1.0 × 10¹³/cm²) at room temperature compared with those of a sample without the AlN interfacial layer (μ_Hall = 1287 cm²/Vs, ρ_s = 539 Ω/sq., and n_s = 0.9 × 10¹³/cm²). Electron transport properties in AlGaN/AlN/GaN structures were theoretically studied, and the calculated results indicated that the insertion of an AlN layer into the AlGaN/GaN heterointerface can significantly enhance the 2DEG mobility due to the reduction of alloy disorder scattering. HEMTs were successfully fabricated and characterized. It was confirmed that AlGaN/AlN/GaN HEMTs with the optimum AlN layer thickness show superior DC properties compared with conventional AlGaN/GaN HEMTs.     

Charge trapping in ultrathin Gd2O3 high-k dielectric

Charge trapping in ultrathin high-k Gd₂O₃ dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 × 10⁻²⁰ cm². The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 × 10¹² eV⁻¹ cm⁻² near the valence band edge.     

High-frequency method to determine SiC crystal conductivity

In this paper, we present a simple non-destructive method for testing SiC plate single crystals of any size and shape. The method is based on measuring the impedance changes of an inductive ferrite-cored coil due to placing the sample into the core gap. The method is valid for any SiC polytypes, though we used 6H one. Using this method we have obtained and discussed a conductivity as a function of doping level (N_d–N_a) for 6H–SiC Lely crystals. The conductivity measurements were carried out with alternating current of 747 kHz frequency. The sensitivity of the method is limited by minimal conductivity 1 Ω⁻¹ cm⁻¹ (that is corresponding to (N_d–N_a)∼2×10¹⁶ cm⁻³ for 6H–SiC : N Lely crystals).     

Properties of fluorine-doped SnO2 thin films by a green sol–gel method

Fluorine doped tin oxide (FTO) films were fabricated on a glass substrate by a green sol–gel dip-coating process. Non-toxic SnF₂ was used as fluorine source to replace toxic HF or NH₄F. Effect of SnF₂ content, 0–10 mol%, on structure, electrical resistivity, and optical transmittance of the films were investigated using X-ray diffraction, Hall effect measurements, and UV–vis spectra. Structural analysis revealed that the films are polycrystalline with a tetragonal crystal structure. Grain size varies from 43 to 21 nm with increasing fluorine concentration, which in fact critically impacts resultant electrical and optical properties. The 500 °C-annealed FTO film containing 6 mol% SnF₂ shows the lowest electrical resistivity 7.0×10⁻⁴ Ω cm, carrier concentration 1.1×10²¹ cm⁻³, Hall mobility 8.1 cm²V⁻¹ s⁻¹, optical transmittance 90.1% and optical band-gap 3.91 eV. The 6 mol% SnF₂ added film has the highest figure of merit 2.43×10⁻² Ω⁻¹ which is four times higher than that of un-doped FTO films. Because of the promising electrical and optical properties, F-doped thin films prepared by this green process are well-suited for use in all aspects of transparent conducting oxide.     

Self-catalyzed molecular beam epitaxy growth and their optoelectronic properties of vertical GaAs nanowires on Si(111)

Self-assembled GaAs nanowires were grown by molecular beam epitaxy (MBE) on un-pretreated Si(111) substrates under different As₄/Ga flux ratios (V/III ratios). It has been found that the fraction of vertical wires would be nearly 100% when the As₄/Ga ratio arrives 90. The transmission electron microscopy (TEM) and micro-photoluminescence (PL) spectra results have indicated that the GaAs nanowires grown under a larger V/III ratio (90) have a pure ZB structure. Field-effect transistors (FET) based on single nanowire were fabricated with GaAs nanowires grown under the larger V/III ratio (90). The characteristics of the FET reveal a hole concentration of 3.919×10¹⁷ cm⁻³ and a hole mobility of 0.417 cm² V⁻¹s⁻¹. Photodetectors based on single nanowire and multiple nanowires structure with a metal-semiconductor-metal (MSM) electrode configuration have been proposed and demonstrated. All the photodetectors operating at room temperature exhibit good photoconductive performance, excellent stability, reproducibility and superior peak responsivity (87.67 A/W under 5 V for single nanowire photodetector).     

Potentiality of trap charge effects and SiON induced interface defects in a-Si3N4/SiON based MIS structure for resistive NVM device

Potential application of amorphous silicon nitride (a-Si₃N₄)/silicon oxy-nitride (SiON) film has been demonstrated as resistive non-volatile memory (NVM) device by studying the Al/Si₃N₄/SiON/p-Si metal–insulator–semiconductor (MIS) structure. The existence of several deep trap states was revealed by the photoluminescence characterizations. The bipolar resistive switching operation of this device was investigated by current–voltage measurements whereas the trap charge effect was studied in detail by hysteresis behavior of frequency dependent capacitance–voltage characteristics. A memory window of 4.6 V was found with the interface trap density being 6.4 × 10¹¹ cm⁻² eV⁻¹. Excellent charge retention characteristics have been observed for the said MIS structure enabling it to be used as a reliable non-volatile resistive memory device.     

Experimental study for high effective mobility with directly deposited HfO2/La2O3 MOSFET

We experimentally examine the effective mobility in nMOSFETs with La₂O₃ gate dielectrics without SiO_x-based interfacial layer. The reduced mobility is mainly caused by fixed charges in High-k gate dielectrics and the contribution of the interface state density is approximately 30% at N_s = 5 × 10¹¹ cm^?2 in the low 10¹¹ cm^?2 eV^?1 order. It is considered that one of the effective methods for improving mobility is to utilize La-silicate layer formed by high temperature annealing. However, there essentially exists trade-off relationship between high temperature annealing and small EOT.     

Interface states in polyfluorene-based metal–insulator–semiconductor devices

Hybrid metal–insulator–semiconductor structures based on ethyl-hexyl substituted polyfluorene (PF2/6) as the active polymer semiconductor were fabricated on a highly doped p-Si substrate with Al₂O₃ as the insulating oxide layer. We present detailed frequency-dependent capacitance–voltage (C–V) and conductance–voltage characteristics of the semiconductor/insulator interface. PF2/6 undergoes a transition to an ordered crystalline phase upon thermal cycling from its nematic-liquid crystalline phase, confirmed by our atomic force microscope images. Thermal cycling of the PF2/6 films significantly improves the quality of the (PF2/6)/Al₂O₃ interface, which is identified as a reduced hysteresis in the C–V curve and a decreased interface state density (D_it) from ∼3.9 × 10¹² eV⁻¹ cm⁻² to ∼3.3 × 10¹¹ eV⁻¹ cm⁻² at the flat-band voltage. Interface states give rise to energy levels that are confined to the polymer/insulator interface. A conductance loss peak, observed due to the capture and emission of carriers by the interface states, fits very well with a single time constant model from which the D_it values are inferred.     

Improved reliability of AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with high density silicon nitride passivation

We have systematically studied the effects of Si_xN_1 − x passivation density on the reliability of AlGaN/GaN high electron mobility transistors. Upon stressing, devices degrade in two stages, fast-mode degradation and followed by slow-mode degradation. Both degradations can be explained as different stages of pit formation at the gate-edge. Fast-mode degradation is caused by pre-existing oxygen at the Si_xN_1 − x/AlGaN interface. It is not significantly affected by the Si_xN_1 − x density. On the other hand, slow-mode degradation is associated with Si_xN_1 − x degradation. Si_xN_1 − x degrades through electric-field induced oxidation in discrete locations along the gate-edges. The size of these degraded locations ranged from 100 to 300 nm from the gate edge. There are about 16 degraded locations per 100 μm gate-width. In each degraded location, low density nano-globes are formed within the Si_xN_1 − x. Because of the low density of the degraded locations, oxygen can diffuse through these areas and oxidize the AlGaN/GaN to form pits. This slow-mode degradation can be minimized by using high density (ρ = 2.48 g/cm³) Si₃₆N₆₄ as the passivation layer. For slow-mode degradation, the median time to failure of devices with high density passivation is found to increase up to 2× as compared to the low density (ρ = 2.25 g/cm³) Si₄₃N₅₇ passivation. A model based on Johnson-Mehl-Avrami theory is proposed to explain the kinetics of pit formation.     

The effect of various concentrations of PVDF-HFP polymer gel electrolyte for dye-sensitized solar cell

A PVDF-HFP gel electrolytes based DSSCs were fabricated successfully, where gel electrolytes with 2.5 wt.%, 5 wt.%, 10 wt.% and 15 wt.% PVDF-HFP are included, respectively. Linear sweep voltammetry (LSV), photocurrent–voltage measurements and electrochemical impedance spectra (EIS) were measured. As the results shown, the apparent diffusion coefficient (D_app) of I⁻ and I₃⁻ decreased as PVDF-HFP increased. D_app of I⁻ and I₃⁻ are decreased from 1.87 × 10^− 6 to 0.67 × 10^− 6 cm²/s and 3.28 × 10^− 6 to 0.88 × 10^− 6 cm²/s, respectively. For the solar cell measurements, the short circuit current density (J_sc) were affected by the ion motilities, which was decreased from 11.58 mA/cm² to 8.17 mA/cm², and the energy converting efficiency (η %) was decreased from 5.17% to 2.79%. For electrochemical impedance spectra (EIS) measurements, the ionic diffusion impedance for the redox-couple (I⁻/I₃⁻) in the gel electrolyte was also increased with the concentration of PVDF-HFP from 0.61 Ω to 8.17 Ω. In the Bode Plots, the electron lifetime (τ_e) of the 2.5 wt.% and 5 wt.% PVDF-HFP electrolytes was increased from 40.52 ms to 48.48 ms and 41.29 ms, respectively. However, τ_e was decreased in the concentrations of 10 wt.% and 15 wt.% PVDF-HFP, due to the ion motilities that were decreased by excessing PVDF-HFP polymer. For gel electrolyte, the cell of 2.5 wt.% PVDF-HFP exhibited a better J_SC of 10.89 mA/cm², a higher energy conversion efficiency (η) of 4.75%, a higher fill factor (FF) of 61.26%, and a smaller R of 1.06 Ω than the 15 wt.% PVDF-HFP based cell.