Comparison of laser voltage probing and mapping results in oversized and minimum size devices of 120 nm and 65 nm technology

Laser voltage probing (LVP) provides signal levels from circuit nodes through the backside of integrated circuits. Previous investigations presented voltage sweeping and modulation mapping, based on CW (continuous wave) 1319 nm laser. In this paper, large device structures have been compared with results of measurements on sub-micron devices – having nominal gate lengths and widths – including a ring oscillator (RO). All signals were obtained with a spectrum analyzer, requiring no internal trigger signals from the circuitry. On ROs, frequency shifts due to the thermal stimulation effect could be determined. Furthermore, a new measurement scheme for sign measurements of LVP signals is introduced.     

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

With the critical charge reduced to generate a single event effect (SEE) and high working frequency for a nanometer integrated circuit, the single event effect (SET) becomes increasingly serious for high performance SOC and DSP chips. To analyze the radiation-hardened method of SET for the nanometer integrated circuit, the n⁺ guard ring and p⁺ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library. The weakest driving capacity inverter cell was used to evaluate the single event transient (SET) pulse-width distribution. We employed a dual-lane measurement circuit to get more accurate SET''s pulse-width. Six kinds of ions, which provide LETs of 12.5, 22.5, 32.5, 42, 63, and 79.5 MeV·cm²/mg, respectively, have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LET_eff from 12.5 MeV·cm²/mg to 79.5 MeV·cm²/mg and the pulse-width presents saturation tendency when the effective linear energy transfer (LET_eff) value is larger than 40 MeV·cm²/mg. The test results also show that the hardened commercial standard cell''s pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.     

A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm².     

Low voltage stress induced leakage current and time to breakdown in ultra-thin (1.2–2.3 nm) oxides

Ultra-thin gate-oxide reliability is an essential factor in CMOS technologies. The low voltage gate current in ultra-thin oxide of metal–oxide–semiconductor devices is very sensitive to electrical stresses. It can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements. In this paper, the low voltage stress induced leakage current (LVSILC) for various oxide thicknesses ranging from 1.2 to 2.3 nm is investigated during constant voltage stress (CVS). From the LVSILC measurements, we shown that time to breakdown can be deduced as a function of the stress voltage. We also study the effect of elevated stress temperature on the time to breakdown. We show that temperature dependence of the time to breakdown is non-Arrhenius and decreases in a drastic way with a slope of 0.036 decade/°C.     

Simulation of the thermal stress induced by CW 1340 nm laser on 28 nm advanced technologies

Previous study on the invasiveness of the CW 1340 nm laser source used in failure analysis, pinpointed silicide diffusions issue and experimentally defined a safe experimental area. Nevertheless, experimentally defining a safe area is a very long process. So we bypassed it by a new approach based on thermal laser stress modelling for defect localization applications (LVI/OBIRCH, cw-LVP). The first target of this study is the 28 nm FDSOI technologies. The results of this simulation are also compared to experiments to check accordance with the temperatures of material diffusion. The model can be used to define safe and not safe areas of interaction between the laser and the IC (exposure time, laser power). Laser invasiveness issues for different technologies and geometries can also be addressed.     

Multi-Poisson process analysis of real-time soft-error rate measurements in bulk 65 nm and 40 nm SRAMs

Altitude and underground real-time soft error rate (SER) measurements on SRAM circuits have been analyzed in terms of independent multi-Poisson processes describing the occurrence of single events as a function of bit flip multiplicity. Applied for both neutron-induced and alpha particle-induced SERs, this detailed analysis highlights the respective contributions of atmospheric radiation and alpha contamination to multiple cell upset mechanisms. It also offers a simple way to predict by simulation the radiation response of a given technology for any terrestrial position, as illustrated here for bulk 65 nm and 40 nm SRAMs.     

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs

Design automation tools have been developed to suppress CDE-induced latchup in CMOS ASICs. The tools govern the placement of I/Os and cores subject to CDE and automate the insertion of well and substrate contacts with varying periodicities around CDE susceptible cells according to rules derived from an analytical latchup model.     

温度对SRAM器件单粒子翻转重离子测试的影响

本文基于单粒子效应地面重离子模拟实验,选取体硅SRAM与SOI SRAM两种待测器件,在兰州重离子加速器上（HIRLF）研究了温度对单粒子翻转测试的影响。用12C粒子对体硅SRAM器件的温度实验显示,单粒子翻转截面易受温度的影响。对于SOI SRAM器件,12C粒子测得的单粒子翻转截面随温度升高有显著的增大,但209Bi 粒子测得的单粒子翻转截面却随温度保持恒定。用Monte Carlo的方法分析了温度对单粒子翻转测试的影响规律,发现在单粒子翻转阈值LET附近温度对单粒子翻转截面有大的影响,但是随着单粒子翻转的发生接近于饱和,单粒子翻转截面渐渐的表现出低的温度依赖性。基于该模拟结果,我们对实验数据进行了分析,同时提出了一种准确评估在轨翻转率的合理方法。     

Design and Analysis of Varactorless 65 nm MMW Voltage Controlled Oscillator

In this work a novel inductive tuning technique for millimeter wave (mmw) applications is presented. Fine frequency tuning is performed using a transformer. For the LC tanks inductive element, transformer is used. To tune the VCO MOS switch is placed at center tapping of the secondary coil of the transformer. The simulation shows that by changing the operating condition of MOS switch frequency band from 59.1 GHz to 64.6 GHz is obtained. The proposed 60 GHz VCO is designed using UMC 65 nm CMOS single Poly eight Metal (1P8M) Technology. Obtained Frequency Tuning Range (FTR) is 8.89% and the corresponding phase noise variation is from ???112.4 dBc/Hz to ???115.9 dBc/Hz at 10 MHz offset from the carrier. The worst phase noise value is ???112.4 dBc/Hz which is obtained at 0.3 V tuning voltage. For 0.8 V supply voltage 7.44 mW of power is dissipated. And the calculated Figure of Merit (FOM) for whole FTR, ranges from ???179.89 dBc/Hz to ???182.62 dBc/Hz.

     

卫星光通信系统中单粒子翻转计算方法研究

高能带电粒子造成的单粒子翻转是影响卫星光通信系统性能的重要因素,给出了单粒子翻转的物理机制及主要研究方法。利用OMERE 3.4软件对星载CMOS 2164器件进行了单粒子翻转率计算,结果表明,通过对轨道倾角和轨道高度的优化设计可以有效减小卫星光通信系统中电子器件的单粒子翻转率。为了有效克服单粒子辐射效应,除了简单的增加屏蔽层厚度等防护方法外,还应考虑通过电子器件的选择来提高抗辐射性能。     

Time-To-Latch-Up investigation of SCR devices as ESD protection structures on 65 nm technology platform

The purpose of this work was to study the influence of different layout parameters on the electrical performances and Time-To-Latch-Up (TTLU) by means of the injection of substrate current on SCR devices to be used as ESD protection structures for the 65 nm Flash memory technology platform. Low (1.2 V) and high (5.0 V) voltage class devices were studied in DC and 100 ns TLP regimes, and an ad hoc setup was developed to investigate TTLU as a function of the injected current needed to Latch-Up HV-SCRs. Results were then compared to 2D device simulations.     

Investigation of 65 nm CMOS transistor local variation using a FET array

CMOS FET local variation has been investigated using a new FET array structure. Key findings include four aspects. (1) At deep sub-micron technology node, local variation is significantly higher than global variation. Only 5–10% of total variation is a result of global variation. (2) Sample size affects point estimate of local variation. Sample size error can account for a significant portion of the fluctuation in the point estimate of local variation. (3) Well proximity effect (WPE) has a small impact on V_t local variation. Its impact on local variation of drive current is more significant. (4) Local variation reduces with temperature. The magnitude of NMOS V_t local variation reduction is more pronounced than PMOS. These results form a solid foundation to accurately model MOSFET local variation.     

A 350 mV, 2 MHz, 16-kb SRAM with programmable wordline boosting in the 65 nm CMOS technology

Analog Integrated Circuits and Signal Processing - The paper presents an SRAM macro capable of working down to 350 mV with programmable wordline boosting feature. Wordline boosting allows...     

Roadmap for 22 nm and beyond (Invited Paper)

The down-scaling is still the most important and effective way for achieving the high-performance logic CMOS operation with low power, regardless of its concern for the technological difficulties, and thus, the past shrinking trend of the gate-length has been very aggressive. In this paper, logic CMOS technology roadmap for ‘22 nm and beyond’ is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The future gate-length shrinking trend predicted in the past several versions of the ITRS has been too aggressive even for the most advanced semiconductor companies to catch up, and thus, the predicted trend has been amended to be less aggressive from the ITRS 2008 Update, resulting in the delay in the gate-length shrinkage for 3 years in the short term and 5 years in the long term from those predicted in ITRS 2007. Corresponding to this, the pace of the introduction of new technologies becomes slower. For the long term, the limit of the downsizing is a big concern. The limit is expected to be at the gate length of around 5 nm because of the too huge off-leakage current in the entire chip. Until that we will have probably six more generations or ‘technology nodes’, considering that we are now in the so-called 45 nm generation. It would take probably 20–30 years until we reach the final limit, because the duration between the generations will become longer when approaching the limit. In order to suppress the off-leakage current, double gate (DG) or fin-FET type MOSFETs are the most promising. Then, it is a natural extension for DG FETs to evolve to Si-nanowire MOSFETs as the ultimate structure of transistors for CMOS circuit applications. Si-nanowire FETs are more attractive than the conventional DG FETs because of higher on-current conduction due to their quantum nature and also because of their adoptability for high-density integration including that of 3D. Then, what will come next after reaching the final limit of the downsizing? The answer is new algorithm. In the latter half of this century, the application of algorithm used for the natural bio system such as the brains of insects and even human will make the integrated circuits operation tremendously high efficiency. Much higher performance with ultimately low power consumption will be realized.     

Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor

This paper reports on the effects of the Halo structure variations on threshold voltage (V_th) in a 22 nm gate length high-k/metal gate planar NMOS transistor. Since the V_th is one of the important physical parameter for determining the functionality of complementary metal-oxide–semiconductor device, this experiment will focus on finding the best combination on process parameter to achieve the best value of V_th. The Halo structure variable process parameters are the Halo implantation dose, the Halo implantation tilting angle, the Source/Drain implantation dose and the compensation implantation dose. The design of the planar device consists of a combination of high permittivity material (high-k) and a metal gate. Titanium dioxide was used as the high-k material instead of the traditional SiO₂ dielectric and tungsten silicide was used as the metal gate. The optimization process was executed using Taguchi's L₉ array to obtain a robust design. Taguchi's Nominal-the-Best signal-to-noise ratio was used in an effort to minimize the variance of V_th. The results show that the V_th values have least variance and the mean value can be adjusted to 0.289 V±12.7% which is in line with projections made by the International Technology Roadmap for Semiconductors.     

Research on the effect of single-event transient of an on-chip linear voltage regulator fabricated on 130 nm commercial CMOS technology

We report single-event transient (SET) responses of an on-chip linear voltage regulator in 130 nm commercial standard CMOS technology by heavy ion experiments at first. Responses can be distinguished by the load current. When the light load current was applied, the negative SET on the output of the regulator larger than 200 mV was not observed, while the positive SETs that are larger than 400 mV and last for about 200 ns were observed. By comparison, when the heavy load current was applied, both positive and negative SETs that are larger than 400 mV and last for several hundred ns were observed. Next, the mechanism behind the phenomenon is analysed and then verified by the post-layout SPICE circuit simulation. It is demonstrated that the input voltage, load current and the load capacitance are key elements in determining the severity of SET. Finally, the most sensitive node is located by analysis and SPICE circuit simulation, which lies in the output of the amplifier inside of the bandgap reference (BGR). This result is a primary consideration in the development of the hardening technique.     

Low-leakage MIS structures with 1.5-6 nm CaF2 insulating layer on Si(1 1 1)

Thin high-quality calcium fluorite films are grown on (1 1 1) silicon in the low- and middle- temperature molecular-beam epitaxy processes followed by annealing. Metal-insulator-semiconductor structures with such films exhibit much smaller leakage currents than the casual structures with silicon dioxide. They demonstrate also satisfactory wear-out characteristics. Low leakage is achieved not due to high permittivity, but due to restricted tunnel transparency of the fluorite owing to a large effective mass of carriers. Therefore, CaF₂ is a promising candidate for gate material in advanced field-effect transistors.     

Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm

Classical scaling equations which estimate parameters such as circuit delay and energy per operation across technology generations have been extremely useful for predicting performance metrics as well as for comparing designs across fabrication technologies. Unfortunately in the CMOS deep-submicron era, the classical scaling equations are becoming increasingly less accurate and new practical scaling methods are needed. We curve fit second and third-order polynomials to circuit delay, energy, and power dissipation results based on HSpice simulations utilizing the Predictive Technology Model (PTM) and International Technology Roadmap for Semiconductors (ITRS) models. While the classical scaling equations give differences as much as 83×from the predictions of PTM and ITRS models, our predictive polynomial models with table-based coefficients yield a coefficient of determination, or R², value of greater than 0.95.     

Statistical simulation of random dopant induced threshold voltage fluctuations for 35 nm channel length MOSFET

Intrinsic parameter fluctuations have become a very important problem for the scaling and integration of future generations of nano-CMOS transistors impacting on circuit and systems yield and reliability. In this paper random discrete dopant (RDD) induced threshold voltage variations have been studied using the Glasgow 3D atomistic drift/diffusion simulator. For the first time, we have carried out statistical simulation based on groundbreaking sample of 100,000 transistors which may assess more than 4σ of the statistical distribution. In order to correctly access the accuracy and the confidence level of the statistical parameters, we have carried out comprehensive statistical analysis using state-of-art statistical tools amenable to our problem. We use the first four moments to fit distribution of RDD induced fluctuations in the threshold voltage by means of several statistical approaches.