共查询到17条相似文献,搜索用时 31 毫秒
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云发生器是构造云模型不确定性推理和设计云模型智能控制器的基础,全面论述了一种基于硬件真随机数云发生器的实现方法.首先设计一种基于雪崩噪声电路产生的真随机数序列发生器,利用LabVIEW平台构建测试系统对其进行一系列特性检验,进而将该真随机数序列转换为正态分布的真随机数作为云发生器的随机数源,最后设计一种真随机数云发生器算法,并通过LabVIEW平台编程实现.实验结果表明,该真随机数云发生器生成结果十分理想,可为云模型不确定性推理后续研究提供基础. 相似文献
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作为现代加密系统不可或缺的一部分,真随机数发生器(TRNG)在信息安全中具有非常重要的作用。 本文提出了一种可配置、轻量级、高吞吐量的真随机数发生器。 该结构利用与非门和异或门构成了可配置的异步反馈环形振荡器,通过在短时间内增加相位噪声,来扩大时间抖动范围,从而改善了熵源的随机性。 该结构在 Xilinx Kintex-7 进行了多次测试验证,实验结果表明,在不同温度(0℃ ~ 80℃ )和不同输出电压(0. 8~ 1. 2 V)的环境变化下,所提出的 TRNG 具有较强的鲁棒性,在硬件资源上仅消耗了 43 个 LUTs 和 6 个 DFFs,并且获得高达 300 Mb / s 的吞吐量。 同时,生成的随机比特流能够以较高的 P 值通过 NISTSP800-22 和 NIST SP800-90B 测试。 相似文献
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功率测量设备的工作范围一般在几百赫,而超声设备的输出一般为几十千赫,甚至几兆赫的高频大电压方波信号,其中还往往含有较多的谐波成分。因此,一般的功率测量设备难以准确地测量出系统的功率。本文采用了真有效值转换技术并以真有效值转换集成芯片AD736为核心部件,合理设计电压、电流采样电路以及功率计算电路,实现了对高频大功率电路的功率测量。此电路可以对超声发生器的输出电功率进行实时监控,也可以应用在其他设备的功率测量系统中。 相似文献
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王晓雨;董守龙;马剑豪;余亮;姚陈果 《电工技术学报》2020,(4):799-806
随着脉冲功率技术在生物医疗、食品加工、电磁成形、等离子体研究等领域日益广泛而深入的应用,脉冲发生器的研制面临高压高频化、双极性、全固态化等新要求。因此,该文提出一种新型模块化的双极性高压高频脉冲发生器的研制策略,主要包括拓扑结构研究、电路理论仿真及原型机研制等内容。通过理论分析、仿真和实验,结果表明此发生器较好地结合了固态Marx和桥式电路的优点,可根据实际需求,通过量化的多级模块堆叠实现高压输出;并可使用开关的时序逻辑控制实现输出极性和脉冲宽度灵活调节;同时具有高重频长寿命。实验原理样机具体参数为输出电压幅值±5kV,脉冲串内重复频率2.5MHz,脉冲宽度200ns~10μs连续可调。 相似文献
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《International Journal of Circuit Theory and Applications》2017,45(11):1885-1897
This paper presents implementation of a chaotic cellular neural network (CNN)‐based true random number generator on a field programmable gate array (FPGA) board. In this implementation, discrete time model of the chaotic CNN is used as the entropy source. Random number series are generated for three scenarios. Obtained number series are tested by using NIST 800.22 statistical test suite. Also, the scale index technique is carried out for these three scenarios to determine the degree of non‐periodicity for key stream. Copyright © 2017 John Wiley & Sons, Ltd. 相似文献
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A novel non‐autonomous continuous‐time chaotic oscillator suitable for high‐frequency integrated circuit realization is presented. Simulation and experimental results, verifying the circuit feasibility, are given. Two methods for using this oscillator as the core of a random number generator are also proposed. Numerical binary data obtained according to the proposed methods pass the four basic tests of FIPS‐140‐2, while experimental data pass the full NIST‐800‐22 random number test suite. Copyright © 2008 John Wiley & Sons, Ltd. 相似文献
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Ramji Gupta Alpana Pandey Rajendra Kumar Baghel 《International Journal of Numerical Modelling》2019,32(5)
A true random number generator (TRNG) is a basic building block of many modern cryptographic systems. As field programmable gate array (FPGA) has a flexible architecture and low‐cost test cycle, hence, it becomes an ideal platform for hardware implementation of digital systems. This paper presents an FPGA implementation of a high‐speed TRNG that is based on a chaotic oscillator at 100 MHz frequency with speed of 1600 Mbps. The experimental results show that the proposed generator is faster and more compact than the existing chaotic ring‐oscillator‐based TRNGs, and further, it is verified that the generated bit sequences pass all TRNG tests in National Institute of Standards and Technology (NIST SP 800‐22). The proposed TRNG is implemented in two FPGA families: Nexys 4 DDR XC7A100TCSG‐1 (Artix 7) and Basys 3 XC7A35T1CPG236C (Artix 7) Xilinx Vivado v.2017.3 design suite. 相似文献
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Aditya Japa Manoj Kumar Majumder Subhendu K. Sahoo Ramesh Vaddi 《International Journal of Circuit Theory and Applications》2020,48(4):524-538
Tunnel field-effect transistor (TFET) exhibits significant p-i-n forward leakage with the increase in drain-to-source voltage bias, and this adversely impacts the power consumption and reliability of TFET digital circuits. This work presents low-power circuit techniques that result in novel compact gates and recommends tristate gates to mitigate the leakage effects. The proposed novel compact gates and tristate gates demonstrate two and six times lower power consumption compared with conventional TFET transmission gates with enhanced reliability. Further, this work introduces a new design methodology that leverages TFET p-i-n forward leakage for hardware obfuscation applications. Utilizing the proposed design methodology, the optimization of 40% and 80% in area and power consumption of hardware security primitives like true random number generators is also accomplished. 相似文献
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S. Callegari R. Rovatti G. Setti 《International Journal of Circuit Theory and Applications》2005,33(1):1-16
True random sources are not implementable in digital hardware, so that many practical applications have historically relied on pseudo‐random generators in order to avoid the potentially long prototyping times and the costs of dedicated analog design. However, pseudo‐random sources have liabilities that make them hardly suitable for some tasks (notably security related ones). Previous attempts to conciliate security, cost‐effectiveness, and rapid development included the exploitation of the analog accessory parts often present on programmable devices. In these designs some analog blocks are used for their side effects (noise amplification) rather than for their originally intended behaviour. Conversely, here we report a direct implementation of a true random source on programmable, low‐cost, general‐purpose hardware, where all blocks are used only for their nominal function. To the best of the authors' knowledge, this is the first proposal of this sort. The design exploits an FPAA, and is based on a non‐linear system exhibiting chaotic behaviour. Measures confirm the correct operation, high throughput, and robustness of the system. Copyright © 2005 John Wiley & Sons, Ltd. 相似文献
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Murat Alcin Ismail Koyuncu Murat Tuna Metin Varan Ihsan Pehlivan 《International Journal of Circuit Theory and Applications》2019,47(3):365-378
It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in current literature. This paper provides a novel type of high-speed TRNG based on chaos and ANN implemented in a Xilinx field-programmable gate array (FPGA) chip. The paper consists of two main parts. In the first part, chaos analyses of Pehlivan-Uyaroglu_2010 chaotic system (PUCS) have been accomplished to prove that PUCS operates in chaotic regime. So PUCS can be an efficient alternative to the entropy source for classical TRNGs. In the second part, the hardware design of the proposed TRNG has been created using VHDL in Xilinx platform. As a result, the implemented TRNG offers throughput up to 115.794 Mbps. Besides, the generated random numbers have been tested with the FIPS 140-1 and NIST 800.22 test suites. The high quality of generated true random numbers have been confirmed by passing all randomness tests. The results have shown that the proposed system can provide not only high throughput but also high quality random bit sequences for a wide variety of embedded cryptographic applications. 相似文献