Effect of Hygrothermal Aging on Interfacial Reliability of Silicon/Underfill/FR-4 Assembly

The reliability issues have been converted to the underfill adjacent interfaces since the introduction of the underfill to flip chip package in 1990's. Both thermal cycling and hygrothermal conditioning severely attack the interfaces to de- laminate. The moisture migrating into the underfill decreases the adhesion strength, swells to deform the assembly, and weakens the mechanical and thermal properties of the material. In this study, interfacial reliability of a silicon/underfill/FR-4 assembly exposed at 85degC/85%RH was studied using moire interferometry and micro-digital image speckle correlation (mu-DiSC) techniques. A thermal aging study was simultaneously performed to understand the long-term reliability of the assembly. The results showed that the thermal aging relieved the stresses induced by hygrothermal swelling mismatch between dissimilar materials involved, whereas increased the strains induced by hygrothermal swelling. It indicated the time effect is not negligible when the assembly is subjected to the moisture conditioning, otherwise, the deformation induced by the swelling could be overestimated. The mu-DiSC technique was applied to measure the critical interfacial fracture toughness of the silicon/underfill interface. The results showed that the moisture could significantly reduce the interfacial strength due to the break of hydrogen bonding. By combining the moire and mu-DiSC results, it was concluded that the hygrothermal loading could increase the possibility of interfacial delamination in a flip chip package. Finally, the morphologies of the fractured surface were studied with the aid of scanning electron microscope. Remarkable changes of the failure mode were observed.     

Reliability study of underfill/chip interface under accelerated temperature cycling (ATC) loading

Interface reliability issue has become a major concern in developing flip chip assembly. The CTE mismatch between different material layers may induce severe interface delamination reliability problem. In this study, multifunctional micro-moiré interferometry (M³I) system was utilized to study the interfacial response of flip chip assembly under accelerated thermal cycling (ATC) in the temperature range of −40 °C to 125 °C. This in-situ measurement provided good interpretation of interfacial behavior of delaminated flip chip assembly. Finite element analysis (FEA) was carried out by introducing viscoelastic properties of underfill material. The simulation results were found to be in good agreement with the experimental results. Interfacial fracture mechanics was used to quantify interfacial fracture toughness and mode mixity of the underfill/chip interface under the ATC loading. It was found that the interfacial toughness is not only relative to CTE mismatch but also a function of stiffness mismatch between chip/underfill.     

Adhesion measurement for electronic packaging applications usingdouble cantilever beam method

Multilayers and interfaces are ubiquitous in microelectronics devices, interconnect and packaging structures. As the interface integrity becomes the major concern of performance, yield, and reliability, the need to evaluate the fracture and delamination behavior of various interfaces increases. This work focused on quantifying interfacial adhesion performance of a typical electronics packaging structure, flip-chip-on-organic-substrate. A series of experiments and analyzes were conducted to investigate the adhesion and fracture behaviors of the underfill/silicon and underfill/organic substrate interfaces. The experimental techniques for the interfacial fracture experiments were developed to produce the double-cantilever-beam (DCB) specimens and to establish a reproducible testing protocol. To extract the interfacial fracture energies, a closed-form solution was developed based on a beam-on-elastic-foundation model. A two-dimensional elastoplastic finite element analysis (FEA) model was also implemented to examine effects of mode-mixity, thermal/residual stresses, and underfill plasticity. The techniques allow for reproducible determination of underfill/printed circuit board (PCB) and underfill/silicon chip interfacial adhesion strength. The developed techniques are also readily applicable to evaluate interfacial adhesion performance for many other similar electronic packaging systems. This provides capabilities in optimizing material selections and process conditions to improve interfacial adhesion performance, Additionally, the interfacial fracture energy measured with high accuracy can provide a basis for realistic modeling of thermo-mechanical reliability of electronic components     

Silicon and Nanoscale Metal Interface Characterization Using Stress-Engineered Superlayer Test Methods

Thin film layers are utilized in emerging microelectronics, optoelectronics, and microelectromechanical systems (MEMS) devices. Typically, these thin film layers are composed of different materials with dissimilar properties. A common mode of failure for thin films is delamination caused by external loading or intrinsic stress present in the materials. To characterize bonded thin film material systems, it is necessary to measure the interfacial fracture toughness. When material thicknesses approach micro- and nanoscales, interfacial fracture toughness measurement is a challenging task. Accordingly, innovative test techniques need to be developed to study interfacial fracture parameters. The ongoing research at Georgia Institute of Technology is developing fixtureless delamination test techniques that can be used to measure interfacial properties of micro- and nanoscale thin films. The single substrate decohesion test (SSuDT) and the single-strip decohesion Test (SSDT) are such fixtureless tests under development. In these tests, a thin film interface material of interest is deposited on a substrate. Then, delamination is driven by a superlayer material on top of the interface material. This superlayer material is sputter deposited and has high intrinsic stress. A deposited release layer material allows for the contact area between the interface material and the substrate to be controlled. These tests differ in geometry, but share the same generic methodology and can be used for a number of material systems over a wide range of mode mixities. This paper presents the methodology and implementation of the SSuDT and SSDT tests and compares results to better understand their scope. A case study of the interfacial fracture toughness as a function of mode mixity for titanium and silicon interface was performed.      

Numerical modeling of interfacial delamination propagation in anovel peripheral array package

Interfacial delamination, due to the presence of dissimilar material systems, is one of the primary concerns in electronic package designs. The mismatch in the coefficient of thermal expansion between the different layers in the package can generate high interfacial stresses upon heating or cooling of the structure during fabrication, assembly, or in field use. These stresses, if sufficiently large, can compromise the adhesive integrity of the interface. The propagation of the resulting delamination along an interface can degrade or completely destroy the functionality of the system. The focus of this study is to examine the potential for interfacial delamination propagation in current and future versions of a novel peripheral array package. Two-dimensional (2-D) and three-dimensional (3-D) numerical models were constructed of this package with cracks embedded along a critical interface. The energy release rate associated with interfacial fracture was determined by employing the global energy balance and the crack closure technique. The fracture mode mixity was determined using the crack surface displacement method. These critical fracture parameters were compared with experimentally determined interfacial fracture toughness data to determine the possibility of delamination growth. A material parametric study was also completed using the numerical models with pre-existing delaminations to identify material property trends that would lower the potential for failure. Also, the effect of plastic behavior on interfacial crack growth was studied through J-integral calculations     

Thermal fracture toughness measurement for underfill during temperature change

The failure of organic packages during thermal cycling is often associated with failure of the underfill by fracture. The fracture toughness of underfills measured by applying a mechanical stresses to the material at a constant temperature is used as a measure of the propensity of underfill fracture. However, this fracture toughness does not take into account transient temperature effects during thermal cycling. To include temperature effects a fracture toughness induced by applying thermal stresses is defined and a method to measure this thermally induced fracture toughness is described. Results on two commercial underfills are presented. Comparison of the conventional, mechanically induced fracture toughness and the new, thermally induced fracture toughness shows that underfill fracture toughness including thermal effects is significantly smaller than the conventional values. This indicates that the mechanical toughness method overestimates the underfill/package reliability that becomes subject to temperature change. The difference is explained using fracture energy concept.     

Adhesion and toughening mechanisms at underfill interfaces forflip-chip-on-organic-substrate packaging

The flip chip-on-organic-substrate packaging technology utilizes a particulate reinforced epoxy as the underfill (UF) to adhere the chip to the package or board, Although the use of underfill encapsulation leads to improved reliability of flip-chip solder interconnections, delamination at various interfaces becomes a major concern for assembly yield loss and package reliability. In spite of their importance, the adhesion and fracture behaviors of the underfill interfaces have not been investigated until recently. Considerable controversy exists over the effects of underfill formulation and the adhesion and toughening mechanisms of the interfaces. The present work focuses on investigating the effects of several key variables on the interface adhesion strengths for UF/chip and UF/organic substrate systems. These variables are underfill organosilane content, filler particle content, rubber particle content, surface morphology and chemistry of the chip and organic substrates. The approach of this study is to measure the effect of these variables on the interfacial fracture energy using the double-cantilever-beam (DCB) techniques. The results demonstrate that the underfill interfacial adhesion and fracture characteristics are controlled by several distinct but competing mechanisms, such as formation of primary bonds, crack-pinning by glass fillers, debonding of glass filler from epoxy matrix (defect formation), and cavitation and shearing induced by rubber particles. Fundamental understanding of the interfacial adhesion and toughening mechanisms can provide guidance for developing new processes and materials to enhance interfacial adhesion and reliability     

Interfacial fracture toughness for delamination growth predictionin a novel peripheral array package

The objective of this study is to predict interfacial delamination propagation that may inhibit the performance of a novel surface mountable, high input/output (I/O) electronic package. Incorporation of such predictions in the design phase of the package can lead to judicial selection of materials and geometric parameters such that the interfacial delamination based failures can be avoided. This, in turn, leads to significant cost savings and shorter time-to-market due to the shortening of the prototyping and qualification testing phases. The focus of the present study is the prediction of potential delaminations at the encapsulant-backplate interface in a very small peripheral array (VSPA) package during manufacturing. The delamination growth prediction is based on the comparison of interfacial fracture parameters obtained from the numerical simulations to appropriate critical values determined experimentally using controlled fracture toughness tests. In this paper, the fracture toughness of the encapsulant/backplate interface is characterized using a fracture toughness test that requires simple test specimen, fixture and loading geometries. The critical interfacial fracture toughness and the fracture mode mixity are determined using closed-form and finite element analyses of the test specimen geometries, taking into consideration the effects of thermo-mechanical residual stresses resulting from the test specimen fabrication process. Furthermore, an experimental characterization of the encapsulant material is also conducted in order to assess the effects of its time- and temperature-dependent thermomechanical response on the fracture toughness of the encapsulant-backplate interface     

Effects of underfill material properties on the reliability ofsolder bumped flip chip on board with imperfect underfill encapsulants

Three different types of underfill imperfections were considered; i.e., (1) interfacial delamination between the underfill encapsulant and the solder mask on the PCB (crack initiated at the tip of underfill fillet), (2) interfacial delamination between the chip and the underfill encapsulant (crack initiated at the chip corner), and (3) the same as (2) but without the underfill fillet. Five different combinations of coefficient of thermal expansion (CTE) and Young's modulus with the aforementioned delaminations were investigated. A fracture mechanics approach was employed for computational analysis. The strain energy release rate at the crack tip and the maximum accumulated equivalent plastic strain in the solder bumps of all cases were evaluated as indices of reliability. Besides, mechanical shear tests were performed to characterize the shear strength at the underfill-solder mask interface and the underfill-chip passivation interface. The main objective of the present study is to achieve a better understanding in the thermo-mechanical behavior of flip chip on board (FCOB) assemblies with imperfect underfill encapsulants     

Numerical Investigation of Underfill Failure Due to Phase Change of Pb-Free Flip Chip Solders During Board-Level Reflow

In this paper, the effects of phase change of Pb-free flip chip solders during board-level interconnect reflow are investigated using numerical technique. Most of the current Pb-free solder candidates are based on Sn and their melting temperatures are in the range of 220 $^{circ}$ C–240 $^{circ}$ C. Thus, Pb-free flip chip solders melt again during subsequent board-level interconnect (BGA) reflow cycle. Since solder volume expands as much as 4% during the phase change from solid to liquid, the volumetric expansion of solder in a predefined volume by chip, substrate, and underfill creates serious reliability issues. One issue is the shorting between neighboring flip chip interconnects by the interjected solder through underfill crack or delaminated interfaces. The authors have observed the interjection of molten solder and the interfacial failure of underfill during solder reflow process. In this paper, a flip chip package is modeled to quantify the effect of the volumetric expansion of Pb-free solder. Three possible cases are investigated. One is without existence of micro crack and the other two are with the interfacial crack between chip and underfill and the crack through the underfill. The strain energy release rate around the crack tip calculated by the modified crack closure integral method is compared with interfacial fracture toughness. Parametric studies are carried out by changing material properties of underfill and interconnect pitch. Also, the effects of solder interconnect geometry and crack length are explored. For the case with interfacial crack, the configuration of a large bulge with small pitch is preferred for the board-level interconnect, whereas a large pitch is preferred for cracks in the mid plane of the underfill.      

Characterization of underfill/substrate interfacial toughnessenhancement by silane additives

This work experimentally measures the apparent fracture toughness of the interfaces between epoxy-based underfill materials and various substrates including aluminum, polyimide, BCB, and printed wiring boards (FR-4) with solder mask. A small amount of silane coupling agent is added to the base underfill in order to form various underfill derivatives, and double layer specimens with preexisting interfacial cracks are prepared for four-point bending tests. The measurements are qualitatively correlated to each silane additive. The purpose of adding silane additives was to enhance the adhesion; the enhancement of interfacial toughness was found to strongly depend on the type of substrate. The results of this study have important implications in flip-chip reliability where interfacial cracking is one of the major failure modes     

Underfill selection methodology for fine pitch Cu/low-k FCBGA packages

A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fracture toughness, coefficient of moisture expansion, flowability, delamination performance and filler settlement were considered. Driving stresses for package failure were also included as a factor of consideration, which clearly depends on the package size and geometry. Based on the approach adopted, underfill material that is suitable for 35 × 35 mm² packages with 15 mm die size and 45 × 45 mm² packages with 21 mm die size was selected. Target value for underfill properties has also been revised.     

Impact of Thermal,Moisture, and Mechanical Loading Conditions on Interfacial Fracture Toughness of Adhesively Bonded Joints

Interfacial delamination is a common failure mode in multilayered IC packages. In this paper, an experimental technique using Brazil-nut specimens is employed to determine the interfacial fracture toughness of an adhesively sandwiched joint with the introduction of edge interfacial crack. The design of experiments (DOE) is applied to study variations in strain rates and the thickness of the sandwich structure. In addition, the effects of moisture content and temperature on the interfacial adhesion are investigated. For the DOEs conducted, as the loading angle increases from 20° to 90°, the interfacial fracture toughness decreases. The fracture toughness and its corresponding mode mixity are determined from the measured critical load by finite element modeling computation.     

Investigation of interfacial delamination of a copper-epoxy interface under monotonic and cyclic loading: experimental characterization

Interfacial delamination is of important concern for multilayered microelectronic packaging structures, as it is one of the most common failures observed in microelectronic packages. To predict interfacial delamination propagation under both static and cyclic loading, one needs to characterize interfacial properties. Key parameters for characterizing an interface include interfacial fracture toughness, interfacial fracture resistance, onset of delamination from an initial interface crack, and fatigue crack propagation (FCP) rate. The objective of this study is to experimentally investigate the interfacial properties of a copper-epoxy interface. Such an interface is one of the most common features seen in multilayered integrated substrates. Amenable to thin film process, sandwich double cantilever beam (DCB) specimens have been designed and fabricated in clean-room environment. Standard tensile tests have been preformed for determining the interfacial fracture toughness and, with monitoring the crack length against the applied force, interfacial fracture resistance. Fatigue tests have also been conducted in studying the onset of delamination from an interfacial delamination starter and the follow-up fatigue crack propagation (FCP) of an interfacial crack along the copper-epoxy interface.     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

Adhesion issues in flip-chip on organic modules

Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses     

Influence of temperature and humidity on adhesion of underfills for flip chip packaging

This paper systematically discusses the influence of temperature and humidity on the adhesion performance of underfill material (epoxy cured with acid anhydride), which was evaluated by die shear test after exposure to various conditions. The inherent adhesion strength between the underfill and passivation is not affected significantly by thermal cycling between -55/spl deg/C and 125/spl deg/C for 1000 cycles. The adhesion strength of underfill material decreases with the increase of test temperature in the investigated range, due to the decrease of modulus of the underfill with the increase of temperature. A sharp decrease in adhesion strength occurs as temperature increases toward the glass transition temperature of the underfill material. Adhesion strength of underfill with different passivation materials decreases after aging in a high temperature and high humidity environment. The extent of the decrease depends on underfill formulation and the hydrophilicity of the passivation material. Hydrophilic passivation such silicon oxide (SiO/sub 2/) and silicon nitride (Si/sub 3/N/sub 4/) shows much more severe adhesion degradation than hydrophobic passivation such as benzocyclobutene (BCB) and polyimide (PI). Adhesion degradation is slower than moisture diffusion. The adhesion stability for hydrophilic passivation can be successfully improved by use of a coupling agent such as silane that introduces stable chemical bonds at interface.     

Investigation of the underfill delamination and cracking inflip-chip modules under temperature cyclic loading

In this paper, stress singularity in electronic packaging is described and three general cases are summarized. The characteristics of each stress singularity are briefed. In order to predict the likelihood of delamination at a bimaterial wedge, where two interfaces are involved, a criterion is proposed and the corresponding parameters are defined. The propagation of a crack inside a homogeneous material with the effects of delamination and stress singularity is predicted by the maximum hoop stress criterion. The proposed criteria are adopted in the analysis of a flip-chip with underfill under thermal cyclic loading. A finite element (FE) model for the package is built and the proper procedures in processing FE data are described. The proposed criterion can correctly predict the interface where delamination is more likely to occur. It can be seen that the opening stress intensity factor along the interface (or peeling stress) plays a very important role in causing interfacial failure. The analytical results are compared with experimental ones and good agreement is found. The effects of delamination and cracking inside the package on the solder balls are also mentioned. Further investigation into the fatigue model of the underfilled solder ball is discussed