Gate length dependence of bias temperature instability behavior in short channel SOI MOSFETs

In this work, a comprehensive study of the bias temperature instability (BTI) degradation has been performed on SOI MOSFETs with various gate lengths (from 30 nm to 150 nm). For both nMOSFETs and pMOSFETs, the BTI degradation is alleviated when the gate length decreases. A new model was proposed to explain the observed gate length dependence of the BTI degradation. The decrease in the BTI degradation of MOSFETs with shorter gate length is caused by the decrease in normal electric field across the interface of Si-dielectric, which was concept-proofed by TCAD simulations.     

A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs)

In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (V_d). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz.     

Analysis of the electrical characteristics of power LDMOSFETs having different design parameters under various temperature

In this paper, we have investigated the electrical characteristics of power lateral double-diffused MOSFETs (LDMOSFETs) having different gate lengths (2.1–3 μm) and drift lengths (6.6–12.6 μm) in the temperature range 100–500 K. The results of this study indicate that gate length and drift region length have a great effect on electrical characteristics, but they have little effect on temperature dependence. The specific on-resistance and the off-state breakdown voltage increase with temperature. The result shows that the specific on-resistance increases exponentially with the exponent 2.2 and, by contrast, the off-state breakdown voltage increases linearly with a slope of 100 mV/K (drift region concentration of measured device: 2×10¹⁵ cm⁻³). As a result, R_on/BV, known for a figure of merit of power device, increases with temperature.     

Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K

The linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed in long channel nanowire MOSFETs with different fin width (W_FIN), from quasi-planar structures (W_FIN = 10 μm) to narrow devices (9.5 nm), operating as single-transistor amplifiers from room temperature down to 100 K. The total, second and third order harmonic distortions (THD, HD2 and HD3, respectively) are extracted using the Integral Function Method (IFM). The analysis is divided in two parts. First, a fixed input signal is applied at the gate of the single-transistor amplifiers and, then, the output signal is fixed. Transport parameters such as effective mobility (μ_eff), mobility degradation coefficient (θ) and series resistance (R_S) have been extracted down to 100 K and correlated to the distortion to explain linearity peaks behavior with temperature and fin width. Narrow transistors have shown improved linearity mainly due to higher intrinsic voltage gain (A_V) considering the entire temperature range. Low temperature operation has shown to degrade the linearity characteristics of both wide and narrow NW MOSFETs.     

Reliability study of fiber-coupled photodiode module for operation at 4 K

The reliability of a photodiode module intended for operation at 4 K was investigated. Flip-chip bonded photodiodes and an adhesively bonded optical fiber attachment structure were considered. Finite element simulations of the thermomechanical stress were used to evaluate the stresses in different design configurations. Results showed that issues with chip cracking in silicon were eliminated by proper selection of component materials. Photodiode modules survived thermal cycling to 77 K and extended operation in 4 K.     

Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process

The breakdown failure mechanisms for a family of power AlGaN/GaN HEMTs were studied. These devices were fabricated using a commercially available MMIC/RF technology with a semi-insulating SiC substrate. After a 10 min thermal annealing at 425 K, the transistors were subjected to temperature dependent electrical characteristics measurement. Breakdown degradation with a negative temperature coefficient of ?0.113 V/K for the devices without field plate was found. The breakdown voltage is also found to be a decreasing function of the gate length. Gate current increases simultaneously with the drain current during the drain-voltage stress test. This suggests that the probability of a direct leakage current path from gate to the 2-DEG region. The leakage current is attributed by a combination of native and generated traps/defects dominated gate tunneling, and hot electrons injected from the gate to channel. Devices with field plate show an improvement in breakdown voltage from ～40 V (with no field plate) to 138 V and with lower negative temperature coefficient. A temperature coefficient of ?0.065 V/K was observed for devices with a field plate length of 1.6 μm.     

Effects of the post nitridation anneal temperature on performances of the nano MOSFET with ultra-thin (<2.5 nm) plasma nitrided gate dielectric

A post nitridation annealing (PNA) is used to improve performances of the metal oxide semiconductor field effect transistor (MOSFETs) with nano scale channel and pulsed radio frequency decoupled plasma nitrided ultra-thin (<50 Å) gate dielectric. Effects of the PNA temperature on the gate leakage and the device performances are investigated in details. For a n-type MOSFET, as the PNA temperature rises from 1000 to 1050 °C, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements in performance are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT. Most of all, the high temperature PNA does not degrade the gate oxide integrity.     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

Fully aromatic polyimide gate insulators with low temperature processability for pentacene organic thin-film transistors

This paper demonstrates the effects of the imidization ratio of polyimide gate insulators on the performance of organic thin-film transistors (OTFTs). We report the synthetic results of polyimide films imidized at a temperature of 200 °C along with an easily removed organic base catalyst (1,8-diazabicyclo[5.4.0]undec-7-ene, DBU), and their application in gate insulators of organic thin-film transistors. The degree of imidization increased to almost 100% after a thermal treatment at 200 °C for 40 min in the presence of DBU. The performance of the pentacene OTFT dramatically improved by using low temperature cured polyimide film as the gate insulator.     

Lithography scaling issues associated with III–V MOSFETs

In this work we investigate fabrication issues associated with scaling down the gate length and source drain contact separation of a III–V MOSFET. We used high resolution electron-beam lithography and lift-off for gate and ohmic contact patterning to fabricate gate-last lithographically-aligned MOSFETs. This work considers the effect of variations in resist thickness on gate lengths and also the fabrication of long narrow gaps using electron-beam lithography. The study showed that the effect of resist thickness variation on metal linewidth is insignificant. A difference of around 2–3 nm was found between PtAu linewidths fabricated using 150 and 280 nm thick resist. A VB6 lithography tool was found to be useful for linewidth measurements. We showed that the choice of resist is critical to gap formation, and that PMMA is not well suited to this task.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Compact model of output conductance in nanoscale bulk MOSFET based on 2D analytical calculations

In this paper we present a new way to calculate channel length shortening in saturation for standard bulk MOSFETs by solving 2D Poisson’s equation. Compared to most existing models, we use in our model only physically meaningful and geometry-independent fitting parameters, which gives our model a good scalability. 2D Poisson is solved in analytical closed form by applying the conformal mapping technique. This gives the model the advantage additionally to its application in circuit simulations to be useful in calculating device scaling behavior. Our model describes the output conductance of MOSFETs down to 50 nm effective channel length very well.     

Proton-induced SEU in SiGe digital logic at cryogenic temperatures

We present the first experimental results confirming the increased SEE sensitivity of SiGe digital bipolar logic circuits operating in a 63 MeV proton environment at cryogenic temperatures. A 3× increase in both the error-event and bit-error cross sections is observed as the circuits are cooled from 300 K to 77 K, with error signature analyses indicating corresponding increases in the average number of bits-in-error and error length over data rates ranging from 50 Mbit/s to 4 Gbit/s. Single-bit-errors dominate the proton-induced SEU response at both 300 K and 77 K, as opposed to the multiple-bit-errors seen in the heavy-ion SEU response. Temperature dependent substrate carrier lifetime measurements, when combined with calibrated 2 D DESSIS simulations, suggest that the increased transistor charge collection at low temperature is a mobility driven phenomenon. Circuit-level RHBD techniques are shown to be very efficient in mitigating the proton- induced SEU at both 300 K and 77 K over the data rates tested. These results suggest that the circuit operating temperature must be carefully considered during component qualification for SEE tolerance and indicate the need for broad-beam heavy-ion testing at low temperatures.     

New insight on negative bias temperature instability degradation with drain bias of 28 nm High-K Metal Gate p-MOSFET devices

The degradation of negative bias temperature instability (NBTI) on 28 nm High-K Metal Gate (HKMG) p-MOSFET devices under non-uniform stress condition has been systematically studied. We found the asymmetry between forward and reverse Idsat shift under non-uniform stress condition is significant for long channel devices even under low drain bias stress (e.g., Vds = −0.1 V and gate channel length L = 1 μm), and seems to be dominated by a minimally required critical length (L = 0.2 μm derived from the experimental data). To the authors’ best knowledge, these are new phenomena reported. We attribute these anomalous NBTI characteristics with drain bias to the local self-heating (LSH) activated NBTI degradation mechanism. One semi-empirical analytical model, which fits well with our experimental data, is then proposed in this paper.     

Reliability of Diode-Integrated SiC Power MOSFET(DioMOS)

Status of the reliability study on silicon carbide (SiC) power MOS transistors is presented. The SiC transistors studied are diode-integrated MOSFETs (DioMOS) in which a highly doped n-type epitaxial channel layer formed underneath the gate oxide acts as a reverse diode and thus an external Schottky barrier diode can be eliminated. The novel MOS device can reduce the total area of SiC leading to potentially lower cost as well as the size of the packaging. After summarizing the issues on reliability of conventional SiC MOS transistors, the improvements by the newly proposed DioMOS with blocking voltage of 1200 V are presented. The I–V characteristic of the integrated reverse diode is free from the degradation which is typically observed in conventional pn-junction-based body diode in SiC MOS transistors. The improved quality of the MOS gate in the DioMOS results in very stable threshold voltage within its variation less than 0.1 V even after 2000 h of serious gate voltage stresses of + 25 V and − 10 V at 150 °C. High temperature reverse bias test (HTRB) shows very stable off-state and gate leakage current up to 2000 h under the drain voltage of 1200 V at 150 °C. These results indicate that the presented DioMOS can be applied to practical switching systems free from the reliability issues.     

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO₂, TiN/SiO₂ or N⁺ poly-Si/SiO₂ are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO₂ gate stack demonstrates the best I_ON/I_OFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V.     

Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

All-digital thermal distribution measurement on field programmable gate array using ring oscillators

In this paper, a digital method for transient temperature distribution measurement of field programmable gate array (FPGA)-based systems is proposed. The smart thermal sensors used rely on correspondence between the delay and temperature in a ring oscillator. The tested temperature was converted into a time signal with a thermally-sensitive width. The output frequency is read out by a counter with a scan path, and then, transited to PC by a Universal Serial Bus (USB) interface. We capture the infrared images of the FPGA chip by infrared camera. The images were compared with the thermal map of the die constructed using an array of sensors. The tested temperature error varies by less than 1.6 °C in the range from 20 °C to 90 °C, and the maximum sampling rate is 330 Hz.     

Temperature stability of a piezoresistive MEMS resonator including self-heating

Temperature stability of a piezoresistive 1.5 μm thin SOI resonator at 74 MHz is presented. As compared to capacitive resonators the self-heating due to the bias current causes a further decrease of the resonator frequency, in addition to the well-known dependency on ambient temperature. The interpretation of the resonance frequency as a device temperature is not obvious anymore under self-heating due to the inhomogeneous temperature distribution.     

Thermal/luminescence characterization and degradation mechanism analysis on phosphor-converted white LED chip scale packages

According to the requirements on minimizing the package size, guaranteeing the performance uniformity and improving the manufacturing efficiency in LEDs, a Chip Scale Packaging (CSP) technology has been developed to produce white LED chips by impressing a thin phosphor film on LED blue chips. In this paper, we prepared two types of phosphor-converted white LED CSPs with high color rendering index (CRI > 80, CCT ~ 3000 K and 5000 K) by using two mixed multicolor phosphor materials. Then, a series of testing and simulations were conducted to characterize both short- and long-term performance of prepared samples. A thermal analysis through both IR thermometry and electrical measurements and thermal simulation were conducted first to evaluate chip-on-board heat dissipation performance. Next, the luminescence mechanism of multicolor phosphor mixtures was studied with the spectral power distribution (SPD) simulation and near-field optical measurement. Finally, the extracted features of SPDs and electrical current-output power (I-P) curves measured before and after a long-term high temperature accelerated aging test were applied to analyze the degradation mechanisms. The results of this study show that: 1) The thermal management for prepared CSP samples provides a safe usage condition for packaging materials at ambient temperature; 2) The Mie theory with Monte-Carlo ray-tracing simulation can be used to simulate the SPD of Pc-white LEDs with mixed multicolor phosphors; 3) The degradation mechanisms of Pc-white LEDs can be determined by analyzing the extracted features of SPDs collected after aging.