New nonvolatile memory with charge-trapping sidewall

This letter reports on the development of a new nonvolatile memory with charge-trapping sidewalls using sub-0.1-/spl mu/m MOSFET technology. This memory has silicon nitride (SiN) sidewalls at both sides of the gate to store the charge. We have found that optimization of the p-n junction edge with the sidewall enables writing, reading, and erasing a 2-bit charge independently. The Vth window, which is the difference in the threshold voltage between forward and reverse read, was about 0.8 V with a gate length of 0.4 /spl mu/m. In addition, it is scalable to 40 nm of the gate length. This device is attractive not only from the prospects of future size reduction, but also its compatibility with CMOS process.     

Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices

A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of localized trapped-charge in the nitride read-only memory (NROM) device. The charge distribution is determined by iteratively fitting simulated subthreshold and gate induced drain leakage (GIDL) currents to measurements. It is shown that the subthreshold and the GIDL measurements are sensitive to charge trapped over the n+ junction edge. Their characteristics are determined by the trapped charge width, density and location and the associated fringing field. Extremely high sensitivity of the GIDL measurement to localized charge over the n+ junction is demonstrated. The extracted charge distribution width is shown to be /spl sim/40 nm, located over the junction edge.     

Organic nonvolatile memory devices utilizing intrinsic charge-trapping phenomena in an n-type polymer semiconductor

Charge trapping is an undesirable phenomenon and a common challenge in the operation of n-channel organic field-effect transistors. Herein, we exploit charge trapping in an n-type semiconducting poly (naphthalene diimide-alt-biselenophene) (PNDIBS) as the key operational mechanism to develop high performance, nonvolatile, electronic memory devices. The PNDIBS-based field-effect transistor memory devices were programmed at 60 V and they showed excellent charge-trapping and de-trapping characteristics, which could be cycled more than 200 times with a current ratio of 10³ between the two binary states. Programmed data could be retained for 10³ s with a memory window of 28 V. This is a record performance for n-channel organic transistor with inherent charge-trapping capability without using external charge trapping agents. However, the memory device performance was greatly reduced, as expected, when the n-type polymer semiconductor was end-capped with phenyl groups to reduce the trap density. These results show that the trap density of n-type semiconducting polymers could be engineered to control the inherent charge-trapping capability and device performance for developing high-performance low-cost memory devices.     

Gadolinium-based metal oxide for nonvolatile memory applications

In this study, the memory characteristic of a gadolinium (Gd)-based oxide charge storage layer was demonstrated. The metal/oxide/high-k/oxide/silicon (MOHOS)-type memories were fabricated by using two different charge storage layers. The Gd₂O₃ nanocrystal (Gd₂O₃-NC) was used as a charge storage layer due to the discrete nodes, while the HfGdO high-k material was used as a charge storage layer due to the existence of discrete traps. In the case of Gd₂O₃-NC memory, a combination of X-ray photoelectron spectroscopy (XPS) and ultraviolet (UV)–visible spectrophotometer analysis was used in this study to extract the valence band location and the band-gap of the Gd₂O₃-NC layer. The retention characteristic was also analyzed to extract the trapping level in Gd₂O₃-NC, based on the relationship between trapping energy and discharging time. A band diagram was created to characterize the memory effect of the Gd₂O₃-NC memory. In the case of HfGdO SONOS-type memory, the electrical and physical studies were conducted for HfGdO charge-trapping layers deposited by a dual-sputtered method for silicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile memory. The Hf/Gd dual-sputtered power ratio and the Ar/O₂ gas flow ratio were optimized. It was observed that the nonstoichiometric GdO (2 0 0) structure may be the main charge-trapping site for the memory. The memory samples with Hf/Gd = 150/150 and Ar/O₂ = 20/5 exhibited better electrical performance. A physical model is proposed to further explain the retention mechanism.     

Sol-Gel processing of Nb-doped Pb(Zr,Ti)O3 thin films for ferroelectric memory applications

The ferroelectric properties of Nb-doped PZT thin films prepared by a sol-gel method were evaluated relative to memory device application requirements. Within the range of 0 to 4 mol %, Nb-doping of PZT compositions near the morphotropic phase boundary region (i.e. PZT 53/47) enhanced overall ferroelectric properties by reducing the te-tragonal distortion of the unit cell. A 4 mol % Nb-doped PZT 53/47 thin film (0.26 μm) had a coercivity of 8 V/ μm, a remanence ratio of 0.54, a switchable polarization of 45 μC/cm², and a specific resistivity of 3 x 10⁹ Ω-cm. Nb-doping levels in excess of 5 mol had a detrimental effect on the resulting thin film ferroelectric properties. X-ray diffraction (XRD) analysis of highly doped films showed development of a significant PbO phase accompanied by diffraction line broadening of the perovskite phase. As such, it was postulated that the creation of excessive lead vacancies in the PNZT lattice resulted in PbO accumulation at the grain boundaries which impeded grain growth, and hence, adversely affected ferroelectric switching performance. The fatigue performance of the sol-gel derived thin film capacitor system was a function of switching voltage. At switching fields sufficient to saturate the polarization, the endurance of the thin film capacitor was greater than 10⁹ cycles. Cycling with lower fields reduced endurance values, but in all cases, the switchable polarization decreased linearly with the logarithm of cycles. Nb-doping did not have a significant effect on the fatigue performance.     

Charge-trapping characteristics of BaTiO3 with and without nitridation for nonvolatile memory applications

The charge-trapping characteristics of BaTiO₃ with and without nitrogen incorporation were investigated based on Al/Al₂O₃/BaTiO₃/SiO₂/Si (MONOS) capacitors. The physical properties of the high-k films were analyzed by transmission electron microscopy and X-ray photoelectron spectroscopy. Compared with the MONOS capacitor with BaTiO₃ as charge-trapping layer, the one with nitrided BaTiO₃ showed higher program speed even at lower operating voltage (4.3 V at +8 V for 100 μs), better endurance property and smaller charge loss (charge loss of 10.6% after 10⁴ s at 85 °C), due to the nitrided BaTiO₃ film exhibiting higher charge-trapping efficiency caused by nitrogen incorporation and suppressed leakage induced by nitrogen passivation.     

Formation of stacked ruthenium nanocrystals embedded in SiO2 for nonvolatile memory applications

n metal oxide semiconductor (MOS)capacitors fabricated by the former method, which are much better than 4.6 Ⅴ and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.     

面向非挥发存储器应用的叠层Ru纳米晶材料的制备与特性

Two methods are proposed to fabricate stacked ruthenium （Ru） nanocrystals （NCs）： rapid thermal annealing （RTA） for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2-4 nm and 3 × 10^12 cm^-2 for the former method, compared to 3-7 nm and 2 ×10^12 cm^-2 for the latter. Because of the higher surface trap density and more uniform electron tunneling path between upper and lower Ru NCs, a 5.2 V memory window and 1 V after a period of 10 years are observed in metal oxide semiconductor （MOS） capacitors fabricated by the former method, which are much better than 4.6 V and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.     

Performance improvement of SONOS memory by bandgap engineering of charge-trapping layer

A significant improvement in device performance and reliability characteristics of silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory has been achieved. Superior endurance characteristic shows no sign of degradation even after 10/sup 6/ program/erase cycles and an extrapolated ten-year detection window of 1.4 V has been attained from retention measurement. The dramatic improvement results from a bandgap engineering of the SiN charge-trapping layer. With a gradual variation of the Si/N ratio from bottom to top of nitride film rather than uniform standard composition, a large number of highly accessible trapping levels are created in addition to the deepened barrier height between nitride and tunnel oxide that reduces back-tunneling probability. The proposed technique shall be valuable in pushing Flash memory technology into the next generation.     

High-density NiSi nanocrystals embedded in Al2O3/SiO2 double-barrier for robust retention of nonvolatile memory

NiSi nanocrystals of high density and good uniformity were synthesized by vapor–solid–solid growth in a gas source molecular beam epitaxy system using Si₂H₆ as Si precursor and Ni as catalyst. A metal–oxide–semiconductor memory device with NiSi nanocrystal–Al₂O₃/SiO₂ double-barrier structure was fabricated. Large memory window and excellent retention at both room temperature and high temperature of 85 °C were demonstrated.     

Resistance switching of the nonstoichiometric zirconium oxide for nonvolatile memory applications

The resistance switching behavior and switching mechanism of nonstoichiometric zirconium oxide thin films were investigated for nonvolatile memory application. The Pt/ZrO/sub x//p/sup +/-Si sandwich structure fabricated by reactive sputtering shows two stable resistance states. By applying proper bias, resistance switching from one to another state can be obtained. The composition in ZrO/sub x/ thin films were confirmed from X-ray photoelectron spectroscope (XPS) analysis, which showed three layers such as top stoichiometric ZrO/sub 2/ layer with high resistance, transition region with medium resistance, and conducting ZrO/sub x/ bulk layer. The resistance switching can be explained by electron trapping and detrapping of excess Zr/sup +/ ions in transition layer which control the distribution of electric field inside the oxide, and, hence the current flow.     

Resistive switching characteristics of Sm2O3 thin films for nonvolatile memory applications

This study investigates a sputtered Sm₂O₃ thin film to apply into a resistive random access memory device. The proposed device exhibits a stable resistance ratio of about 2.5 orders after 10⁴ cycling bias pulses and no degradation for retention characteristics monitored after an endurance test at 85 °C. The conduction mechanisms for low and high resistance states are dominated by ohmic behavior and trap-controlled space-charge limited current, respectively. The resistance switching is ascribed to the formation/rupture of conductive filaments.     

Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications

The self-assembly of metal nanocrystals including Au, Ag, and Pt on ultrathin oxide for nonvolatile memory applications are investigated. The self-assembly of nanocrystals consists of metal evaporation and selective rapid-thermal annealing (RTA). By controlling process parameters, such as the thickness of the deposited film, the post-deposition annealing temperatures, and the substrate doping concentration, metal nanocrystals with density of 2–4 × 10¹¹ cm⁻², diameter less than 8.1 nm, and diameter deviation less than 1.7 nm can be obtained. Observation by scanning-transmission electron microscopy (STEM) and convergent-beam electron diffraction (CBED) shows that nanocrystals embedded in the oxide are nearly spherical and crystalline. Metal contamination of the Si/SiO₂ interface is negligible, as monitored by STEM, energy dispersive x-ray spectroscopy (EDX), and capacitance-voltage (C-V) measurements. The electrical characteristics of metal, nanocrystal nonvolatile memories also show advantages over semiconductor counterparts. Large memory windows shown by metal nanocrystal devices in C-V measurements demonstrate that the work functions of metal nanocrystals are related to the charge-storage capacity and retention time because of the deeper potential well in comparison with Si nanocrystals.     

A novel nonvolatile memory cell suitable for both flash andbyte-writable applications

The structure, operation, and fabrication of a novel EEPROM/flash cell and array architecture are described. The cell is about half the size of the traditional floating gate tunnel oxide (FLOTOX) electrically erasable programmable read only memory (EEPROM) cell when laid out with the same design rules. This approach has a simple fabrication sequence and requires minimum overhead circuitry rendering it especially suitable for embedded applications. Characterization shows this approach has good retention and has million cycle endurance. Both read and write disturbs are characterized. There are large margins for both types of disturbs. In fact, the data on write disturbs show the disturb margins to be so large that disturb margin can be safely traded off for reduced stress on select transistors     

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si₃N₄) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO₂ as a blocking oxide in p-Si/SiO₂/AlN/SiO₂/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.     

Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications

Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiO_xN_y metal oxide NPs embedded in the HfO_xN_y high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O₂/N₂ ambient. Well-isolated TiO_xN_y NPs with a diameter of 5–20 nm, a surface density of ～3 × 10¹¹ cm^?2, and a charge trap density of around 2.33 × 10¹² cm^?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping.     

Electrical characterization of metal-ferroelectric (Mn-substituted BiFeO3)-insulator (HfO2)-semiconductor capacitors for nonvolatile memory applications

Metal-ferroelectric (Mn-substituted BiFeO₃)-insulator (HfO₂)-semiconductor has been fabricated by co-sputtering technique. X-ray diffraction (XRD) patterns have proven the existence of a substitution phase. The shift in binding energy of Fe ions and the change in atom ratio of Mn to Fe were analyzed by X-ray photoelectron spectra (XPS). The memory windows as functions of insulator film thickness and annealing temperature were compared. The maximum memory window is 3 V at the sweep voltage of 8 V with thicker (60 nm) HfO₂. The leakage current and the charge injection effect can be reduced with increasing the amount of substituting Mn for Fe-site.     

Charge storage and data retention characteristics of forming gas-annealed Gd2O3-nanocrystal nonvolatile memory cell

Trapping characteristics of forming gas-annealed Gd₂O₃ nanocrystal (Gd₂O₃-NC) memories were studied in detail. The trapping energy can be obtained from the data retention characteristic for different absolute temperature (T). The discharging time (τ) was extracted from a linear fitting curve of the data retention characteristic. From the relationship between ln(1/τT²) and 1/kT, the trapping energy was evaluated. Based on the retention properties, the discharge mechanisms of electrons in shallow and deep traps are correlated to the charge loss time. The observed values of the trapping energy demonstrated that deep traps are passivated by hydrogen species after FGA treatment; the difference of programming and erasing (P/E) speed of the memories between the samples with- and without-FGA treatment can be explained by this passivation process. A band diagram is proposed to explain the behavior of the charge loss mechanism. The fact that the endurance of Gd₂O₃-NC memories are not significantly degraded by the FGA treatment indicates that, though the deep traps are passivated by hydrogen, the reliability of the Gd₂O₃-NC memories is not affected. The method of FGA treatment enables the determination of the discharge process in nanocrystal memories.     

Reliable impurity trap memory with high charge trap efficiency using ultrathin SiO2 impurity host layer for nonvolatile memory application

We demonstrated reliable impurity trap memory (ITM) with high charge trap efficiency by incorporating only 1 nm-SiO₂ impurity host layer (IHL) between Al₂O₃ diffusion barrier layer and blocking oxide. While the ITM without IHL showed significant retention degradation as the amount of Ti impurity increased from 0.7 to 3 Å for enlarging memory window, the ITM with IHL showed stable retention characteristic which is charge loss less than 1 V after 10⁴ s at 85 °C. We postulated that the chemical reaction between Ti and SiO₂ induced three dimensionally-distributed impurity traps in IHL, which could result in the well-discrete stored charges in program mode.     

A nonvolatile semiconductor memory device in 6H-SiC for harsh environment applications

An electrically erasable programmable read-only memory (EEPROM) cell fabricated on a 6H-SiC substrate is reported. It is the first fully functional SiC EEPROM device. This device uses a generic double-polysilicon-gate configuration. It has been tested at both room temperature and elevated temperatures, up to 200/spl deg/C, to demonstrate full programmability. The threshold voltage shifts between programmed and erased states, at all tested temperatures, are larger than 4.5 V. In both states, the device functions satisfactorily as an n-type MOSFET. Charge retention time is more than 24 h at room temperature.