Accelerated thermal fatigue of lead-free solder joints as a function of reflow cooling rate

Leadless chip resistor (LCR) assemblies were manufactured using both traditional tin-lead (Sn37Pb) and lead-free (Sn3.8Ag0.7Cu) solders. The leadfree test vehicles were assembled using three different cooling rates: 1.6°C/sec, 3.8°C/sec, and 6.8°C/sec. They were then exposed to accelerated thermalcycling (ATC) tests between 0°C and 100°C with a 10–14°C/min ramp rate and a 5-min dwell time. The test results indicated that these lead-free solder joints had better creep-fatigue performance than the tin-lead solder joints. The LCR built with the medium cooling rate showed the longest fatigue life compared with the resistors built with the normal cooling rate of 1.6°C/sec and the higher cooling rate 6.8°C/sec. The number of cycles to failure was significantly correlated to the void defect rate. Failure analyses were done using cross-sectioning methods and scanning electron microscopy (SEM). Finite-element models were built to analyze the inelastic, equivalent strain range in solder joints subjected to thermal-cycling conditions with different degrees of solder wetting. The results indicated that poor wetting increases strains throughout the joint significantly, which is in accordance with the ATC results.     

Chip Scale Package (CSP) solder joint reliability and modeling

A viscoplastic constitutive model was used to analyze the thermally induced plastic and creep deformation and low cycle fatigue behavior of the solder joints in Chip Scale Packages (CSP) mounted on Printed Circuit Boards (PCB). The time-dependent and time-independent viscoplastic strain rate and plastic hardening work factors of solder material were used in 2-D plane strain finite element models. The viscoplastic strain rate data was fitted to the viscoplastic flow equation. The plastic hardening factors were considered in the evolution equation. A viscoelastic constitutive model was used for molding compound. Finite element models, incorporating the viscoplastic flow and evolution equations for solder and the viscoelastic equations for molding compound, were verified by temperature cycling tests on assembled CSPs. The effect of the cyclic frequency, dwell time, and temperature ramp rate on the response of the viscoplastic deformation was studied for a tapeless Lead-on-Chip (LOC) CSP and a flexible substrate CSP. The ramp rate significantly affects the equivalent stress range in solder joints while a dwell time in excess of 10 min per half cycle does not result in increased strain range. The failure data from the experiments was fitted to the Weibull failure distribution and the Weibull parameters were extracted. After satisfactory correlation between the experiment and the model was observed, the effect of material properties and package design variables on the fatigue life of solder joints in CSPs was investigated and the primary factors affecting solder fatique life were subsequently presented. Furthermore, a simplified model was proposed to predict the solder fatigue life in CSPs.     

Thermal Cycling Reliability of Sn-Ag-Cu Solder Interconnections. Part 1: Effects of Test Parameters

The work presented in part 1 of this study focuses on identifying the effects of thermal cycling test parameters on the lifetime of ball grid array (BGA) component boards. Detailed understanding about the effects of the thermal cycling parameters is essential because it provides means to develop more efficient and meaningful methods of reliability assessment for electronic products. The study was carried out with a single package type (BGA with 144 solder balls), printed wiring board (eight-layer build-up FR4 structure), and solder interconnection composition (Sn-3.1Ag-0.5Cu) to ensure that individual test results would be comparable with each other. The effects of (i) temperature difference (ΔT), (ii) lower dwell temperature and lower dwell time, (iii) mean temperature, (iv) dwell time, and (v) ramp rate were evaluated. Based on the characteristic lifetimes, the thermal cycling profiles were categorized into three lifetime groups: (i) highly accelerated conditions, (ii) moderately accelerated conditions, and (iii) mildly/nonaccelerated conditions. Thus, one might be tempted to use the highly accelerated conditions to produce lifetime statistics as quickly as possible. However, to do this one needs to know that the failure mechanisms do not change from one lifetime group to another and that the failure mechanisms correlate with real-use failures. Therefore, in part 2 the observed differences in component board lifetimes will be explained by studying the failure mechanisms that take place in the three lifetime groups.     

Temperature profile effects in accelerated thermal cycling of SnPb and Pb-free solder joints

Accelerated thermal cycling (ATC) has been widely used in the microelectronics industry for reliability assessment. ATC testing decreases life cycle test time by one or more of the following means: increasing the heating and cooling rate, decreasing the hold time, or increasing the range of the applied temperature. The relative effect of each of these cycle parameters and the failure mechanisms they induce has been the subject of many studies; however uncertainty remains, particularly regarding the role of the heating and cooling rate. In this research, three conditions with two ramp rates (14 °C/min and 95 °C/min) and two temperature ranges (ΔT = 0–100 °C and −40 to 125 °C) were applied to resistor 2512 and PBGA 256 test vehicles assembled with SnPb and Pb-free solders. The test results showed that the higher ramp rate reduced the testing time while retaining the same failure modes, and that the damage per cycle increased with the temperature difference. For the resistors, the Pb-free solder joints lasted longer than the SnPb joints at the smaller ΔT, but were inferior at the larger ΔT. In contrast, the Pb-free solder joints in the PBGA test vehicles lasted longer than the SnPb solder under both conditions.     

DETERMINATION OF GENERATION LIFETIME FROM C-t TRANSIENTS UNDER LINEAR VOLTAGE RAMP BIAS

When a linear voltage ramp is applied to the gate of a MOS capacitor,a capacitance-time(C-t)transient is observed.The MOS capacitor is biased into strong inversion before apply-ing the voltage ramp in order to eliminate surface generation.From C-t transient curve obtainedexperimentally the minority carrier generation lifetime in semiconductor can be determined.Theexperimental results show that for the same sample the lifetimes extracted from C-t curves un-der varying voltage sweep rates are close each other,and they are consistent with the lifetimesextracted by saturation capacitance method.     

快速跳频性能特征及其测试的研究

跳频转换时间、驻留时间、跳频速率是快速跳频的典型性能特征。文中介绍了这些性能特征的概念,从快速跳频系统的设计层面重点讲述了跳频转换时间、驻留时间、跳频速率之间的关系以及他们和硬件电路之间的联系,分析了影响快速跳频性能的主要因素,提出了提高快速跳频性能的途径。并对跳频转换时间等快速跳频性能特征的测试方法进行了研究,给出了使用下变频以及实时频谱分析仪的测试实例。     

Thermal cycling analysis of flip-chip solder joint reliability

The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (ΔT) effects on the predicted fatigue lives of solder joints are reported     

用线性电压扫描的电容-时间瞬态测定少子产生寿命

本文建议用耗尽的线性扫描电压扫描MOS电容样品。扫描开始前MOS电容被置于强反型态,以消除表面产生的影响。根据扫描所得的电容-时间瞬态曲线,可确定样品中少于产生寿命。实验表明,对于同一个MOS电容样品,不同电压扫描率下得到的结果有很好的一致性,且与饱和电容法的结果相符合。     

Error-Signal Response of a Phase-Locked Loop to a Coherent Chirp Signal

A new theory which describes the transient response of a PLL to a periodic ramp voltage applied to the VCO for generating a coherent chirp signal has been presented. With the appropriate choice of loop parameters and the ramp voltage rate to make the value of the normalized loop natural frequency within the range (0, 1), the PLL's equation can be simplified to a nearly linear differential equation. Its asymptotic solution can be obtained by the perturbation method as ε is a rather small value. Computer simulation results in agreement with the analysis have been obtained. Its application to generate a coherent linear frequency modulation waveform using a high-gain second-order PLL is considered.     

Thermomechanical reliability characterization of a handheld product in accelerated tests and use environment

Thermomechanical reliability of electronics has commonly been studied by employing accelerated temperature cycling (ATC) tests. However, due to the localized heat dissipation in modern electronic devices, operational power cycling (OPC) is considered a more realistic testing alternative. In order to characterize the thermomechanical reliability of modern high-density electronics, the failure modes, mechanisms and lifetimes of a contemporary commercial handheld device were studied under the ATC and OPC conditions.The experimental measurements and finite element analysis (FEA) showed distinct differences in the thermomechanical response of the device component boards under the OPC and ATC conditions. The results from FEA showed that the interconnection deformations during the OPC test were mostly in the elastic region of the solder, whereas those during the ATC tests reached well into the plastic region. The inclusion of the product enclosure further emphasized this difference, as the enclosure restricted the thermal expansion of the component board during OPC testing. The experimental test results were consistent with the FEA results, as the device failed due to solder interconnection cracking under the ATC conditions within 18 days of testing, but those under the OPC conditions remained operational even after 460 days.Finally, FEA estimations suggest that even three times higher power dissipation levels compared to those found in contemporary handheld devices would result in many years of lifetime in OPC testing.     

Determination of generation lifetime fromC-t transients under linear voltage ramp bias

When a linear voltage ramp is applied to the gate of a MOS capacitor, a capacitancetime (C-t) transient is observed. The MOS capacitor is biased into strong inversion before applying the voltage ramp in order to eliminate surface generation. FromC-t transient curve obtained experimentally the minority carrier generation lifetime in semiconductor can be determined. The experimental results show that for the same sample the lifetimes extracted fromC-t curves under varying voltage sweep rates are close each other, and they are consistent with the lifetimes extracted by saturation capacitance method.     

An improved NMOS AC hot-carrier lifetime prediction algorithm basedon the dominant degradation asymptote

This study presents a new algorithm for improved prediction of AC hot-carrier lifetime. It is based on identifying and projecting the dominant degradation asymptote. The algorithm accounts for the stress-bias dependence of the hot-carrier degradation rate and the nonlinearity of the degradation time-dependence. Detailed model parameter extraction and lifetime prediction procedures are explained, and applications of the new algorithm demonstrated. Significant differences in the predicted AC lifetimes are found between the existing and the new algorithms over a wide range of CMOS inverter design parameters, such as the input ramp rate and the load capacitance     

Analyses of thermal stresses and control schemes for fasttemperature ramps of batch furnaces [IC manufacture]

This work studies fast temperature ramps of batch furnaces under different control schemes based on thermal and stress analyses. A thermal model is first developed to predict temperature distributions on silicon wafers during ramping processes. Thermoelastic model of stresses is then used to predict the onset of slip-line generation under dynamic conditions. Three control schemes, one based on a maximum allowable within-wafer temperature difference, one with a constant cooling rate, and the third based on the condition for onset of slip generation, are then analyzed. The results show that in order to achieve the highest ramp rates while maintaining defect-free wafer processing, the ultimate criterion for temperature control of the furnaces should be the condition for the onset of defect generation instead of the conventional scheme based on constant ramp rates     

Recent developments in rapid thermal processing

Rapid thermal annealing (RTA) with a short dwell time at maximum temperature is used with ion implantation to form shallow junctions and polycrystalline-Si gate electrodes in complementary, metal-oxide semiconductor (CMOS) Si processing. Wafers are heated by electric lamps or steady heat sources with rapid wafer transfer. Advanced methods use “spike anneals,” wherein high-temperature ramp rates are used for both heating and cooling while also minimizing the dwell time at peak temperature to nominally zero. The fast thermal cycles are required to reduce the undesirable effects of transient-enhanced diffusion (TED) and thermal deactivation of the dopants. Because junction profiles are sensitive to annealing temperature, the challenge in spike annealing is to maintain temperature uniformity across the wafer and repeatability from wafer to wafer. Multiple lamp systems use arrayed temperature sensors for individual control zones. Other methods rely on process chambers that are designed for uniform wafer heating. Generally, sophisticated techniques for accurate temperature measurement and control by emissivity-compensated infrared pyrometry are required because processed Si wafers exhibit appreciable variation in emissivity.     

A general Weibull model for reliability analysis under different failure Criteria-application on anisotropic conductive adhesive joining technology

In this paper, a generic four-parameter model has been developed and applied to the anisotropic conductive adhesive (ACA) flip-chip joining technology for electronics packaging applications. The model can also be used to predict any minimum failure cycles if the maximum acceptable failure criterion (in this case, a preset electrical resistance value) is set. The original reliability testing from which the test data was obtained was carried out on flip-chip anisotropically conductive adhesive joints on an FR-4 substrate. In the study, nine types of ACA and one nonconductive film (NCF) were used. In total, nearly 1000 single joints were subjected to reliability tests in terms of temperature cycling between -40/spl deg/C and 125/spl deg/C with a dwell time of 15 min and a ramp rate of 110/spl deg/C/min. The reliability was characterized by single contact resistance measured using the four-probe method during temperature cycling testing up to 3000 cycles. A single Weibull model is used for two failure definitions defined as larger than 50 m/spl Omega/ and larger than 100 m/spl Omega/ respectively using the in situ electrical resistance measurement technique. The failure criteria are incorporated into this Weibull model. This paper shows the flexibility and usefulness of Weibull distribution in this type of applications.     

Switching Rate and Dwell Time in M-of-N Selection Diversity

Many investigations of hybrid selection (HS) diversity assume maximal ratio combining (MRC) of the selected branches. However, a coherent detector needs to dwell on the received signal for some time before it can produce accurate channel estimates for fading compensation, a requirement that appears inconsistent with the branch switching that occurs in a selection diversity receiver. Motivated by this observation, we derive in this letter analytical results on the switching rate and average dwell time of a selection diversity receiver where M out of a total of N independent branches are selected for combining. We show that the switching rate can be many times the Doppler frequency, while the average dwell time can be a small fraction of the reciprocal Doppler frequency. The brevity of the dwell times suggests difficulty in obtaining channel state information, which in turn calls into question performance analyses of idealized HS/MRC structures. Our results also suggest that HS/MRC should be frame-based, rather than continuously acting in time     

A dual-threshold up-down counter for GPS acquisition

In this work, the up-down counter detector for the acquisition of GPS signals is modified to use dual-thresholds for each trial. Closed form expressions for the mean and variance of the dwell time and the probabilities of detection and false alarm are derived. The new detector has a significantly smaller mean dwell time than the conventional single-threshold up-down counter and a lower dwell time variance when signals are weak. Further, the new detector has a low computational load, when compared to the optimal sequential probability ratio test (SPRT), whose main disadvantage is its computational complexity.     

中速搜索引导长驻留采集的搜索调度方法

针对雷达信号侦察系统搜索时间长、截获概率低的问题,文中提出了一种基于空域宽开雷达信号侦察系统的搜索调度方法来优化设计驻留时间。根据驻留时间的长短,将驻留时间分为仅能截获单个雷达脉冲的中等驻留时间和可截获多个雷达脉冲的长驻留时间。搜索开始阶段使用较短的中等驻留时间用于频域的快速扫描,在截获信号后将驻留时间调整为长驻留时间,以便采集雷达信号用于频率及周期结构分析。仿真结果表明,提出的算法可合理利用系统资源,提高系统的截获性能,为现有雷达对抗侦察系统设计提供了有益参考。     

最高可用频率自适应预报算法研究

基于实际观测数据的最高可用频率短期预报对于短波通信网络选择工作频率具有重要的意义,利用Kalman滤波技术设计了最高可用频率自适应预报算法,并用实际观测数据对其进行检验,结果表明:该算法能够自动跟踪实际测量数据的变化,较准确地预报未来时刻的最高可用频率。     

电子组件温度循环试验研究

为了使温度循环试验在有效提高电子组件的可靠性方面得以广泛应用,基于温度循环试验的机理,对电子组件温度循环试验的关键参数(温度范围、循环次数、保持时间、温变速率、风速)进行了探讨,给出了这些参数的工程经验选取值。在此基础上,借助热分析软件分析了温变速率、保持时间和风速三个参数对试验过程的影响并定性分析了三个参数间的关系。最后,提出了进行温度循环试验时应注意的问题,强调科学、正确地执行温度循环试验的重要性。