Simplification of sub-gap density of states extraction method for amorphous In-Ga-Zn-O thin-film transistors by a single capacitance-voltage curve

Sub-gap density of states (DOS) is one of the key parameters which impact both the electrical characteristics and reliability of amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors. So the investigation of DOS extraction is important. Here, a simplified and efficient DOS extraction method based on a single capacitance-voltage (C-V) curve is proposed. The method is verified by comparing with the results from the existing DOS extraction methods such as static current-voltage (I-V) measurement. Besides, this method is applied to extract DOS of an a-IGZO thin-film transistor with different electrical properties. This updated method is employed to explain the decrease of device turn-on voltage, which could be attributed to the DOS decrease. In summary, it is a simple method based on a single C-V curve without optical illumination, temperature dependence, accurate I-V model supporting or complicated mathematics fitting.     

基于陷落电荷效应的非晶硅TFT的开态电流模型

对非晶硅薄膜晶体管,提出基于陷落电荷和自由电荷分析的新方法。考虑到带隙中指数分布的深能态和带尾态,给出了基于阈值电压的开启区电流模型。定义阈值电压为栅氧/半导体界面处陷落于深能级陷阱态的电荷与陷落于带尾态的电荷相等时所对应的栅压。电流模型中,引入一陷落电荷参数β,此参数建立了电子的带迁移率与有效迁移率之间的关系。最后,将电流模型同时与Pao-Sah模型和实验数据进行比较和验证,结果表现出很好的一致性。     

Illuminating Trap Density Trends in Amorphous Oxide Semiconductors with Ultrabroadband Photoconduction

Under varying growth and device processing conditions, ultrabroadband photoconduction (UBPC) reveals strongly evolving trends in the defect density of states (DoS) for amorphous oxide semiconductor thin-film transistors (TFTs). Spanning the wide bandgap of amorphous InGaZnO_x (a-IGZO), UBPC identifies seven oxygen deep donor vacancy peaks that are independently confirmed by energetically matching to photoluminescence emission peaks. The subgap DoS from 15 different types of a-IGZO TFTs all yield similar DoS, except only back-channel etch TFTs can have a deep acceptor peak seen at 2.2 eV below the conduction band mobility edge. This deep acceptor is likely a zinc vacancy, evidenced by trap density which becomes 5-6× larger when TFT wet-etch methods are employed. Certain DoS peaks are strongly enhanced for TFTs with active channel processing damage caused from plasma exposure. While Ar implantation and He plasma processing damage are similar, Ar plasma yields more disorder showing a ≈2 × larger valence-band Urbach energy, and two orders of magnitude increase in the deep oxygen vacancy trap density. Changing the growth conditions of a-IGZO also impacts the DoS, with zinc-rich TFTs showing much poorer electrical performance compared to 1:1:1 molar ratio a-IGZO TFTs owing to the former having a ∼10 × larger oxygen vacancy trap density. Finally, hydrogen is found to behave as a donor in amorphous indium tin gallium zinc oxide TFTs.     

A step-accurate model for the trapping and release of charge carriers suitable for the transient simulation of analog circuits

A compact add-on model is proposed to simulate the mechanism of charge trapping and release (detrapping) and its effect on the threshold voltage of MOSFET devices. The model uses implicit algebraic differential equations compatible with transient analysis in SPICE. It also shares the accuracy level of the transient analysis. A micro-model approach is used, and each trap is treated by a two-state Markov process. The normalization of trap behavior can be enabled or disabled, so that the designer can compare average trap behavior to the result of repeated Monte-Carlo simulations of a circuit. In this manner, the model can compromise between device-level modeling and circuit-level modeling. Unlike models geared towards digital circuit design, the trapping and release rates need not be constant during electrical stress. The trapping and release rates are a function of time, as they depend on the circuit state-space equations. An operational amplifier is analyzed using the new model, and the proposed approach is compared with the state of the art.     

Detrapping Current Measurement System Driven by Triboelectric Nanogenerators for Mapping Electron Trap States in Dielectrics

Electron trap states characterization plays a vital role in mesoscale measurement. Previous destructive methods have been applicable only in qualitative comparison. Nonetheless, the imaging of trap states distribution in space and energy level remains challenging. Herein, a triboelectric nanogenerator driven detrapping current (TENGd-DTC) measurement system is reported. The triboelectric nanogenerator (TENG) is designed as a high voltage generator, with an output voltage of ≈3 kV for driving the dielectric barrier discharge (DBD). The discharge model with dynamic carriers’ evolution is proposed, thus the detrapping currents can be extracted from DBD currents, based on which energy levels and densities of trap states are quantitatively calculated. The chamber design parameters as the platform for TENGd-DTC measurement under DBD are optimized. With the optimized chamber, the energy level range within 0.6–0.8 eV can be clearly characterized, and the difference between results of the proposed and the current methods is less than 12%. More importantly, the improved measurement electrode array is applied for multi-point scanning, and imaging of trap parameters is demonstrated vividly at a spatial resolution of ≈50 μm. This work paves an effective and non-destructive imaging approach for trap states characterization, and potential applications in mesoscale modification of functional materials.     

Assessing the width of Gaussian density of states in organic semiconductors

The Density of States (DOS) is an ingredient of critical importance for the accurate physical understanding of the optoelectronic properties of organic semiconductors. The disordered nature of this class of materials, though, renders the task of determining the DOS far from trivial. Its extraction from experimental measurements is often performed by driving the semiconductor out of thermal equilibrium and therefore requires making assumptions on the charge transport properties of the material under examination. This entanglement of DOS and charge transport models is unfavorable since transport mechanisms in organic semiconductors are themselves still subject of debate. To avoid this, we propose an alternative approach which is based on populating and probing the DOS by means of capacitive coupling in Metal Insulator Semiconductors (MIS) structures while keeping the semiconductor in thermal equilibrium. Assuming a Gaussian shape, we extract the DOS width by numerical fitting of experimental Capacitance–Voltage curves, exploiting the fact that the DOS width affects the spatial distribution of accumulated charge carriers which in turn concurs to define the MIS capacitance. The proposed approach is successfully tested on two benchmark semiconducting polymers, one of n-type and one of p-type and it is validated by verifying the robustness of the extraction procedure with respect to varying the insulator electrical permittivity. Finally, as an example of the usefulness and effectiveness of our approach, we study the static characteristics of thin film transistors based on the aforementioned polymers in the framework of the Extended Gaussian Disorder transport model. Thanks to the extracted DOS widths, the functional dependence of current on the gate voltage is nicely predicted and physical insight on transistor operation is achieved.     

Characterization, modeling, and minimization of transient thresholdvoltage shifts in MOSFETs

MOSFETs subjected to large-signal gate-source voltage pulses on microsecond to millisecond time scales exhibit transient threshold voltage shifts which relax over considerably longer periods of time. This problem is important in high-accuracy analog circuits where it can cause errors at the 12 b level and above. In this paper, transient threshold voltage shifts are characterized with respect to their dependence on stress amplitude and duration, relaxation time, gate bias, substrate bias, drain voltage, temperature, and channel width and length. In contrast to previous studies, threshold voltage shifts are measured at time and voltage scales relevant to analog circuits, and are shown to occur even when the effects of Fowler-Nordheim tunneling, avalanche injection, hot carriers, trap generation, self-heating, mobile ions, and dipolar polarizations are absent. A new model is proposed in which channel charge carriers tunnel to and from near-interface oxide traps by one of three parallel pathways. Transitions may occur elastically, by direct tunneling between the silicon band edges and an oxide trap, or inelastically, by tunneling in conjunction with a thermal transition in the insulator or at the Si-SiO₂ interface. Simulations based on this model show excellent agreement with experimental results. The threshold voltage shifts are also shown to be correlated with 1/f noise, in corroboration of the tunneling model. Techniques for the minimization and modeling of errors in circuits are presented     

Modeling of SILC based on electron and hole tunneling. I. Transienteffects

A detailed investigation of the steady-state and transient leakage currents in thin oxides is proposed. The experimental data are compared with numerical results obtained from a model based on an inelastic trap-assisted tunneling process, which includes both electron and hole contributions. In order to accurately reproduce the transient discharge currents, a continuous distribution of oxide traps was adopted. The energies of these levels can be either in correspondence of the conduction or valence band edges of the adjacent silicon/polysilicon layers. Both electrons and holes contribute to the transient stress-induced leakage current (SILC), but the extracted trap densities cannot account for the steady-state SILC. A different mechanism, involving trap levels with energy aligned to the energy gap of the silicon layers is proposed and is developed in the following paper. The model can be applied to any type of device and bias conditions and may be used to correctly recognize the role of electron and hole SILC and the spatial and energy distribution of defect states     

Correlation of stress-induced leakage current in thin oxides withtrap generation inside the oxides

Increases in pre-tunneling leakage currents in thin oxides after the oxides are subjected to high voltage stresses are correlated with the number of traps generated inside of the oxides by the high-voltage stresses. The densities of the traps are calculated using the tunneling front model and analyzing the transient currents that flowed through the oxide after removal of the stress voltage pulses. It is found that the trap distributions are relatively uniform throughout the small portion of the oxide sampled by the transient currents. The trap densities increase as the cube root of the fluence of electrons that passes through the oxide during the stress, independent of the stress polarity. The voltage dependence of the low-level pretunneling current is dependent on the sequence in which the stress voltage polarities and the low-level current measurement polarities are applied. The portion of the low-level pre-tunneling current that is not dependent on the polarity sequence is best fitted by a voltage dependence consistent with Schottky emission     

Characterizing wearout, breakdown and trap generation in thin silicon oxide

A model describing how wearout leads to breakdown in thin silicon oxides has been developed. During wearout defects or traps are generated inside the oxide and at the oxide interfaces. The signature of the trap generation is the permanent change in the transient current, in response to a voltage pulse, from an exponential decay to a 1/time decay. In oxides thinner than approximately 20 nm the dominant trap generation mechanism appears to be determined by the high fields across the oxides and not electron flow through the oxides. Locally higher current densities, flowing through the traps generated during wearout, lead to local breakdown. This model is critically dependent on the measurement of the properties of the traps generated inside the oxides during the wearout phase. The techniques for measurement of these traps and some of their properties have been described. The ability of this model to describe oxide charging, low-level leakages, transient currents, the role of asperities, polarity dependences, and the fluence, time, thickness, voltage and temperature dependences of oxide breakdown distributions has been discussed.     

Interface Electron Traps as a Source of Anomalous Capacitance in AlGaN/GaN Heterostructures

We studied by modeling and simulation how deep traps at the AlGaN/GaN heterostructure interface influence the shape of capacitance–voltage (C–V) curves of the heterostructure. Assuming donor and acceptor type of traps, we found differences in the C–V curves for sharp energy interface states or continuously distributed states with the same total concentration for the acceptor-type interface states. The background doping concentration of GaN had only a marginal influence on the shape of the C–V curves. We observed that an anomalous capacitance peak occurred for the continuous distribution of traps in the bandgap; a similar peak had been observed in experiment. We also saw that the capacitance curves shifted slightly to the right or to the left depending on the GaN doping concentration. A remarkable difference was found between the capacitance curves for the structures with the sharp acceptor trap level and continuous distribution of traps. For donor-type interface states, we found practically no influence on C–V curves since they remain populated and charge neutral during the measurement.     

优化Hammerstein模型的电磁脉冲效应建模仿真

针对采用Hammerstein模型描述电磁脉冲效应时模型参数确定困难的问题,提出一种基于优化Hammerstein模型的非线性电磁脉冲效应建模仿真方法。该方法利用高阶累积量求解模型线性延迟阶数,采用赤池信息准则（Akaike Information Criterion,AIC）优化模型非线性阶次,两者共同确定出一个参数最少、精度较高的最优模型,并以瞬态抑制器的电磁脉冲效应建模为例验证了该方法。     

Trap-limited bimolecular recombination in poly(3-hexylthiophene): Fullerene blend films

Trap-limited bimolecular recombination in poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl-C61-butyric acid methyl ester (PC₆₁BM) blend films has been investigated by using photo-induced charge extraction by linearly increasing voltage (photo-CELIV) method. The bimolecular recombination rate is strongly dependent on the photoexcitation density, the PC₆₁BM composition and the thermal annealing process, but it slightly depends on the thickness of the blend film. The results show that the trap-limited bimolecular recombination is strongly affected by the distribution of the density of trap state (trap DOS). The higher trap-limited bimolecular recombination rate means the trap DOS centered at lower energy which is beneficial to charge carriers transportation, due to the lower activation energy and faster release rate. On the other hand, the trap-limited bimolecular recombination rate is mainly controlled by the slower species of charge carriers in the blend film when the transport of electrons and holes are strongly unbalanced, and the recombination rate will increase when the transport of electrons and holes becomes more balanced.     

An analytical model for charge pumping below strong inversion and accumulation

A compact analytical model for charge pumping (CP) is derived. It accounts for emission during the high and low gate bias levels and assumes instantaneous transition edges. This model, which does not apply on the top of the CP curves when using large gate voltage swings, where emission fully proceeds during the transitions edges of the gate signal, applies on all the other regions provided that the transition times of the gate signal are much shorter than the times at steady state biases. Therefore it holds at large bias swings on both edges of Elliot curves and at small bias swings on the whole Elliot curves provided that the interface traps are completely filled [1]. It is compared with the analytical model proposed by Wachnik and Lowney [2] in which emission is not accounted for at all. This model, which holds at Elliot curve maxima when small voltage swings are used, has been shown to be extremely useful for studying interface trap properties [1, 2, 3 and 4]. The CP model proposed primarily, that of Brugler and Jespers [5], is used as a reference. The model derived in this article very satisfactorily fits the experimental curves in the regions of large CP current where it holds. Discrepancies at low current levels are due to the well-known contribution of the transistor source and drain regions or could be due to edge effects. Comparing the different models and the experimental curves allows to evaluate emission and capture during different regions of the gate bias period. The three regions of CP response, depending on the gate voltage swing and involving or not emission and the full filling of the interface traps, are also evidenced.     

A new method to characterize border traps in submicron transistors using hysteresis in the drain current

In this paper, a new method for measuring border trap density (n/sub BT/) in submicron transistors using hysteresis in the drain current is proposed. This method is used to measure energy and spatial distribution of border traps in jet vapor deposited (JVD) metal-silicon nitride-semiconductor field effect transistors (MNSFETs). The drain current transient varies linearly with logarithmic time suggesting that tunneling to and from the spatially uniform border traps is the dominant charge exchange mechanism. Using a feedback mechanism gate voltage transients are obtained from which n/sub BT/ is calculated. The prestress energy distribution in JVD MNSFETs is found to be uniform whereas the post-stress energy distribution shows a peak near the midgap.     

Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling,experimental evidence,and impact on circuits

With the downscaling of CMOS devices, dynamic variability induced by negative bias temperature instability (NBTI) has become a critical issue. In addition to the time-dependent device-to-device variation (DDV) of NBTI degradation, the cycle-to-cycle variation (CCV) originated from random trap occupation is found non-negligible and should be added into the total dynamic variation. This paper summarizes our recent studies on NBTI-induced dynamic variability, focusing on the CCV effect, with more details on the statistical modeling, circuit reliability simulation methodologies and experimental results. By adding the random trap occupation into consideration, a statistical model for total dynamic variation (DDV + CCV) is proposed. The effective occupancy probability p_eff is introduced as a key parameter for modeling and circuit reliability simulation. With the statistical trap response (STR) method and modified on-the-fly method, the proposed model is validated by the experimental evidence under both DC and AC NBTI. According to the model and experimental results, circuit reliability simulation framework is proposed for both long-term quasi-static and short-term transient performance evaluation with the additional impact of CCV. Two representative digital circuit units, ring oscillator (RO) and SRAM cell, are simulated under different conditions, indicating it necessary to consider the evident influence of the CCV in accurate circuit reliability evaluation. The results are helpful for the reliability/variability-aware circuit design in nanoscale technology.     

高K栅堆叠结构MOSFET器件阈值电压不稳定度的半经验解析模型

A semi-empirical analytic model for the threshold voltage instability of MOSFET is derived from the Shockley-Read-Hall (SRH) statistics in this paper to account for the transient charging effects in a MOSFET high-k gate stack. Starting from the single energy level and single trap assumption, an analytical expression of the filled trap density in terms of the dynamic time is derived from the SRH statistics. The semi-empirical analytic model of the threshold voltage instability is developed based on the MOSFET device physics between the threshold voltage and the induced trap density. The obtained model is also verified by the extensive experimental data of the trapping and de-trapping stress from the different high k gate configuration.     

A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs-from single electron emission to PBTI recovery transient

A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large- and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temperature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In addition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method.     

Numerical simulation of tunnel diodes for multi‐junction solar cells

This work presents efforts to simulate numerically the current voltage (IV) curve of a III–V based Esaki tunnel diode. Using a tunneling model, which takes into account the full nonlocality of the barrier, a good agreement between measured and simulated IV curves of a GaAs tunnel diode was achieved. The influence of a series resistance effect as well as the importance of trap assisted tunneling (TAT) could be shown. In addition, we present a two‐dimensional model of a III–V multi‐junction solar cell including the numerical model of the investigated Esaki tunnel diode. Copyright © 2008 John Wiley & Sons, Ltd.     

基于表面势的多晶硅晶体管漏电流物理模型

提出了一种基于薄层电荷模型、陷阱态密度和表面势的多晶硅薄膜晶体管漏电流物理模型。模型采用非迭代的运算方法, 简单且适用于所有大于平带电压的工作区域。 考虑了包括高斯分布的深能态和指数分布的带尾态在内的陷阱分布形式, 陷阱分布参数的提取通过光电子调制谱方法实现。通过模型与现有实验结果的比较, 得到一致的符合结果。