The radiation test based assessment of process quality and reliability for conventional 65-nm CMOS technology

This work presents a solution for radiation hardness assessment using compact and productive X-ray facilities, as well as the automated measurement system. The radiation test procedure can be integrated in commercial IC's process as a mandatory option for providing high reliability and radiation hardened IC projects.Using the radiation test procedure as a one of technology stage, the assessment of total ionizing dose (TID) hardness was done for test structures, which were fabricated in conventional 65 nm CMOS technology.     

Radiation induced transconductance overshoot in the 130 nm partially-depleted SOI MOSFETs

This paper presents the total ionizing dose (TID) radiation performances of core and input/output (I/O) MOSFETs from 130 nm partially-depleted silicon-on-insulator (PDSOI). Both the core NMOS and PMOS are totally hardened to 1.5 Mrad(Si), while the I/O devices are still sensitive to TID effect. The worst performance degradation is observed in I/O PMOS which is manifested as significant front gate threshold voltage shift and transconductance decrease. Contrary to PMOS, front gate transconductance overshoot is observed in short channel I/O NMOS after irradiation. A radiation induced localized damage model is proposed to explain this anomalous phenomenon. According to this model, the increments of transconductance depend on the extension distance and trapped charge density of the localized damage region in gate oxide. More trapped charge lead to more transconductance increase. These conclusions are also verified by the TCAD simulations. Furthermore, the model presents a way to extract the trapped charge density in the localized damage region.     

The effect of oxide layer thickness on the quantification of 1.5 MeV γ–radiation induced interface traps in the Ag/SiO2/Si MOS devices

This work presents the effect of varied thickness of oxide layer and radiation dose on electrical characteristics of Ag/SiO₂/Si MOS devices irradiated by 1.5 MeV γ–radiations of varied doses. SiO₂ layers of 50, 100, 150 and 200 nm thickness were grown on Si substrates using dry oxidation and exposed to radiation doses of 1, 10 and 100 kGy. The exposure to radiation resulted in generation of fixed charge centers and interface traps in the SiO₂ and at the Si/SiO₂ interface. Capacitance-conductance-voltage (C-G-V) and capacitance-conductance-frequency (C-G-f) measurements were performed at room temperature for all MOS devices to quantify the active traps and their lifetimes. It is shown that accumulation and minimum capacitances decreased as the thickness of SiO₂ layer increased. For the unexposed MOS devices, the flat band voltage V_FB decreased at a rate of −0.12 V/nm, density of active traps increased by 4.5 times and depletion capacitance C_DP, increased by 2.5 times with the increase of oxide layer thickness from 50 to 200 nm. The density of active traps showed strong dependence on the frequency of the applied signal and the thickness of the oxide layer. The MOS device with 200 nm thick oxide layer irradiated with 100 kGy showed density of active interface traps was high at 50 kHz and was 3.6×10¹⁰ eV⁻¹ cm⁻². The relaxation time of the interface traps also increased with the exposure of γ–radiation and reached to 9.8 µs at 32 kHz in 200 nm thick oxide MOS device exposed with a dose of 100 kGy. It was inferred that this was due to formation of continuum energy states within the band gap and activation of these defects depended on the thickness of oxide layer, applied reverse bias and the working frequency. The present study highlighted the role of thickness of oxide layer in radiation hard environments and that only at high frequency, radiation induced traps remain passivated due to long relaxation times.     

Numerical design of a 100 W, 38 dB gain,W-band multi-section serpentine waveguide vacuum electronic TWT

The serpentine waveguide circuit is a robust beam-wave interaction circuit for W-band TWTs. Here presented the electromagnetic properties and design methodology for W-band multi-section SWG traveling wave tube. Cold-test (in absence of electron beam) numerical design performed theoretically and further optimized/validated with standard simulation code to predict the dispersion, interaction impedance, ohmic-loss and small-signal gain. Numerical simulation for the quarter wave transformer couplers with SWG circuit geometry shown the return-loss less than −20 dB for the 5% frequency band. Later, in systematic manner, hot-test (in presence of electron beam) numerical design performed for multi-section TWT by using standard particle-in-cell 3-D simulation code. The three section, 60 periods SWG TWT predicted peak radiation power 130 W at target frequency 94 GHz, 39.5 dB saturated gain, 5.3% instantaneous 3-dB frequency bandwidth, and 6.5% electronic efficiency.     

A 1.58 nW power consumption and 34.45 ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag

In this paper a bandgap reference (BGR) circuit irrespective of the temperature and the supply voltage variation with very low power consumption is proposed. The proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) generators of the proposed BGR, which has four cores cascaded with each other, are used in order to increase not only the output voltage, but also the output control ability for the temperature and the voltage insensitivity. To combine produced voltage from PTAT and CTAT generator, a weight combination circuit, which uses internal capacitors of transistors, is applied. Due to the fact that all of the transistors in such a topology are worked in sub-threshold region, the power consumption is significantly diminished to 1.58 nW. Also the variation of the temperature from −25 °C to 150 °C, leads to the temperature coefficient about 34.45 ppm/°C. The design simulation is done at 960 MHz frequency in TSMC 0.18 µm CMOS technology with the help of Cadence software. Also the post layout simulation result and the layout of the proposed circuit are presented. The output and the chip area of this BGR are 141.5 mV and 1387 µm² respectively.     

Design and characterization of high-voltage NMOS and PMOS devices in standard 0.25 μm CMOS technology

This paper presents the design of high-voltage NMOS and PMOS devices with shallow trench isolation (STI) in standard 0.25 μm/5 V CMOS technology. Breakdown voltages of 20 V for n-channel device with a specific on resistance of 1.06 mΩ cm² and −20 V for p-channel device with a specific on resistance of 2.83 mΩ cm² have been achieved without any modification of existing standard CMOS process.     

A mixed-signal pulse width modulator for portable SMPS applications

This paper presents a design for a mixed-signal pulse width modulator (MSPWM) integrated circuit that targets the digital control of high-frequency switched-mode DC–DC power supplies (SMPS). Previous designs consider digital pulse width modulators (DPWM) implementations that encounter important design issues, such as power consumption, non-linearity, layout dependency, trimming capability and temperature dependency. This work presents effective solutions, suitable for large-scale production of ICs, since it combines high-precision, high-linearity and temperature-independent standard analog circuits, which are commonly offered by the semiconductor industry, with the simplicity and reuse of digital PID compensation as input. The 8-bit prototype designed for a 0.18-μm CMOS process operates at switching frequency of 2 MHz, draws only 96.25 μA from a 1.8 V supply and takes 0.029 mm², including the non-overlapping control logic of SMPS power devices.     

Feed-forward Output Swing Prediction AGC design with Parallel-Detect Singular-Store Peak Detector

This paper presents an Automatic Gain Control (AGC) circuit design with 200–530 μW average power consumption given a 1 V supply. The Variable Gain Amplifier (VGA) therein comes with 0.9 V input range and output stages with a swing of 0.9 V and a minimum bandwidth of 100 MHz. Feed-forward Output Swing Prediction is used to adjust the gain of the VGA corresponding to the signal envelope detected by a Parallel-Detect Singular-Store Peak Detector. At a maximum refresh-rate of 4 MHz, the AGC is capable of adjusting the gain of the VGA within less than 250 ns when the input signal envelope is reduced by 20 dB, and 100 ns when raised by 20 dB. The circuit design is carried out using a 0.18 μm standard CMOS process with a core area of 0.0024 mm².     

Leakage reduction through optimization of regular layout parameters

Regular layouts that follow restrictive design rules are essential to robust CMOS design in order to alleviate many manufacturing induced effects, such as the effect of non-rectangular gate (NRG) due to sub-wavelength lithograph. NRG dramatically increases the leakage current by more than 15X compared to that of ideal physical layout. To mitigate such a penalty, we developed a technique to optimize regular layout through restrictive design rule parameters and to benchmark post-lithography circuit performance. We propose a procedure to systematically optimize key layout parameters in regular layout to minimize the leakage energy with minimal over head to active energy, circuit speed and area. The proposed layout optimization technique is demonstrated with a 65 nm technology and projected for 45 nm and 32 nm technology nodes. Experimental results show that more than 70% reduction in leakage can be achieved with area penalty of ～10% and 9–12% overhead on circuit speed and active energy.     

Effect of interface traps for ultra-thin high-k gate dielectric based MIS devices on the capacitance-voltage characteristics

The impact of states at the Al₂O₃/Si interface on the capacitance-voltage C-V characteristics of a metal/insulator/semiconductor heterostructure (MIS) capacitor was studied by a numerical simulation, by solving Schrodinger-Poisson equations and taking the electron emission rate from the interface state into account. Efficient computation and accurate physics based capacitance model of MOS devices with advanced ultra-thin equivalent oxide thickness (EOT) (down to 2.5 nm clearly considered here) were introduced for the near future integrated circuit IC technology nodes. Due to the importance of the interface state density for a low dimension and very low oxide thickness, a high frequency C-V model has been developed to interpret the effect of interface state density traps which communicate with the Al₂O₃/Si and their influence on the C-V characteristics. We found that these states are manifested by jumping capacity in the inversion zone, for a density of interface, higher than 1 × 10¹¹ cm^− 2 eV^− 1 during a p-doping of 1 × 10¹⁸ cm^− 3. This behavior has been investigated with various doping, temperature, frequency and energy levels on the C-V curves, and compared with the MIS structure that contains a standard SiO₂ insulator.     

Radiation induced loss properties and hardness enhancement technique for ErYb doped fibers for avionic applications

We present radiation reliability properties and their enhancement of ErYb doped optical fibers in terms of induced loss and lifetime prediction via master curve analysis method. In this study, we are primarily concerned with the effects of ionizing radiation on the performance of double cladded ErYb doped optical fibers in an accelerated low dose γ-radiation environment (i.e. <120 rad/h rate) for high power optical amplifiers to be used in satellite communication systems. We demonstrate a novel method that utilizes pre-radiation exposure and thermal annealing, for enhancing radiation hardness of the fibers with respect to induced optical loss and lifetime prediction. Based on this method, we are able to modify radiation induced loss-rate properties of the fiber with an initial loss penalty, realizing overall loss-budget improvement for relatively long-term deployment (i.e. >5 years). In a direct comparison to non-hardened ErYb doped fibers, we demonstrate approximately 0.16 dB/m of radiation induced loss improvement including an initial loss penalty of 0.14 dB for radiation-hardened fibers over a 10-year duration in a natural low dose (i.e. <0.3 rad/h) radiation environment, i.e. low earth orbit.     

A low power current controllable single-input three-output current-mode filter using MOS transistors only

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8 V and using 0.18 μm CMOS process parameters. The power consumption and the required chip area are only 0.5 mW and 77.4 μm × 70.2 μm, respectively.     

Non-destructive Raman evaluation of a heavily doped surface layer fabricated by laser doping with B-doped Si nanoparticles

The heavy B-doping of an intrinsic Si(1 0 0) wafer has been performed by irradiating a B-doped Si nanoparticle film on the surface of the Si(1 0 0) substrate with energy densities of 8.0 and 16.0 J/cm² by 532-nm laser light. The thicknesses of the heavily doped surface layers were investigated using Raman spectroscopy. The observed 488.0-nm-excited Raman bands were decomposed into two bands: a Fano-type band due to the heavily doped Si surface layer and a Voigt band due to the lightly doped, intrinsic Si region. The analysis of the Fano-type band indicated that the carrier concentration of the heavily doped region was larger than approximately 10¹⁹ cm⁻³. Based on the two-state model, the thicknesses of the heavily doped surface layers were 480 and 630 nm for the samples prepared with energy densities of 8.0 and 16.0 J/cm², respectively. These values were consistent with those obtained by secondary ion mass spectroscopy (SIMS).     

A new ambipolar blue emitter for NTSC standard blue organic light-emitting device

A novel blue emitter, In2Bt, featured with a rigid and coplanar distyryl-p-phenylene backbone flattened by two different bridging atoms (i.e. carbon and sulfur) exhibits high thermal and morphological stability (T_g ～ 192 °C) and ambipolar charge carrier mobilities in the range of 10^?4 ～ 10^?5 cm² V^?1 s^?1. OLED device: ITO/PEDOT:PSS (300 Å)/α-NPD (200 Å)/TCTA (100 Å)/In2Bt (200 Å)/TPBI (500 Å)/LiF (5 Å)/Al (1500 Å) utilized In2Bt as an emitter gave a maximum brightness as high as 8000 cd m^?2 (12 V) and saturated-blue emission with CIE chromaticity coordinates of (0.16, 0.08), which is very close to the National Television Standards Committee (NTSC) standard blue gives an enlarged palette of colors for color displays.     

A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers

In this paper, a low power Variable Gain Amplifier (VGA) circuit with an approximation to exponential gain characteristic is presented. It is achieved using current mirrors to generate appropriate current signals to bias the input stage of the VGA circuit working in triode region, and the output stage working in saturation region, respectively. The VGA circuit presented herein comes with a 549 μW maximum power consumption given a 1.8 V supply. Most important of all, it has a linear-in-dB 48-dB dynamic gain range per stage. The effect of the input trasconductance and the output resistance on the linearity of gain control is also discussed. This circuit is fabricated using a 0.18 μm standard CMOS process with a core area of 0.0045 mm².     

A novel 5.8 GHz quasi-lumped element resonator antenna

In this paper, a novel quasi-lumped element resonator antenna is presented. The proposed antenna consists of the interdigital capacitor in parallel with a straight line inductor and is fabricated on Duroid RC4003C circuit board. The entire arrangement was fed by a coaxial feed at a frequency of 5.8 GHz. The size, bandwidth and radiation patterns were studied. The proposed antenna exhibits better impedance bandwidth and significant size reduction in comparison with similar results obtained from the conventional microstrip patch antenna with similar feeding technique and resonant frequency. The size of the proposed antenna structure is 5.8 × 5.6 mm² and experimental results are shown to be in good agreement with the design simulation.     

Efficient biasing circuit strategies for inductorless wideband low noise amplifiers with feedback

This paper presents a comparative study among different biasing circuits of inductorless low-area Low Noise Amplifier (LNAs) with feedback. This study intends to determine the most suitable biasing circuit to achieve the best LNA performance for wideband applications. The main performance metrics are analyzed and a comparison is carried out based on electrical simulations. To this purpose, two different CMOS technology processes are considered: 130 nm and 90 nm. In both cases, the supply voltage is 1.2 V. The best LNA designed in 130 nm achieves a bandwidth of 2.94 GHz with a flat voltage gain (A_v) of 16.5 dB and a power consumption of 3.2 mW. The same LNA topology designed in 90 nm technology has a bandwidth of 11.2 GHz, featuring a voltage gain of 16.6 dB and consuming 1.9 mW. Both LNAs are input-impedance matched and have a noise figure below 2.4 dB measured at 2.4 GHz. As a case study, the layout of the best-performance LNA circuit has been implemented in a 130 nm technology, achieving an area of 0.012 mm², which is near the size of a pad or an inductor. It is demonstrated that the bandwidth of this circuit can be notably increased by simply adding a small inductance in the feedback path.¹     

RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications

In this paper a radio frequency (RF) to direct current (DC) voltage converter with multi-stage rectifiers is reported for micro power conversion in RF power harvesting systems. The purpose of this paper is to select an appropriate structure for the micro power-converters, operating in high frequencies. The main idea is to convert RF range sinusoidal signals to a DC voltage to produce power for the rest of the electrical circuit or a system. The reported rectifier demonstrated an efficiency of 10% at large span of frequency for input signal of 350 mV. In the presented work, an analytical and numerical study of the micro power-converters is reported for various applications. Different design parameters have been investigated for an efficient structure design including, number of MOSs, DC current of a known load, size of MOSFETs capacitors, and frequency of the operation. Consequently, optimized parameters have been reported in order to improve the RF to DC conversion efficiency. Reported circuits were designed and simulated in 180 nm twin-well CMOS process with low threshold metal-oxide semiconductor field-effect transistors (MOSFETS); this multistage rectifier occupied an area of 0.23 mm × 0.146 mm and it produced an output voltage of 2 V at its output. This output voltage can provide the supply voltage required to operate the RFID processing circuitry. Post layout simulations demonstrated that for thirteen stages of the rectifiers, the efficiency of 10% for a capacitive load of 10 pF has been achieved.     

Investigation of Si/SiGe/Si heterostructure implanted by H ion and annealed in vacuum and dry O2 ambient

The 20-nm-thick Si cap layer/74-nm-thick Si_0.72Ge_0.28 epilayer/Si heterostructures implanted by 25 keV H⁺ ion to a dose of 1×10¹⁶ cm⁻² were annealed in ultra-high vacuum ambient and dry O₂ ambient at the temperature of 800 °C for 30 min, respectively. Rutherford backscattering/ion channeling (RBS/C), Raman spectra, high-resolution X-ray diffraction (HRXRD) and atomic force microscopy (AFM) were used to characterize the structural characteristics of the Si_0.72Ge_0.28 layer. Investigations by RBS/C demonstrated that the crystal quality of the Si/Si_0.72Ge_0.28/Si heterostructure sample implanted by 25 keV H⁺ in conjunction with subsequent annealing in dry O₂ ambient is superior to that of identical sample annealing in ultra-high vacuum ambient. The less strain relaxation of SiGe layer of the Si/Si_0.72Ge_0.28/Si heterostructures implanted by H ion and annealed in dry O₂ ambient at the temperature of 800 °C for 30 min could be doublechecked by Raman spectra as well as HRXRD, which was compared with that in an identical sample annealed in ultra-high vacuum ambient for identical thermal budget. In addition, the SiGe layer of the H-implanted Si/SiGe/Si heterostructural sample annealed in dry O₂ ambient accompanied by better crystal quality and less strain relaxation made its surface morphology superior to that of the sample annealed in ultra-high vacuum ambient at the temperature of 800 °C for 30 min, which was also verified by AFM images.     

MISO current mode bi-quadratic filter employing high performance inverting second generation current conveyor circuit

This paper presents static and dynamic studies of a new CMOS realization for the inverting second generation current conveyor circuit (ICCII). The proposed design offers enhanced functionalities compared to ICCII circuits previously presented in the literature. It is characterized by a rail to rail dynamic range with high accuracy, a low parasitic resistor at terminal X (1.6 Ω) and low power consumption (0.31 mW) with wide current mode (3.32 GHz) and voltage mode (3.9 GHz) bandwidths.Furthermore, a new MISO current mode bi-quadratic filter based on using ICCII circuits as active elements is proposed. This filter can realize all standard filter responses without changing the circuit topology. It is characterized by active and passive sensitivities less than unity and an adjustment independently between pole frequency and quality factor. The operating frequency limit of this filter is about 0.8 GHz with 0.674 mW power consumption.The proposed current conveyor circuits and bi-quadratic filter are tested by TSPICE using CMOS 0.18 µm TSMC technology with ±0.8 V supply voltage to verify the theoretical results.