Power cycle reliability of Cu nanoparticle joints with mismatched coefficients of thermal expansion

The power cycle reliability of Cu nanoparticle joints between Al₂O₃ heater chips and different heat sinks (Cu-40 wt.%Mo, Al-45 wt.%SiC and pure Cu) was studied to explore the effect of varying the mismatch in the coefficient of thermal expansion (CTE) between the heater chip and the heat sink from 4.9 to 10.3 ppm/K. These joints were prepared under a hydrogen atmosphere by thermal treatment at 250, 300 and 350 °C using a pressure of 1 MPa, and all remained intact after 3000 cycles of 65/200 °C and 65/250 °C when the CTE mismatch was less than 7.3 ppm/K, despite vertical cracks forming in the sintered Cu. When the CTE mismatch was 10.3 ppm/K, the Cu nanoparticle joint created at 300 °C endured the power cycle tests, but the joint created at 250 °C broke by lateral cracks in the sintered Cu after 1000 cycles of 65/200 °C. The Cu nanoparticle joint created at 350 °C also broke by vertical cracks in the heater chip after 1000 cycles of 65/250 °C, suggesting that although sintered Cu can be strengthened to tolerate the stress by increasing the joint temperature, this eventually causes the weak and brittle chip to fracture through accumulated stress. The calculation results of stresses on the heater chip showed that the stress can be higher than the strength of Al₂O₃ when the CTE mismatch is 10.3 ppm/K and the Young's modulus of the sintered Cu is higher than 20 GPa, suggesting that the heater chip can be broken.     

Reliability of Cu nanoparticle joint for high temperature power electronics

Power cycle reliability of Cu nanoparticle joint has been studied for high temperature operation of power devices. Al₂O₃ heater chips and Cu–65 wt% Mo baseplates were joined by Cu nanoparticles and Sn–0.7Cu and power cycle tests of 65/200 °C and 65/250 °C were carried out on the joints. The Cu nanoparticles were prepared by reducing Cu carbonate in ethylene glycol with dodecanoic acid + dodecyl amine (C12) and decanoic acid and decyl amine (C10) as capping agents. A power cycle test of 65/200 °C did not inflict severe damage on the Cu nanoparticle joints so that there were not many cracks formed after 3000 cycles. Vertical cracks were formed in the C12 Cu nanoparticle joint after 3000 cycles of 65/250 °C test, however the maximum temperature during the power cycle test did not change at all because vertical cracks did not have an effect on preventing heat flow. On the contrary, lateral cracks were completely formed in the Sn–0.7Cu soldered joint after 200 cycles of 65/200 °C test and in the C10 Cu nanoparticle joint after 360 cycles of 65/250 °C test. In these experiments, the maximum temperatures were rapidly increased because heat conduction was prevented across the formed lateral cracks.     

Development of chip-on-flex bonding using Sn-based bumps and non-conductive adhesive

We developed a reliable and low cost chip-on-flex (COF) bonding technique using Sn-based bumps and a non-conductive adhesive (NCA). Two types of bump materials were used for the bonding process: Sn bumps and Sn–Ag bumps. The bonding process was performed at 180 °C for 10 s using a thermo-compression bonder after dispensing the NCA. Sn-based bumps were easily deformed to contact Cu pads during the bonding process. A thin layer of Cu₆Sn₅ intermetallic compound was observed at the interface between Sn-based bumps and Cu pads. After bonding, electrical measurements showed that all COF joints had very low contact resistance, and there were no failed joints. To evaluate the reliability of COF joints, high temperature storage tests (150 °C, 1000 h), thermal cycling tests (−25 °C/+125 °C, 1000 cycles) and temperature and humidity tests (85 °C/85% RH, 1000 h) were performed. Although contact resistance was slightly increased after the reliability test, all COF joints passed failure criteria. Therefore, the metallurgical bond resulted in good contact and improved the reliability of the joints.     

Thermal characterization of high power LED with ceramic particles filled thermal paste for effective heat dissipation

The next generation packaging materials are expected to possess high heat dissipation capability. Understanding the needs for betterment in the field of thermal management, the present study aims at investigating the package level analysis on a high power LED. In this study, commercially available thermal paste was heavily filled with ceramic particles of aluminium nitride (AlN) and boron nitride (BN) in order to enhance the heat dissipation of the device. Different particle sizes of AlN and BN fillers were incorporated homogenously into the thermal paste and applied as a thermal interface material (TIM) for an effective system level analysis employing thermal transient measurement. It was found that AlN TIM achieve less LED junction temperature by a difference of 2.20 °C compared to BN filled TIM. Furthermore, among D₅₀ = 1170 nm, 813 nm and 758 nm, the AlN at D₅₀ = 1170 nm was found to exhibit the lowest junction temperature of 38.49 °C and the lowest total thermal resistance of 11.33 K/W compared to the other two fillers.     

An investigation of the reliability of solderable ICA with low-melting-point alloy (LMPA) filler

Conductive adhesives play a major role in the electronic packaging industry as an alternative to solder due to their potential advantages that include mild processing conditions and superior thermo-mechanical performance. In a conductive adhesive interconnection, adequate mechanical and electrical performance and long-term reliability are critical.In this paper, the reliability of solderable isotropic conductive adhesive (ICA) interconnections was investigated. Reliability testing was performed via thermal shock (−55 to 125 °C, 1000 cycles) and high-temperature and high-humidity tests (85 °C, 85% RH, 1000 h). The interfacial microstructure of the solderable ICA was also investigated. Additionally, the fracture mode was investigated via mechanical pull strength testing before and after the reliability test. The electrical resistance of the solderable ICA interconnection showed improved stability compared to conventional ICAs, and similar stability to conventional solder paste (Sn–3Ag–0.5Cu and Sn–58Bi) due to the metallurgical interconnection formed by the molten LMPA fillers between the corresponding metallization layers. After the reliability tests, the grown IMC layer was composed of Cu₆Sn₅ (η-phase) and Cu₃Sn (ε-phase), and the scallop-type IMC transformed into a layer-type IMC. The fracture propagated along the Cu–Sn IMC/SnBi interface and the fracture surface showed a semi-brittle fracture mode mixed with cleavage and ductile tear bands.     

Effect of elevated temperature on PCB responses and solder interconnect reliability under vibration loading

In this paper, vibration tests are conducted to investigate the influence of temperature on PCB responses. A set of combined tests of temperature and vibration is designed to evaluate solder interconnect reliability at 25 °C, 65 °C and 105 °C. Results indicate that temperature significantly affects PCB responses, which leads to remarkable differences in vibration loading intensity. The PCB eigenfrequency shifts from 290 Hz to 276 Hz with an increase of test temperature from 25 °C to 105 °C, during which the peak strain amplitude is almost the same.Vibration reliability of solder interconnects is greatly improved with temperature rise from 25 °C to 105 °C. Mean time to failure (MTTF) of solder joint at 65 °C and 105 °C is increased by 70% and 174% respectively compared to that of solder joint at 25 °C. Temperature dominates crack propagation path of solder joint during vibration test. Crack propagation path is changed from the area between intermetallic compound (IMC) layer and Cu pad to the bulk solder with temperature increase.     

High temperature degradation of palladium coated copper bond wires

High temperature storage lifetime tests of palladium coated copper bond wires (pcc-wires) beyond 1000 h@150 °C lead to an increased number of broken stitches during wire bond pull test. In this article we show that there is an intrinsic degradation of pcc-wires: defects in the Pd layer allow a temperature driven diffusion of Cu to the Pd surface reacting to CuO on the wire surface. Voids in the range of several microns in the Cu wire core weaken the bond wire strength to very low values.The degradation mechanism of pcc-wires is found in both cases, in molded packages and at non-molded wires from the spool. We present results after temperature storage at 150 °C, 175 °C, 200 °C, and 250 °C up to 3000 h.     

Young's modulus of a sintered Cu joint and its influence on thermal stress

Al₂O₃ chips and pure Cu plates were joined by Cu nanoparticles at 250 °C and 350 °C, and the Young's moduli of the sintered Cu were evaluated by nanoindentation tests. The average Young's moduli were 52.7 ± 19.8 GPa and 76.5 ± 29.7 GPa at 250 °C and 350 °C, respectively, indicating that the sintered structures were strengthened at higher temperatures. The calculation results indicated that the joint at 350 °C has a high Young's modulus, but make the stress higher than the chip strength, resulting in breakage of the chip during 65/250 °C power cycling.     

Studies on various chip-on-film (COF) packages using ultra fine pitch two-metal layer flexible printed circuits (two-metal layer FPCs)

Various fine pitch chip-on-film (COF) packages assembled by (1) anisotropic conductive film (ACF), (2) nonconductive film (NCF), and (3) AuSn metallurgical bonding methods using fine pitch flexible printed circuits (FPCs) with two-metal layers were investigated in terms of electrical characteristics, flip chip joint properties, peel adhesion strength, heat dissipation capability, and reliability. Two-metal layer FPCs and display driver IC (DDI) chips with 35 μm, 25 μm, and 20 μm pitch were prepared. All the COF packages using two-metal layer FPCs assembled by three bonding methods showed stable flip chip joint shapes, stable bump contact resistances below 5 mΩ, good adhesion strength of more than 600 gf/cm, and enhanced heat dissipation capability compared to a conventional COF package using one-metal layer FPCs. A high temperature/humidity test (85 °C/85% RH, 1000 h) and thermal cycling test (T/C test, ?40 °C to + 125 °C, 1000 cycles) were conducted to verify the reliability of the various COF packages using two-metal layer FPCs. All the COF packages showed excellent high temperature/humidity and T/C reliability, however, electrically shorted joints were observed during reliability tests only at the ACF joints with 20 μm pitch. Therefore, for less than 20 μm pitch COF packages, NCF adhesive bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for over 25 μm pitch COF applications. Furthermore, we were also able to demonstrate double-side COF using two-metal layer FPCs.     

Thermo-mechanical reliability of a multi-walled carbon nanotube-incorporated solderable isotropic conductive adhesive

Carbon nanotubes (CNTs) are considered as ideal candidates for the reinforcement of polymer composites due to their superior physical properties. In this paper, in order to investigate the influence of multi-walled carbon nanotubes (MWCNTs) on the reliability properties of solderable isotropic conductive adhesives (SICAs) with a low-melting-point alloy (LMPA), two types of SICAs (with 0.03 wt.% MWCNTs and without MWCNT) were formulated. Thermal shock (− 55 to 125 °C, 1000 cycles) and high-temperature and high-humidity (85 °C, 85% RH, 1000 h) tests were conducted on these samples. The SICA assemblies with and without MWCNTs showed stable electrical reliability properties during reliability testing; this stability was due to the formation of excellent metallurgical interconnection between corresponding metallization by the molten LMPA fillers. Although the mechanical pull strength of SICA assemblies decreased after thermal aging, due to the excessive layer growth and planarization of the IMCs, the SICA with MWCNTs showed enhanced mechanical reliability properties compared with the SICA samples without MWCNTs. This improvement in performance was caused by the enhancement effect of the MWCNTs. These results demonstrate that MWCNTs within SICAs can enhance the reliability properties of SICA joints due to their outstanding physical properties.     

Consideration of temperature and current stress testing on flip chip solder interconnects

This work discusses the experimental set-up and data interpretation for high temperature and current stress tests of flip chip solder joints using the four-point Kelvin measurement technique. The single solder joint resistance responses are measured at four different four-point Kelvin structure locations in a flip chip package. Various temperatures (i.e., 125–165 °C) and electric current (i.e., 0.6–1.0 A) test conditions are applied to investigate the solder joint resistance degradation behavior and its failure processes. Failure criterion of 20% and 50% joint resistance increases, corresponding to solder and interfacial voiding, are employed to evaluate the solder joint electromigration reliability. The absolute resistance value is substantially affected by the geometrical layout of the metal lines in the four-point Kelvin structure, and this is confirmed by finite element simulation.Different current flow directions and strengths yielded different joint resistance responses. The anode joint, where electrons flow from the die to the substrate, usually measured an earlier resistance increase than the cathode joint, where electrons flow in the opposite direction. The change in measured joint resistances can be related to solder and interfacial voiding in the solder joint except for ±1 A current load, where resistance drop mainly attributed to the broken substrate Cu metallization as a result of “hot-spot” phenomenon. The solder joint temperature increases above the oven ambient temperature by ～25 °C, ～40 °C and ～65 °C for 0.6 A, 0.8 A and 1.0 A stress current, respectively. It is found that two-parameter log-normal distribution gives a better lifetime data fitting than the two-parameter Weibull distribution. Regardless of failure criterion used, the anode joint test cells usually calculated a shorter solder joint mean life with a lower standard variation of 0.3–0.6, as compared to the cathode joint test cells with a higher standard variation of 0.8–1.2. For a typical flip chip solder joint construction, electromigration reliability is mainly determined by the under bump metallization consumption and dissolution, with intermetallic compound formation near the die side of an anode joint.     

High strain rate constitutive behavior of SAC105 and SAC305 leadfree solder during operation at high temperature

Industry migration to leadfree solders has resulted in a proliferation of a wide variety of solder alloy compositions. The most popular amongst these are the Sn–Ag–Cu family of alloys like SAC105 and SAC305. Electronics subjected to shock and vibration may experience strain rates of 1–100/s. Electronic product may often be exposed to high temperature during storage, operation and handling in addition to high strain rate transient dynamic loads during drop-impact, shock and vibration. Properties of leadfree solder alloys at high strain rates at low and high temperatures experienced by the solder joint during typical mechanical shock events are scarce. Previous studies have showed the effect of high strain rates and thermal aging on the mechanical properties of leadfree alloys including elastic modulus and the ultimate tensile strength. The ANAND viscoplastic constitutive model has been widely used to describe the inelastic deformation behavior of solders in electronic components. In this study, SAC105 and SAC305 leadfree alloys have been tested at strain rates of 10, 35, 50 and 75/s at various operating temperatures of 50 °C, 75 °C, 100 °C and 125 °C. Full-field strain in the specimen have been measured using high speed imaging at frame rates up to 75,000 fps in combination with digital image correlation. The cross-head velocity has been measured prior-to, during, and after deformation to ensure the constancy of cross-head velocity. Stress–strain curves have been plotted over a wide range of strain rates and temperatures. Experimental data for the pristine specimen has been fit to the ANAND's viscoplastic model.     

Junction temperature and reliability of high-power flip-chip light emitting diodes

In this work, infrared micro-imaging, emission microscope measurements are performed on the chip surface of flip-chip light emitting diodes (FCLEDs). The temperature deviation on the chip surface increases from 19 to 146 °C when the injection current changes from 20 to 2000 mA. When the structure of FCLED is optimized, the temperature deviation becomes smaller. And the thermal resistance is achieved to as low as 10.4 °C/W. The finite element method calculation based on the model of steady-state current field and temperature field is carried out to investigate the effects of current spreading on thermal performance of FCLED.     

Investigation on thermal fatigue of SnAgCu,Sn100C,and SnPbAg solder joints in varying temperature environments

Thermal cycling tests have been performed for a range of electronic components intended for avionic applications, assembled with SAC305, SN100C and SnPbAg solder alloys. Two temperature profiles have been used, the first ranging between −20 °C and +80 °C (TC1), and the second between −55 °C and +125 °C (TC2). High level of detail is provided for the solder alloy composition and the component package dimensions, and statistical analysis, partially supported by FE modeling, is reported. The test results confirm the feasibility of SAC305 as a replacement for SnPbAg under relatively benign thermomechanical loads. Furthermore, the test results serve as a starting point for estimation of damage accumulation in a critical solder joint in field conditions, with increased accuracy by avoiding data reduction. A computationally efficient method that was earlier introduced by the authors and tested on relatively mild temperature environments has been significantly improved to become applicable on extended temperature range, and it has been applied to a PBGA256 component with SAC305 solder in TC1 conditions. The method, which utilizes interpolated response surfaces generated by finite element modeling, extends the range of techniques that can be employed in the design phase to predict thermal fatigue of solder joints under field temperature conditions.     

Experimental analysis of Sn-3.0Ag-0.5Cu solder joint board-level drop/vibration impact failure models after thermal/isothermal cycling

Sn-3.0Ag-0.5Cu board-level lead-free solder joint drop (1000g, 1 ms)/vibration (15g, 25–35 Hz) reliability after thermal (− 40–125 °C, 1000 cycle)/isothermal (150 °C, 500 h) cycling was reported in this study. The failure performance of solder joint and testing life were analyzed under design six testing conditions (1. Single drop impact, 2. Order thermal cycling and drop impact, 3. Order isothermal cycling and drop impact, 4. Single vibration 5. Order thermal cycling and vibration 6. Order isothermal cycling and vibration). The results revealed that the pre-cracks initiation during thermal cycling do not affect the solder joint drop impact reliability, but decrease the vibration reliability. The formation of voids weaken both drop and vibration reliability of solder joint. After thermal cycling, the crack initiated from β-Sn near IMC layer, and continued propagation through the same path when under second in order vibration impact. But propagation path turn to IMC layer when under second in order drop impact. The drop life increases from 41 times to 49 times, and vibration life decrease from 77 min to 45 min. After isothermal cycling, the formation of voids let the cracks occurred at IMC layer under second in order no matter drop impact or vibration. The drop and vibration life is 19 times and 62 min respectively.     

Strength determination of high-power LED die using point-load and line-load tests

The strength of high-power light emitting diode (LED) dies, cut from wafers with a laser, has to be determined for the need of design and quality control in order to assure the good reliability of packages in manufacturing and service. The objective of this study is to determine the strength of high-power LED die with a size of 1 × 1 × 0.1 mm³ by point-load test (PLT) and line-load test (LLT) associated with a plate-on-elastic-foundation configuration. ANSYS (one of commercial finite element codes) analysis is used to calculate the stress distributions of the die under both PLT and LLT. The ANSYS models of the PLT and LLT are validated by comparing with experimental force–displacement curves, and the results are further used to convert the die failure force from the tests into the die strength. The mechanism of tensile-stress dominated die strength has been discussed and validated in detail via these test results and analyses. The results of the PLT and LLT also indicate that for the die failure on chip surface, the average die strengths are about 1.44 GPa and 1.52 GPa from the PLTs with two different-radius pins, and about 1.2 GPa from the LLT. On the other hand, for failures on sapphire surface, the average die strengths are reasonably about 1.49 GPa and 1.26 GPa from the two PLTs, but the average one from the LLT is about 0.64 GPa (with less than 50% of the values from the PLT). The inconsistent data between two PLT and LLT for failure on sapphire surfaces were found to result from the edge chipping of the die specimen observed by scanning electron microscopy. It was also observed that the thin-layer GaN material has to be taken into account in the ANSYS analyses with a bi-material model of the LED die for precisely determining the die strength for failure on the chip surface. Otherwise, these strength data would be overestimated by a few tens of percent with a uni-material model of the LED die. All in all, this study has successfully demonstrated that the LED die strength can be determined by these feasible, easy-to-use and reliable test methods.     

Crystal growth of AlN: Effect of SiC substrate

The morphology of AlN crystal grown under the same growth conditions by the PVT method on four kinds of 4H-SiC substrates (SiC (0001), SiC (000−1), 8° off-axis SiC (0001), and 8° off-axis SiC (000−1), off-oriented from the basal plane toward the 〈11–20〉 direction) was investigated. It is found that the nucleation more easily occurs on the Si face substrate than on the C face substrate at 1800–1900 °C. Hexagonal flakes nucleated on the SiC (0001) substrate, while tetrahedral grains nucleated on the 8° off-axis SiC (0001) substrate. AlN grown on the 8° off-axis SiC (000−1) substrate was strikingly different, and flower pattern structure AlN deposited on the substrate. A stepped structure with smooth terraces was obtained on the 8° off-axis SiC (0001) substrate at 1900 °C for 4 h. We conclude that the AlN grown on the 8° off-axis SiC (0001) substrate was first by island nucleation then by the step-flow growth mode.     

Optimization and validation of thermal management for a RF front-end SiP based on rigid-flex substrate

This paper mainly presents a new 3D stacking RF System-in-Package (SiP) structure based on rigid-flex substrate for a micro base station, with 33 active chips integrated in a small package of 5cm × 5.5cm × 0.8cm. Total power consumption adds up to 20.1 Watt. To address thermal management and testability difficulties of this RF SiP, a thermal test package is designed with the same package structure and assembly flow, only replacing active chips with thermal test dies (TTDs). Optimization and validation of thermal management for the thermal test package is conducted. Effects of the structure, chip power distribution, and ambient temperature aspects on the thermal performance are studied. Thermal vias designed in the organic substrate provide a direct heat dissipation path from TTDs to the top heatsink, which minimizes junction temperature gap of the top substrate from 31.2 °C to 5.3 °C, and enables junction temperatures of all the chips on the face to face structure to be well below 82 °C. Chip power distribution optimization indicates placing high power RF parts on the top rigid substrate is a reasonable choice. The ambient temperature optimizes with forced air convection and cold-plate cooling method, both of which are effective methods to improve thermal performances especially for this micro base station application where environment temperature may reach more than 75 °C. The thermal management validation is performed with a thermal test vehicle. Junction temperatures are compared between finite-volume-method (FVM) simulation and thermal measurement under the natural convection condition. The accordance of simulation and measurement validates this thermal test method. Junction temperatures of typical RF chips are all below 80 °C, which shows the effectiveness of thermal management of this RF SiP.     

Structural and electrical studies of Cu-doped CdO prepared by solid state reaction

This paper reports synthesis, crystal structure and electrical properties of Cu-doped CdO (CdO:Cu) powders. X-ray diffraction shows that majority of the samples are monophase and has the cubic structure. The limit solubility of Cu ions in CdO lattice is found to be 2 mol% (after heating at 900 °C), whereby the impurity phase was determined to be the monoclinic-CuO. For monophase CdO:Cu samples synthesized at 900 °C, the lattice parameter decreased with increasing Cu concentration. Electrical conductivity of undoped CdO and 2 mol% Cu-doped CdO (after heating at 900 °C) were found to be 79 and 191 Ω^?1 cm^?1, respectively, at 100 °C and 912 and 1549 Ω^?1 cm^?1, respectively, at 900 °C. Thus, it appears that electrical conductivity slightly increases with Cu doping. Finally, the activation energy of monophase CdO:Cu (after heating at 900 °C) is shown to decrease with Cu concentration.     

Defect and microstructural evolution in thermally cycled Cu through-silicon vias

In this study, the effect of thermal cycling on defect generation, microstructure, and RF signal integrity of blind Cu through-silicon vias (TSVs) were investigated. Three different thermal cycling profiles were used; each differentiated by their peak cycling temperature (100 °C, 150 °C, 200 °C) and the time needed to complete one cycle (cycle time). The study was performed on two Cu TSV wafer sample types; one containing large processing-induced voids (voided sample), the other without (non-voided sample). It was found that the RF signal return loss |S₁₁| of the Cu TSVs increased upon thermal cycling for both the voided and the non-voided sample types. This was attributed to the increase in the void area due to the formation of new voids, rather than the growth of preexisting voids. On the other hand, the grain orientation and grain sizes of the Cu TSVs were found to be unaffected by all studied thermal cycling conditions and sample types.