Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors

This work studies the effects of number of gate finger on the DC subthreshold characteristics of multi-finger nanoscale MOS transistors. We found in not optimally-tempered nanoscale (gate length = 90 nm) MOS transistors that the significantly deteriorated subthreshold characteristics can be effectively improved by increasing the number of gate finger. This observation was explained with a modified subthreshold slope model based on voltage-doping transformation theory. Hence, the multi-finger structure does not only enhance the operation frequency, it also improves the subthreshold DC characteristics of the nanoscale MOS transistors.     

Study of the breakdown failure mechanisms for power AlGaN/GaN HEMTs implemented using a RF compatible process

The breakdown failure mechanisms for a family of power AlGaN/GaN HEMTs were studied. These devices were fabricated using a commercially available MMIC/RF technology with a semi-insulating SiC substrate. After a 10 min thermal annealing at 425 K, the transistors were subjected to temperature dependent electrical characteristics measurement. Breakdown degradation with a negative temperature coefficient of ?0.113 V/K for the devices without field plate was found. The breakdown voltage is also found to be a decreasing function of the gate length. Gate current increases simultaneously with the drain current during the drain-voltage stress test. This suggests that the probability of a direct leakage current path from gate to the 2-DEG region. The leakage current is attributed by a combination of native and generated traps/defects dominated gate tunneling, and hot electrons injected from the gate to channel. Devices with field plate show an improvement in breakdown voltage from ～40 V (with no field plate) to 138 V and with lower negative temperature coefficient. A temperature coefficient of ?0.065 V/K was observed for devices with a field plate length of 1.6 μm.     

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4 GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4 GHz and achieves a phase noise of −130 dBc/Hz 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1 GHz to 2.60 GHz (20.83%) with a control voltage varying from 0 to 0.3 V. It achieves a peak to peak voltage of 0.59 V with an ultra low power consumption of 3.8 mW from a 0.6 V supply voltage. The output power level of the QVCO is −10 dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.     

1 Volt organic transistors with mixed self-assembled monolayer/Al2O3 gate dielectrics

Control of the threshold voltage and the subthreshold swing is critical for low voltage transistor operation. In this contribution, organic field-effect transistors (OFETs) operating at 1 V using ultra-thin (∼4 nm), self-assembled monolayer (SAM) modified aluminium oxide layers as the gate dielectric are demonstrated. A solution-processed donor–acceptor semiconducting polymer poly(3,6-di(2-thien-5-yl)-2,5-di(2-octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione)thieno[3,2-b]thiophene) (PDPP2TTT) is used as the active layer. It is shown that the threshold voltage of the fabricated transistors can be simply tuned by carefully controlling the composition of the applied SAM. The optimised OFETs display threshold voltages around 0 V, low subthreshold slopes (150 ± 5 mV/dec), operate with negligible hysteresis and show average saturated field-effect mobilities in excess of 0.1 cm²/V s at 1 V.     

Gate leakage current suppression and reliability improvement for ultra-low EOT Ge MOS devices by suitable HfAlO/HfON thickness and sintering temperature

Ultra-low effective oxide thickness (EOT) Ge MOS devices with different HfAlO/HfON stacks and sintering temperatures are investigated in this work. The suppression of gate leakage current and improvement of reliability properties can be achieved by either stacked gate dielectrics or a low sintering temperature. Especially, the qualities of the interface and high-k gate dielectric in Ge devices are significantly improved through a low sintering temperature. A 0.5 nm HfAlO/2.5 nm HfON gate stack and a sintering temperature at 350 °C are the suitable conditions to achieve low EOT, gate leakage, and good reliability for Ge MOS devices.     

Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors

Silicon on insulator (SOI) substrates offer a promising platform for monolithic high energy physics detectors with integrated read-out electronics and pixel diodes. This paper describes the fabrication and characterisation of specially-configured SOI substrates using improved bonded wafer ion split and grind/polish technologies. The crucial interface between the high resistivity handle silicon and the SOI buried oxide has been characterised using both pixel diodes and circular geometry MOS transistors. Pixel diode breakdown voltages were typically greater than 100 V and average leakage current densities at 70 V were only 55 nA/cm². MOS transistors subjected to 24 GeV proton irradiation showed an increased SOI buried oxide trapped charge of only 3.45 × 10¹¹ cm^?2 for a dose of 2.7 Mrad.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

Characteristics of Ni/SiC Schottky diodes grown by ICP-CVD

A Ni/SiC Schottky diode was fabricated with an α-SiC thin film grown by the inductively coupled plasma chemical vapor deposition, ICP-CVD method on a (1 1 1) Si wafer. The α-SiC film was grown on a carbonized Si layer that the Si surface had been chemically converted to a very thin SiC layer by the ICP-CVD method at 700 °C. To reduce defects between the Si and α-SiC, the surface of the Si wafer is slightly carbonized. The film characteristics of α-SiC were investigated by employing TEM and FT-IR. A sputtered Ni thin film was used for the anode metal. The boundary status of the Ni/SiC contact was investigated by AES as a function of annealing temperature. It is shown that the ohmic contact could be acquired below 1000 °C annealing temperature. The forward voltage drop of the Ni/α-SiC Schottky diode is 1.0 V at 100 A/cm². The breakdown voltage is 545 V which is five times larger than the ideal breakdown voltage of a silicon device. Also, the dependence of barrier height on temperature was observed.     

CCD image sensor with compensated reset operation

A low voltage charge coupled device (CCD) image sensor has been developed by adjusting the electron potential barrier in the electron sensing structure. A charge injection to the gate dielectrics of a MOS transistor was utilized to optimize the electron potential level in the output structure. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2 V to 5.5 V, which is suitable for compensating the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole–Frenkel conduction and Fowler–Nordheim conduction. A CCD image sensor with 492(H) × 510(V) pixels adopting this structure showed complete reset operation with the driving voltage of 3.0 V. The image taken with the image sensor utilizing this structure was not saturated to the illumination of 30 lux, that is, showed no image distortion.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques

A CMOS analogue current-mode multiplier/divider circuit is presented. It is based on a dynamic biasing applied at the bulk terminal of MOS transistors operating in both saturation and triode. With the proposed structure, the multiplier forms a feedback loop that improves the current swing and accuracy. The multiplier has been fabricated using a standard 0.18 µm CMOS technology. The circuit consumes 144 µW using a single supply voltage of 1.8 V with a measured THD lower than 1% for an output current of 38 µA, and requires a die area of 90 µm x 45 µm.     

Low temperature fabrication of a ZnO nanoparticle thin-film transistor suitable for flexible electronics

A bottom-gate/top-drain/source contact ZnO nanoparticle thin-film transistor was fabricated using a low temperature annealing process (150 °C) suitable for flexible electronics. Additionally, a high-k resin filled with TiO₂ nanoparticles was used as gate dielectric. After fabrication, the transistors presented almost no hysteresis in the I–V curve, a threshold voltage (V_T) of 2.2 V, a field-effect mobility on the order of 0.1 cm²/V s and an I_ON/I_OFF ratio of about 10⁴. However, the transistor is sensitive to aging effects due to interactions with the ambient air, resulting in current level reduction caused by trapped oxygen at the nanoparticle surface, and an anti-clockwise hysteresis in the transfer curve. It was demonstrated, conjointly, the possible desorption of oxygen by voltage stress and UV light exposure.     

High-performance pentacene field-effect transistors using Al2O3 gate dielectrics prepared by atomic layer deposition (ALD)

High-performance pentacene field-effect transistors have been fabricated using Al₂O₃ as a gate dielectric material grown by atomic layer deposition (ALD). Hole mobility values of 1.5 ± 0.2 cm²/V s and 0.9 ± 0.1 cm²/V s were obtained when using heavily n-doped silicon (n⁺-Si) and ITO-coated glass as gate electrodes, respectively. These transistors were operated in enhancement mode with a zero turn-on voltage and exhibited a low threshold voltage (< −10 V) as well as a low sub-threshold slope (<1 V/decade) and an on/off current ratio larger than 10⁶. Atomic force microscopy (AFM) images of pentacene films on Al₂O₃ treated with octadecyltrichlorosilane (OTS) revealed well-ordered island formation, and X-ray diffraction patterns showed characteristics of a “thin film” phase. Low surface trap density and high capacitance density of Al₂O₃ gate insulators also contributed to the high performance of pentacene field-effect transistors.     

Modeling and design of a monolithically integrated power converter on SiC

To fully explore the high temperature and high power density potential of the 4H-SiC material, not only power devices need to be fabricated on SiC, but also the circuitries for signal generation/processing, gate driver and control. In this paper, static and dynamic characteristics of SiC lateral JFET (LJFET) devices are numerically simulated and compact circuit models developed. Based on these models, analog and digital integrated circuits functional blocks such as OPAMP, gate driver and logic gates are then designed and simulated. Finally, a fully integrated power converter including pulse-width-modulation circuit, over-temperature protection circuit and a power boost converter is designed and simulated. The converter has an input of 200 V and an output voltage of 400 V, 2.5 A, operating at 1 kW and 5 MHz.     

Complementary-like inverters based on an ambipolar solution-processed molecular bis(naphthalene diimide)-dithienopyrrole derivative

We report on high-mobility top-gate organic field-effect transistors (OFETs) and complementary-like inverters fabricated with a solution-processed molecular bis(naphthalene diimide)-dithienopyrrole derivative as the channel semiconductor and a CYTOP/Al₂O₃ bilayer as the gate dielectric. The OFETs showed ambipolar behavior with average electron and hole mobility values of 1.2 and 0.01 cm² V^?1 s^?1, respectively. Complementary-like inverters fabricated with two ambipolar OFETs showed hysteresis-free voltage transfer characteristics with negligible variations of switching threshold voltages and yielded very high DC gain values of more than 90 V/V (up to 122 V/V) at a supply voltage of 25 V.     

Novel organic inverters with dual-gate pentacene thin-film transistor

We report on the fabrication and characterization of dual-gate pentacene organic thin-film transistors (OTFTs) with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al₂O₃ as a bottom-gate dielectric and PEALD 200 nm thick Al₂O₃ as a top-gate dielectric. The V_th of dual-gate OTFT has changed systematically with the application of voltage bias to top-gate electrode. When voltage bias from −10 V to 10 V is applied to top gate, V_th changes from 1.95 V to −9.8 V. Two novel types of the zero drive load logic inverter with dual-gate structure have been proposed and fabricated using PEALD Al₂O₃ gate dielectrics. Because the variation of V_th due to chemical degradation and the spatial variation of V_th are inherent in OTFTs, the compensation technology by dual-gate structure can be essential to OTFT applications.     

On the short-circuit and avalanche ruggedness reliability assessment of SiC MOSFET modules

This paper provides an insight into the operational robustness of commercially available SiC MOSFET power modules, during short-circuit (SC) and unclamped inductive switching (UIS) test environments. A set of five different power modules from three vendors rated from 1.2–1.7 kV and with various current ratings have been evaluated, where the possible failure mechanisms that cause the breakdown of the modules have been addressed. The SC pulse duration of the modules was gradually increased until the failure occurred. A critical short circuit energy in the order of 4.0–8.0 J was observed at a supply voltage of 800 V and a pulse duration of 4.0 μs. At lower supply voltage of 500 V, all modules survived until 10.0 μs. One of the modules, rated at 1.7 kV, survived SC tests at voltages up to 1000 V for a pulse duration of 4 μs, but failed when the supply voltage was increased to 1100 V. Prior to failure, a gate-source voltage drop has been recorded, which is associated with a high G-S leakage current. The main failure mechanism, however, is the thermal runaway which leads the devices into avalanche breakdown mode. During the UIS tests, multiple samples from the three vendors of the power modules failed. The failure of the modules was always caused by the external diode connected in parallel with the MOSFETs. One of the modules from the same vendor which does not have external diode and another module from a different vendor with external diode survived the UIS tests under nominal test conditions.     

Self-aligned flexible organic thin-film transistors with gates patterned by nano-imprint lithography

Many applications that rely on organic electronic circuits still suffer from the limited switching speed of their basic elements – the organic thin film transistor (OTFT). For a given set of materials the OTFT speed scales inversely with the square of the channel length, the parasitic gate overlap capacitance, and the contact resistance. For maximising speed we pattern transistor channels with lengths from 10 μm down to the sub-micrometre regime by industrially scalable UV-nanoimprint lithography. The reduction of the overlap capacitance is achieved by minimising the source–drain to gate overlap lengths to values as low as 0.2 μm by self-aligned electrode definition using substrate reverse side exposure. Pentacene based organic thin film transistors with an exceptionally low line edge roughness <20 nm of the channels, a mobility of 0.1 cm²/Vs, and an on–off ratio of 10⁴, are fabricated on 4″ × 4″ flexible substrates in a carrier-free process scheme. The stability and spatial distribution of the transistor channel lengths are assessed in detail with standard deviations of L ranging from 185 to 28 nm. Such high-performing self-aligned organic thin film transistors enabled a ring-oscillator circuit with an average stage delay below 4 μs at an operation voltage of 7.5 V.     

A low power current controllable single-input three-output current-mode filter using MOS transistors only

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8 V and using 0.18 μm CMOS process parameters. The power consumption and the required chip area are only 0.5 mW and 77.4 μm × 70.2 μm, respectively.