Impact of switching frequencies on the TID response of SiC power MOSFETs

Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MOSFETs are investig-ated under different switching frequencies from 1 kHz to 10 MHz.A significant shift was observed in the threshold voltage as the frequency increased,which resulted in premature failure of the drain-source breakdown voltage and drain-source leakage current.The degradation is attributed to the high activation and low recovery rates of traps at high frequencies.The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching fre-quency of SiC power MOSFETs.     

Resonant gate driver with efficient gate energy recovery and switching loss reduction

This article describes a novel resonant gate driver for charging the gate capacitor of power metal-oxide semiconductor field-effect-transistors (MOSFETs) that operate at a high switching frequency in power converters. The proposed resonant gate driver is designed with three small MOSFETs to build up the inductor current in addition to an inductor for temporary energy storage. The proposed resonant gate driver recovers the CV² gate loss, which is the largest loss dissipated in the gate resistance in conventional gate drivers. In addition, the switching loss is reduced at the instants of turn on and turn off in the power MOSFETs of power converters by using the proposed gate driver. Mathematical analyses of the total loss appearing in the gate driver circuit and the switching loss reduction in the power switch of power converters are discussed. Finally, the proposed resonant gate driver is verified with experimental results at a switching frequency of 1 MHz.     

Mechanism of device degradation in n- and p-channel polysiliconTFTs by electrical stressing

The effects of electrical stress on hydrogenated n- and p-channel polysilicon thin-film transistors are discussed. The on-state caused the most significant degradation, whereas off-state and accumulation conditions resulted in negligible degradation. The on-state stress degraded the threshold voltage, trap state density, and subthreshold sharpness of both n- and p-channel devices toward perhydrogenated values, and the rates of degradation increased with stressing biases. The field-effect mobility and leakage current, however, were not degraded by stressing. The mechanism of device degradation may be attributed to the metastable creation of midgap states within the polysilicon channel, as opposed to gate dielectric charge trapping or interface state generation     

off-State Current Limits of Narrow Bandgap MOSFETs

OFF-state current limitations of two types of MOSFETs, namely 1) flatband-mode MOSFET and 2) inversion-mode MOSFET, with narrow bandgap channel materials such as InSb, InAs, InGaAs, and Ge are discussed in conjunction with long-term requirements of the International Technology Roadmap for Semiconductors (ITRS). Flatband-mode high-mobility MOSFETs appear to be better suited for low off-state currents, in particular when a backside contact is used for minority carrier extraction. Based on off-state thermal minority carrier generation in narrow bandgap materials at room temperature, flatband MOSFETs with InSb channels appear to be applicable for high-performance logic and even low operating power requirements of the long-term ITRS; however, standby power requirements will demand InAs or channels of higher bandgap unless material and interface quality (and, thus, carrier lifetime) is substantially improved. The effects of drain-induced barrier lowering, band-to-band tunneling, impact ionization, and increased temperature on off-state currents are not considered here but may impose further restrictions     

Synchrotron x-ray irradiation effects on the device characteristics and the resistance to hot-carrier damage of MOSFETs with 4 nm thick gate oxides

The effects of synchrotron x-ray irradiation on the device characteristics and hot-carrier resistance of n- and p-channel metal oxide semiconductor field effect transistors (MOSFETs) with 4 nm thick gate oxides are investigated. In p-channel MOSFETs, device characteristics were significantly affected by the x-ray irradiation but completely recovered after annealing, while the device characteristics in n-channel MOSFETs were not noticeably affected by the irradiation. This difference appears to be due to a difference in interface-state generation. In p-channel MOSFETs, defects caused by boron-ion penetration through the gate oxides may be sensitive to x-ray irradiation, causing the generation of many interface states. These interface states are completely eliminated after annealing in hydrogen gas. The effects of irradiation on the resistance to hot-carrier degradation in annealed 4 nm thick gate-oxide MOSFETs were negligible even at an x-ray dose of 6000 mJ/cm².     

Parallel hot-carrier-induced degradation mechanisms inhydrogen-passivated polysilicon-on-insulator LDD p-MOSFET's

Hot-carrier-induced stressing has been shown to degrade hydrogen-passivated p-channel polysilicon-on-insulator (poly-SOI) MOSFETs by two parallel degradation mechanisms. The authors observe hot-carrier-induced degradation of hydrogen passivation at grain boundaries through the creation of additional donor-type grain boundary states in the channel, as well as hot-electron trapping in the gate oxide. Due to the presence of both of these degradation mechanisms, p-channel polysilicon lightly doped source and drain (LDD) MOSFETs exhibit anomalous hot-carrier-induced degradation behavior that has not been observed in bulk p-MOSFETs     

Impact of the gate driver voltage on temperature sensitive electrical parameters for condition monitoring of SiC power MOSFETs

Condition monitoring using temperature sensitive electrical parameters (TSEPs) is widely recognized as an enabler for health management of power modules. The on-state resistance/forward voltage of MOSFETs, IGBTs and diodes has already been identified as TSEPs by several researchers. However, for SiC MOSFETs, the temperature sensitivity of on-state voltage/resistance varies depending on the device and is generally not as high as in silicon devices. Recently the turn-on current switching rate has been identified as a TSEP in SiC MOSFETs, but its temperature sensitivity was shown to be significantly affected by the gate resistance. Hence, an important consideration regarding the use of TSEPs for health monitoring is how the gate driver can be used for improving the temperature sensitivity of determined electrical parameters and implementing more effective condition monitoring strategies. This paper characterizes the impact of the gate driver voltage on the temperature sensitivity of the on-state resistance and current switching rate of SiC power MOSFETs. It is shown that the temperature sensitivity of the switching rate in SiC MOSFETs increases if the devices are driven at lower gate voltages. It is also shown, that depending on the SiC MOSFET technology, reducing the gate drive voltage can increase the temperature sensitivity of the on-state resistance. Hence, using an intelligent gate driver with the capability of customizing occasional switching pulses for junction temperature sensing using TSEPs, it would be possible to implement condition monitoring more effectively for SiC power devices.     

Hot-carrier-induced time dependent dielectric breakdown in high voltage pMOSFETs

We report about the time dependent gate dielectric breakdown failure of high voltage p-channel MOSFETs submitted to hot-carrier stress. We consider the time integral of the instantaneous gate current raised to a constant exponent as a measure of the dielectric film wear out, and we check that this integral computed up to the dielectric failure time is indeed a constant not depending on the drain-source stress bias.     

A Current Source Gate Driver Achieving Switching Loss Savings and Gate Energy Recovery at 1-MHz

In this paper, a new current source gate drive circuit is proposed for power MOSFETs. The proposed circuit achieves quick turn on and turn off transition times to reduce switching loss and conduction loss in power MOSFETs. In addition, it can recover a portion of the CV gate energy normally dissipated in a conventional driver. The circuit consists of four controlled switches and a small inductor (typically 100 nH or less). The current through the inductor is discontinuous in order to minimize circulating current conduction loss. This also allows the driver to operate effectively over a wide range of duty cycles with constant peak current-a significant advantage for many applications since turn on and turn off times do not vary with the operating point. Experimental results are presented for the proposed driver operating in a boost converter at 1 MHz, 5 V input, 10 V/5 A output. At 5 V gate drive, a 2.9% efficiency improvement is achieved representing a loss savings of 24.8% in comparison to a conventional driver.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对p MOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于p MOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是p MOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对pMOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于pMOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是pMOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

Hot-carrier degradation of submicrometer p-MOSFETs withthermal/LPCVD composite oxide

It is shown that while gate oxides containing thermal/LPCVD composite oxide have lower defect densities than gates using only thermal oxides, they are more susceptible to hot-carrier degradation. The hot-carrier-induced degradation of composite oxides is worse in p-channel MOSFETs than in n-channel MOSFETs. This sensitivity of p-channel MOSFETs is caused by higher electron trapping levels in LPCVD oxides. For 150-Å gate technology, the hot-carrier-degradation resistance of thermal/LPCVD composite gate oxides with a 70-Å or thicker thermal oxide layer approaches that of high-quality pure thermal oxide     

Hot-electron-induced instability in 0.5-μm p-channel MOSFETspatterned using synchrotron X-ray lithography

Radiation damage caused by X-ray includes positive oxide charge, neutral traps, and interface states. Although several annealing steps are performed throughout the entire fabrication process, the radiation damage, particularly neutral traps, is not completely annealed out. The hot-electron-induced instability in p-channel MOSFETs is significantly increased due to the enhanced electron trapping in the oxide by residual traps. However, the degradation in n-channel MOSFETs due to channel-hot carriers is not significantly increased by X-ray lithography since n-channel MOSFETs are susceptible to interface state generation by hot carriers but are relatively insensitive to the degradation due to electron trapping. The results suggest that p-channel MOSFETs in addition to n-channel MOSFETs need to be carefully examined for hot carrier-induced instability in CMOS VLSI circuits patterned using X-ray lithography and/or when the radiation damage is incurred in the back-end-of-the-line processing     

A spillover effect of avalanche-generated electrons in buriedp-channel MOSFET's

The authors describe a new mechanism for hot-electron resistance in buried p-channel MOSFETs, which is explained by the spillover of avalanche-generated electrons into the bulk. This effect was observed in a buried p-channel MOSFET formed in a retrograde n-well. It is shown that this effect reduces the hot-electron-induced device degradation even with the greater number of avalanche-generated electrons induced by high bulk doping     

Low-power and high-stability SRAM technology using alaser-recrystallized p-channel SOI MOSFET

Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked over bottom n-channel bulk MOSFETs for both drivers and transfer gates. A sufficient laser power assures the same leakage currents between SOI MOSFETs fabricated on an undulated insulating layer in memory cell regions and on an even insulating layer in field regions. The on/off ratio of the SOI MOSFETs is increased by a factor of 10⁴, and the source-drain leakage current is decreased by a factor of 10-10² compared with those of polysilicon thin-film transistors (TFTs) fabricated by using low-temperature regrowth of amorphous silicon. A test 256-kb SRAM fabricated this technology shows improved stand-by power dissipation and cell stability. The process steps can be decreased to 83% of those TFT load SRAMs if both the peripheral circuit and memory cells are made with p-channel SOI and n-channel bulk MOSFETs     

Noise performance of Si/Si/sub 1-x/Ge/sub x/ FETs

Noise characteristics are evaluated for SiGe/Si based n-channel MODFETs and p-channel MOSFETs. The analysis is based on a self-consistent solution of Schrodinger and Poisson's equations. The model predicts a superior minimum noise figure for an n-channel MODFET at 77 K. P-channel MOSFETs behave similar to n-channel devices operating at 300 K. Minimum noise figure decreases with increasing quantum well (QW) width for both n- and p-channel devices. However, the p-channel devices are less sensitive to QW width variation. Minimum noise temperature behaves similarly. As observed, a range of doped epilayer thickness exists where minimum noise figure is a minimum for both n- and p-channel FETs.<>     

Performance and reliability design issues for deep-submicrometerMOSFETs

Device design constraints, such as threshold voltage variation due to short-channel and drain-induced-barrier-lowering effects, off-state leakage current due to punchthrough and gate-induced drain leakage, hot-carrier effects such as hot-electron degradation and avalanche breakdown, and time-dependent dielectric breakdown, are examined. The current-driving capability, ring-oscillator switching speed, and small-signal voltage gain are examined. The impact that each of these factors has on the allowable choice of MOSFET channel length, oxide thickness, and power supply voltage is examined. Based on experimental results, a set of design curves, using a set of typical performance and reliability criteria, is presented for deep-submicrometer nonlightly doped drain (non-LDD) n-channel devices. From these curves, the relative importance of each particular performance/reliability mechanism for a given technology and design criteria can be determined. Because the performance and reliability issues addressed are also relevant to other MOSFET technologies, the design guidelines can also be extended to other technologies, including p-channel and LDD devices     

Monte Carlo simulation of p- and n-channel GOI MOSFETs by solving the quantum Boltzmann equation

The scaling characteristics of both n- and p-channel Ge-on-insulator (GOI) as well as silicon-on-insulator (SOI) MOSFETs with channel length ranging from 20-130 nm are studied by a two-dimensional self-consistent fullband Monte Carlo device simulator. The transistors' intrinsic performance and subthreshold characteristics are investigated for various channel lengths and Ge layer thicknesses. Our results indicate that both n- and p-channel GOI MOSFETs can be scaled down to the nanoregion, due to the nonstationary transport, especially for the p-channel device. More than 10% performance improvement for nMOS and about 20% for pMOS can be achieved in GOI even when channel length is scaled down to 20 nm, as compared to SOI devices. However, the GOI devices suffer from more severe short channel effect and have larger p-n junction leakage current as compared to SOI counterpart. For high-performance CMOS applications, GOI devices are feasible if the junction leakage can be reduced by optimizing the device structure.     

Hot-carrier degradation mechanisms in silicon-On-Insulator MOSFETS

The structure, operation principles and basic characteristics of SOI MOSFETs are evoked, before focusing on the degradation aspects. The hot-carrier injection into the front gate oxide and buried oxide is discussed as a function of silicon film thickness, transistor configuration (n- or p-channel, inversion- or accumulation-mode), and stressing bias. The special phenomena involved in ultra-thin, fully-depleted SIMOX MOSFETs are compared to those governing partially-depleted and bulk-equivalent transistors. It is demonstrated that the coupling between back-interface defects and front channel properties is a unique and very challenging degradation feature in SOI. The road map to reach an accurate electrical image of the degraded transistor, by accounting for coupling effects or by avoiding them, is described. Although the aging mechanisms and investigation methods are more sophisticated than in bulk Si, the degradation of SOI MOSFETs does not appear to impede on the development of high performance, low-voltage ULSI SOI circuits.     

Evaluation of high-voltage 4H-SiC switching devices

In this paper, the on-state and switching performance of 4H-SiC UMOSFETs, TIGBTs, BJTs, SIThs, and GTOs with voltage ratings from 1 to 10 kV are simulated at different temperatures. Comparison with silicon devices highlights the advantages of SiC technology. SiC BJTs suffer the same problem as Si BJTs, namely the degradation of current gain with increased voltage rating which makes them unsuitable for applications above 4 kV. SiC MOSFETs dominate applications below 4 kV for their attractive conduction performance and advantages such as ease of use. Above 3 kV, SiC MOSFETs are not as attractive as SiC bipolar devices because of their high on-state voltages. In the voltage range simulated, SiC IGBTs, SIThs, and GTOs have comparable current handling ability. Considering the GTOs slow switching speed and drive complexities, IGBTs and SIThs are a better choice in the voltage range 4-10 kV. Calculations based on conduction loss and switching loss indicate that SiC SIThs are superior to IGBTs except in high-temperature and high-frequency applications where IGBTs are better. The need to provide a large gate current during turnoff and turn-off failure caused by gate debiasing, decreases the attractiveness of the SITh