HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

A methodology for projecting SiO2 thick gate oxide reliability on trench power MOSFETs and its application on MOSFETs VGS rating

In this work, a methodology based on the E-model for the reliability projection of a thick (> 20 nm) SiO₂ gate oxide on a vertical trench power MOSFET, is presented. Experimental results suggest that a Logic Level (LL) trench MOSFET with 35 nm of gate oxide can be rated at V_GS = + 12 V if one assumes continuous DC Gate-Source bias of V_GS = + 12 V at T = 175 °C for 10 years at a defect level of 1 Part Per Million (PPM). We will demonstrate that if we take into account MOSFET device lifetime as dictated by the Automotive Electronics Council (AEC Q101) mission profile, then devices can be rated higher to V_GS = + 14.7 V at T = 175 °C for the same PPM level (1 PPM). The application of the methodology for establishing the oxide thickness, t_ox, for any required voltage rating, is discussed.     

Temperature-dependent ambipolar electrical characteristics of pentacene-based thin-film transistors: The impact of opposite-sign charge carriers

The temperature-dependent electrical and charge transport characteristics of pentacene-based ambipolar thin-film transistors (TFTs) were investigated at temperatures ranging from 77 K to 300 K. At room temperature (RT), the pentacene-based TFTs exhibit balanced and high charge mobility with electron (μ_e) and hole (μ_h) mobilities, both at about 1.6 cm²/V s. However, at lower temperatures, higher switch-on voltage of n-channel operations, almost absent n-channel characteristics, and strong temperature dependence of μ_e indicated that electrons were more difficult to release from opposite-signed carriers than that of holes. We observed that μ_e and μ_h both followed an Arrhenius-type temperature dependence and exhibited two regimes with a transition temperature at approximately 210–230 K. At high temperatures, data were explained by a model in which charge transport was limited by a dual-carrier release and recombination process, which is an electric field-assisted thermal-activated procedure. At T < 210 K, the observed activation energy is in agreement with unipolar pentacene-based TFTs, suggesting a common multiple trapping and release process-dominated mechanism. Different temperature-induced characteristics between n- and p-channel operations are outlined, thereby providing important insights into the complexity of observing efficient electron transport in comparison with the hole of ambipolar TFTs.     

High-performance diketopyrrolopyrrole-based organic field-effect transistors for flexible gas sensors

We demonstrate high-performance flexible polymer OFETs with P-29-DPP-SVS in various geometries. The mobilities of TG/BC OFETs are approximately 3.48 ± 0.93 cm²/V s on a glass substrate and 2.98 ± 0.19 cm²/V s on a PEN substrate. The flexible P-29-DPP-SVS OFETs exhibit excellent ambient and mechanical stabilities under a continuous bending stress of 1200 times at an R = 8.3 mm. In particular, the variation of μ_FET, V_Th and leakage current was very negligible (below 10%) after continuous bending stress. The BG/TC P-29-DPP-SVS OFETs on a PEN substrate applies to flexible NH₃ gas sensors. As the concentration of NH₃ increased, the channel resistance of P-29-DPP-SVS OFETs increased approximately 100 times from ∼10⁷ to ∼10⁹ Ω at V_SD = −5 V and V_GS = −5 V.     

Temperature dependences of threshold voltage and drain-induced barrier lowering in 60 nm gate length MOS transistors

The temperature dependence of threshold voltage (V_T) and drain-induced barrier lowering (DIBL) characteristics for MOS transistors fabricated with three different threshold voltage technologies are studied. We found that the technique employed to adjust the V_T value make the devices to be not well-scaled for short-channel effects for ultra-short devices at low temperatures. For devices with a short gate length (L<90 nm) and being fabricated using the low threshold voltage (low-V_T) technology, both the temperature dependencies of threshold voltage and DIBL are different to the standard-V_T and high-V_T ones. Abnormally large values of DIBL were found for low V_T-devices because of the significant encroachment of drain depletion region on the channel region. On the other hand, the high substrate doping in high-V_T process makes the devices to have a larger junction depth than that used in the standard process. It causes a poorer DIBL for short-channel devices. Hence the best scaling or design of the devices at room temperature does not imply that they should also be good at low temperatures, especially for L = 60 nm fabricated using the low-V_T process. Different device design and process optimization are required for devices to be operated at temperatures beyond the nominal range.     

Field and hot electron-induced degradation in GaN-based power MIS-HEMTs

We investigate the degradation of AlGaN/GaN MIS-HEMTs submitted to gate step-stress experiments, and demonstrate the existence of field- and hot-electron induced processes. When the devices are submitted to gate-step stress with high V_DS > 50 V, four different regimes are identified: (i) for V_GS < − 10 V, no significant degradation is observed, since the devices are in the off-state; (ii) for − 10 V < V_GS < 0 V, hot electrons flow through the channel, as demonstrated by the (measurable) electroluminescence signal. These hot electrons can be trapped within device structure, inducing an increase in the threshold voltage. (iii) for V_GS > 0 V, the density of hot electrons is significantly reduced, due to the increased interface scattering and device temperature. As a consequence, EL signal drops to zero, and the electrons trapped during phase (ii) are de-trapped back to the channel, where they are attracted by the high 2DEG potential. (iv) Finally, for V_GS > 5 V, a significant increase in threshold voltage is detected. This effect is observed only for high positive voltages, i.e. when a significant leakage current flows through the gate. Such gradual degradation is ascribed to the injection of electrons from the 2DEG to the gate insulator, which is a field-driven effect. These results were obtained by combined electrical and optical characterization carried out at different voltages during the step stress.     

A comparative study of electrical and optical properties of InN and In0.48Ga0.52N

We present results of our studies concerning electrical and optical properties of In_0.48Ga_0.52N and InN. Hall measurement were carried out at temperatures between T=77 and 300 K. Photoluminescence (PL) spectrum in InN and In_0.48Ga_0.52N. InN has a single peak at 0.77 eV at 300 K. However, the PL in In_0.48Ga_0.52N has two peaks; a prominent peak at 1.16 eV and a smaller peak at 1.55 eV. These two peaks are attributed to Indium segregation corresponding to a high Indium concentration of 48% and a low concentration of 36%. High electric field measurements indicate that drift velocity that tends to saturate at around V_d=1.0×10⁷ cm/s at 77 K in InN at an electric field of F=12 kV/cm. However, in In_0.48Ga_0.52N the I–V curve is almost linear up to an electric field of F=45 kV/cm, where the drift velocity is V_d=1.39×10⁶ cm/s. At applied electric fields above this value a S-type negative differential resistance (NDR) is observed leading to an instability in the current and to the irreversible destruction of the sample.     

Investigation on the thermal behavior of 0.15 μm gate-length In0.4Al0.6As/In0.4Ga0.6As MHEMT

In this study, we have successfully investigated the electrical performances of In_0.4Al_0.6As/In_0.4Ga_0.6As metamorphic high-electron-mobility transistor (MHEMT) at temperatures range from 275 K to 500 K comprehensively. By extracting the device S-parameters, the temperature dependent small signal model has been established. At room temperature, 0.15 μm T-gate device with double δ-doping design exhibits f_T and f_MAX values of 103 GHz and 204 GHz at V_ds = 1 V, an extrinsic transconductance of 678 mS/mm, and a current density of 578 mA/mm associated with a high breakdown voltage of ?13 V. Power measurements were evaluated at 40 GHz and the measured output power, linear power gain, and maximum power-added efficiency, were 7.12 dBm, 10.15 dB, and 23.1%, respectively. The activation energy (E_a) extracted from Arrhenius plots is = 0.34 eV at 150 ≦ T ≦ 350 K. The proposed device is promisingly suitable for millimeter-wave power application.     

Improvement in negative differential conductance characteristics of hole resonant-tunneling diodes with high Ge fraction Si/strained Si1−xGex/Si(1 0 0) heterostructure

Hole resonant-tunneling diodes (RTD) with Si/strained Si_1?xGe_x heterostructures epitaxially grown on Si(1 0 0) have been fabricated and improvement in negative differential conductance (NDC) characteristics for high Ge fraction such as x = 0.5 was investigated. It is clearly shown that SiH₄ exposure at low temperatures of 400–450 °C just after Si_1?xGe_x epitaxial growth is effective to suppress surface roughness in atomic order. In the case of the RTD with x = 0.48, NDC characteristics for 1.4-nm thick Si barriers were observed at higher temperatures around 270 K than that for 2.4-nm thick Si barriers. By increasing the Ge fraction to x = 0.58, NDC characteristics were also observed at higher temperatures around 290 K than that with x = 0.48.     

Device characteristics of AlGaN/GaN MIS–HEMTs with high-k HfxZr1−xO2 (x = 0.66, 0.47, 0.15) insulator layer

This study investigates the characteristics of AlGaN/GaN MIS–HEMTs with Hf_xZr_1−xO₂ (x = 0.66, 0.47, and 0.15) high-k films as gate dielectrics. Sputtered Hf_xZr_1−xO₂ with a dielectric constant of 20–30 and a bandgap of 5.2–5.71 eV was produced. By increasing the Zr content of HfZrO₂, the V_TH shifted from −1.8 V to −1.1 V. The highest Hf content at this study reduced the gate leakage by approximately one order of magnitude below that of those Zr-dominated HFETs. The maximum I_DS currents were 474 mA/mm, 542 mA/mm, and 330 mA/mm for Hf content of 66%, 47%, 15% at V_GS = 3 V, respectively.     

Fabrication of a CoSb3-based thermoelectric module

A CoSb₃-based thermoelectric module was fabricated using Ce_0.45Co_2.5Fe_1.5Sb₁₂ p-type leg and Yb_0.25Co₄Sb₁₂/Yb₂O₃ n-type leg. Ag–Cu foil was used to construct the junction of hot side legs. With two p–n couples, the module generated a maximum output power (P_max) of 140 mW and a maximum open-circuit voltage (V_o) of 210 mV under the thermal condition of hot side temperature T_h=810 K and a temperature difference ΔT=490 K. No deterioration in output power in vacuum was seen when thermal cycle of five times for the module was carried out under T_h=810 K and ΔT=490 K with natural cooling to room temperature, which shows the module has high durability.     

Evaluation of lateral barrier height of inhomogeneous photolithography-fabricated Au/n-GaAs Schottky barrier diodes from 80 K to 320 K

In order to evaluate current conduction mechanism in the Au/n-GaAs Schottky barrier diode (SBD) some electrical parameters such as the zero-bias barrier height (BH) Φ_bo(I–V) and ideality factor (n) were obtained from the forward bias current–voltage (I–V) characteristics in wide temperature range of 80–320 K by steps of 10 K. By using the thermionic emission (TE) theory, the Φ_bo(I–V) and n were found to depend strongly on temperature, and the n decreases with increasing temperature while the Φ_bo(I–V) increases. The values of Φ_bo and n ranged from 0.600 eV and 1.51(80 K) to 0.816 eV and 1.087 (320 K), respectively. Such behavior of Φ_bo and n is attributed to Schottky barrier inhomogeneities by assuming a Gaussian distribution (GD) of BHs at Au/n-GaAs interface. In the calculations, the electrical parameters of the experimental forward bias I–V characteristics of the Au/n-GaAs SBD with the homogeneity in the 80–320 K range have been explained by means of the TE, considering GD of BH with linear bias dependence.     

Structural and magnetic properties of silver doped melt-textured YBCO prepared in a solar furnace

Magnetic measurements and structural investigation have been performed on melt-textured YBCO and AgYBCO HTS. The “sun” technique produces very dense YBCO (ρ=5.86 g cm⁻³) and AgYBCO [ρ=6.36 g cm⁻³; 10% b/w (by weight) silver. This technique renders samples with a large volume fraction of the Y₂BaCuO₅ (211) phase. The material is characterized by very high J_c values, as compared with bulk polycrystalline YBCO prepared by other methods. This feature is attributed to the enhanced amount of 211 particles which serve as pinning centers. Additional significant densification of the structure due to silver incorporation is obtained, and a reduction of the size of 211 inclusions is also observed. Silver doped samples show “butterfly”-like hysteresis loops at relatively high temperatures (T≥60K). This feature is probably associated with oxygen deficiency which arises from the slower oxygen diffusion into silver doped samples. J_c values enhancement was obtained in silver doped “sun” samples at high temperatures (T≥60K) and fields of 20–30 kOe. The temperature dependence of effective activation energy of pinning, U_eff, was measured for YBCO and AgYBCO materials. U_eff is higher in silver doped samples in the high temperature region T≥60K.     

Punch-through impact ionization MOSFET (PIMOS): From device principle to applications

In the present work a punch-through impact ionization MOSFET (PIMOS) is presented, which exploits impact ionization in low-doped body-tied Ω- and tri-gate structures to obtain abrupt switching (3–10 mV/decade) combined with a hysteresis in the I_D(V_DS) and I_D(V_GS) characteristics. The PIMOS device shows an extraordinary temperature stability up to 125 °C. The influence of various parameters on device performance as abrupt switch or memory cell is investigated. Reduction of the electrical channel length, i.e. of gate length and/or substrate doping, reduces the breakdown voltage and hence the DRAM operating voltage, but also increase the I_off. Two architectures for a capacitor-less DRAM cell are demonstrated and evaluated. In addition, a PIMOS n-type hysteretic inverter is demonstrated, which may serve as a 1T SRAM cell.     

Effects of channel thickness variation on bias stress instability of InGaZnO thin-film transistors

Here, we report on the effects of channel (or active) layer thickness on the bias stress instability of InGaZnO (IGZO) thin-film transistors (TFTs). The investigation on variations of TFT characteristics under the electrical bias stress is very crucial for commercial applications. In this work, the initial electrical characteristics of the tested TFTs with different channel layer thicknesses (40, 50, and 60 nm) are performed. Various gate bias (V_GS) stresses (10, 20, and 30 V) are then applied to the tested TFTs. For all V_GS stresses with different channel layer thickness, the experimentally measured threshold voltage shift (ΔV_th) as a function of stress time is precisely modeled with stretched-exponential function. It is indicated that the ΔV_th is generated by carrier trapping but not defect creation. It is also observed that the ΔV_th shows incremental behavior as the channel layer thickness increases. Thus, it is verified that the increase of total trap states (N_T) and free carriers resulted in the increase of ΔV_th as the channel layer thickness increases.     

A study of charge transport in a novel electroluminescent poly(phenylene vinylene-co-fluorenylene vinylene) based π-conjugated polymer

The charge transport properties in a novel electroluminescent poly{[2-(4′,5′-bis(3″-methylbutoxy)-2′-p-methoxy-phenyl)phenyl-1,4-phenylene vinylene]-co-(9,9-dioctyl-2,7-fluorenylene vinylene)} (BPPPV-PF) have been studied using a time-of-flight (TOF) photoconductivity technique. The TOF transients for holes were recorded over a range of temperatures (207–300 K) and electric fields (1.5 × 10⁵–6.1 × 10⁵ V/cm). The hole transport in this polymer was weakly dispersive in nature with a mobility at 300 K of 5 × 10⁻⁵ cm²/V s at 2.5 × 10⁵ V/cm. This increased to 8.4 × 10⁻⁵ cm²/V s at 6.1 × 10⁵ V/cm. The temperature and field dependence of charge mobility has been analyzed using the disorder formalisms (Bässler’s Gaussian disorder model (GDM) and correlated disorder model (CDM)). The fit with Gaussian disorder (GDM) model yielded the mobility pre-factor μ_∞ = 1.2 × 10⁻³ cm²/V s, energetic disorder parameter σ = 82 meV and positional disorder parameter Σ = 1.73. The average inter-site separation (a = 7 Å) and the charge localization length (L = 3.6 Å) was estimated by assuming the CDM type charge transport. The microscopic charge transport parameters derived for this polymer are almost identical to the reported values for fully conjugated polymers with high chemical purity. The results presented indicate that the charge transport parameters can be controlled and optimized for organic optoelectronic applications.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Fast and accurate method of lifetime estimation for HfSiON/SiO2 dielectric n-MOSFETs under positive bias temperature instability

This paper proposes a fast and accurate method to measure the constants a and n of the power law ∆ V_th = atⁿ for HfSiON/SiO₂ dielectric nMOSFETs under positive bias temperature instability (PBTI), where ∆ V_th is a shift of threshold voltage, and t is stress duration. The proposed method requires one nMOSFET only, uses a voltage ramp stress (VRS), measures ∆ V_th vs. t data during VRS, uses a regression method to fit the data for each VRS pulse to the power law to obtain a and n at each stress voltage V_g,str, then obtains five voltage-independent constants for the power law after fitting the curves of a and n vs. V_g,str to empirical models. The five voltage-independent constants agreed very well with those obtained using the constant voltage stress (CVS) method. After obtaining the voltage-independent constants, the lifetime t_L at an operating voltage V_op was estimated using the power law. The estimated t_L = 1.67 × 10⁸ s was quite close to t_L = 1.74 × 10⁸ s estimated using CVS, and to t_L = 1.72 × 10⁸ s estimated by extrapolating the ΔV_th vs. t curve measured at V_g,str = V_op = 1.2 V to ΔV_th = 200 mV. The time required for measurement was 900 s, compared to 30,000 s for the CVS method. These experimental results show that the proposed VRS-regression method is very useful for screening nMOSFETs under PBTI.     

Fabrication and characterization of Pb1−xYbxTe-based alloy thin-film thermoelectric generators grown by thermal evaporation technique

In this study p-Pb_0.925Yb_0.075Te:Te and n-Pb_0.94Yb_0.06Te powders synthesized by solid-state microwave technique were used to fabricate thermally evaporated thin films. The nanostructure and composition of the films were studied using X-ray diffraction (XRD), field emission scanning electron microscopy (FESEM) and energy dispersive X-ray spectroscopy (EDX). Electrical characterizations of the as-deposited films in terms of the Seebeck coefficient and electrical conductivity and power factor were conducted at a range of 298 K to 523 K. The microthermoelectric devices were composed of 20-pair and 10-pair p-Pb_0.925Yb_0.075Te:Te and n-Pb_0.94Yb_0.06Te thin films on glass substrates. The dimensions of the thin-film thermoelectric generators, which consisted of 20-pair and 10-pair legs connected by aluminum electrodes, were 23 mm×20 mm and 12 mm×10 mm, respectively. The 20-pair p–n thermocouples in series generated a maximum open-circuit voltage output (V_oc) of 0.581 V and a maximum output power of 25.87×10^?8 W at a temperature difference ΔT=164 K, whereas the 10-pair p–n thermocouples generated 0.311 V and 13.71×10^?8 W maximum V_oc and maximum output power, respectively, at ΔT=164 K.     

Scaling down of organic complementary logic gates for compact logic on foil

In this work, we realize complementary circuits with organic p-type and n-type transistor integrated on polyethylene naphthalate (PEN) foil. We employ evaporated p-type and n-type organic semiconductors spaced side by side in bottom-contact bottom-gate coplanar structures with channel lengths of 5 μm. The area density is 0.08 mm² per complementary logic gate. Both p-type and n-type transistors show mobilities >0.1 cm²/V s with V_on close to zero volt. Small circuits like inverters and 19-stage ring oscillators (RO) are fabricated to study the static and the dynamic performance of the logic inverter gate. The circuits operate at V_dd as low as 2.5 V and the inverter stage delay at V_dd = 10 V is as low as 2 μs. Finally, an 8 bit organic complementary transponder chip with data rate up to 2.7 k bits/s is fabricated on foil by successfully integrating 358 transistors.