0.18μm RF CMOS双向可控硅ESD防护器件的研究(英文)

基于传统双向可控硅(DDSCR)提出了两种静电放电(ESD)保护器件,可应对正、负ESD应力从而在2个方向上对电路进行保护。传统的DDSCR通过N-well与P-well之间的雪崩击穿来触发,而提出的新器件则通过嵌入的NMOS/PMOS来改变触发机制、降低触发电压。两种改进结构均在0.18μmRFCMOS下进行流片,并使用传输线脉冲测试系统进行测试。实验数据表明,这两种新器件具有低触发电压、低漏电流(～nA),抗ESD能力均超过人体模型2kV,同时具有较高的维持电压(均超过3.3V),可保证其可靠地用于1.8V、3.3V I/O端口而避免出现闩锁问题。     

应用于片上ESD防护中新式直通型MOS触发SCR器件的研究

在基于0.13μm CMOS工艺制程下,为研究片上集成电路ESD保护,对新式直通型MOS触发SCR器件和传统非直通型MOS触发SCR进行了流片验证,并对该结构各类特性进行了具体研究分析。实验采用TLP(传输线脉冲)对两类器件进行测试验证,发现新式直通型MOS触发SCR结构要比传统非直通型MOS触发SCR具有更低的触发电压、更小的导通电阻、更好的开启效率以及更高的失效电流。     

基于0.5 μm CMOS集成电路高低压兼容技术研究

将高压MOSFETs器件集成到低压CMOS数字和模拟电路中的应用越来越频繁。文章参考了Parpia提出结构,将高压NMOS、PMOS器件制作在商用3.3V/5V 0.5μmN-阱CMOS工艺中,没有增加任何工艺步骤,也没有较复杂BiCMOS工艺中用到的P-阱、P+、N+埋层,使用了PT注入。通过对设计结构的PCM测试,可以得到高压大电流的NMOS管BVdssn>23V～25V,P管击穿BVdssp>19V。同时,文章也提供了高压器件的设计思路和结果描述。     

辐照诱发CMOS电路器件间漏电流的理论研究

应用解析分析和TCAD器件模拟研究了CMOS电路中由辐照诱发的器件间漏电流问题。以往报道中对于场氧化层中陷阱电荷沉积进而导致寄生漏电流通道开启的物理过程存在若干不同观点,本文中针对这些矛盾点入手,在理论分析中考虑电场强度、氧化层厚度和掺杂浓度随深度的变化,而不仅仅是针对单一变量进行分析。在所有可能的器件间漏电流通道中,以N型阱作为漏区和源区的寄生结构在源漏间存在电压差时相对其他寄生结构对总剂量效应更敏感。但考虑到电路实际工作中N阱区通常接相同电源电平,所以该类寄生结构不会恶化实际CMOS电路的总剂量效应敏感性。总的来说,存在于实际电路中、并且在实际工作中仍然需要考虑的器件间漏电流通道对总剂量效应并不十分敏感（< pA）。     

A model for n-well junction effect on gate-charging damage inPMOSFETs

A quantitative model explaining N-well junction effect on gate charging damage in PMOSFETs is presented. This model takes into account the reverse-biased N-well junction leakage, generated both thermally and by photons and its behavior on limiting charging current passing through gate oxide during plasma processing. The modeling results suggest that plasma illumination plays a key role in enabling gate charging damage in PMOSFETs. The model can also apply to reverse-biased source and drain junctions in both P and NMOSFETs during plasma events     

Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process

Electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interface circuits in a 130-nm CMOS process is presented in this paper. First, the ESD protection diodes with different dimensions were designed and fabricated to evaluate their ESD levels and parasitic effects in gigahertz frequency band. With the knowledge of the dependence of device dimensions on ESD robustness and the parasitic capacitance, whole-chip ESD protection scheme were designed for the general receiver and transmitter interface circuits. Besides, an ESD protection scheme is proposed to improve the ESD robustness under the positive-to-V_SS (PS-mode) ESD test, which is the most critical ESD-test pin combination. With a silicon-controlled rectifier (SCR) between the I/O pad and V_SS, the clamping voltage along the PS-mode ESD current path can be reduced, so the PS-mode ESD level can be improved. Besides, the parasitic P-well/N-well diode in the SCR can provide the NS-mode ESD current path. Thus, SCR is the most promising ESD protection device in ESD protection design with low-capacitance consideration. The ESD protection scheme presented in this paper has been practically applied to an IC product with 2.5-Gb/s high-speed front-end interface.     

基于标准CMOS工艺的光敏传感单元结构的研究

基于0.6μm标准N阱CM O S工艺,研究了光敏管的结深及其侧墙结构对有源感光单元的感光面积百分比、光电响应信号幅值、感光灵敏度以及感光动态范围等参数的影响。研究了包括传统N+/P衬底的光敏管结构,以及网格状N+/P衬底,N阱/P衬底,网格状N阱/P衬底,P+/N阱/P衬底的光敏管结构。测试结果表明,不同深结深的光敏管结构,可以将器件感光灵敏度提高8~16.5 dB;网格状光敏管结构可以增加光敏管的侧墙面积,改善器件感光灵敏度;非网格状光敏管结构具有较低的暗电流和较大的感光动态范围,其中P+/N阱/P衬底光敏管结构的传感单元在变频两次扫描的工作方式下的感光动态范围可达139.8 dB。     

A multiple-terminal gate charging model

A gate charging model considering charging effect at all terminals of a MOSFET is reported in this letter. The model indicates two distinct charging mechanisms existing in P MOSFETs with a protecting device at their gates during plasma processing. The "normal-mode" charging mechanism exists when antenna size at the gate is higher than that at other terminals combined. In contrast, the "reverse-mode" charging mechanism exists in the case of antenna size at the gate lower than that at other terminals combined. The normal-mode mechanism will dominate the charging event when there is no protecting device at the transistor gate or the protecting device provides very low leakage current. On the other hand, the reverse-mode mechanism becomes dominant if the protecting device provides very high leakage current. The normal-mode charging mechanism is limited by the N-well junction leakage while in the reverse-mode mechanism, it is limited by the leakage of the protecting device. The model also suggests that larger N-well junction gives rise to higher charging damage in the normal-mode mechanism while it is opposite in the reverse-mode mechanism. These were confirmed by experimental data. The model points out that a zero charging damage can be achieved at certain combinations of the gate, source, drain and N-well antenna ratio. The knowledge of these transistor terminal antenna-ratio combinations will maximize the effective usage of the charging protection devices in circuit design. The reverse-mode charging mechanism suggests that the use of a high-leakage device at the transistor gate for charging protection may cause an opposite effect when the transistor terminal antenna ratios run into a condition that triggers this mechanism. This implies that PMOS transistors with gate intentionally pinned at ground or low potential in circuits may be prone to charging damage depending on the connectivity of their source, drain, and NW.     

双电荷离子注入的倒阱技术

本文从VLSl CMOS倒阱意义出发,结合我所中能离子注入的双电荷产生及其应用研究,介绍了在NV—3204注入机上实现近400keV的B受主高能注入以形成单峰(约1.0μm)、阱深(约2.0μm)的P倒阱。在此基础上,将它应用到新的CMOS硅栅工艺中。结果初步预示:新一代P倒阱CMOS硅栅工艺具有工艺流程简单、高温经历时间短、抗闩锁能力强等优点。对于只有中能离子注入机的单位,这一双电荷离子注入形成倒阱,将是一种现实有效的技术,也是P型深注入结的有效手段。     

Optimized retrograde N-well for 1-/spl mu/m CMOS technology

Using experiment and simulation, transistors in a high-energy implanted N-well are designed for optimum device performance suitable for 1-/spl mu/m CMOS technology. The effect of process parameters on device performance is obtained. Superior body effect, junction capacitance, punchthrough voltage, and subthreshold slope are achieved for 1-/spl mu/m n- and p-channel transistors. With shallow P/P+ epitaxial material, this retrograde N-well approach also provides latch-up immunity for high-density CMOS.     

工艺阱深对CMOS集成电路抗闩锁性能的影响

闩锁效应是体硅CMOS电路中最为严重的失效机理之一,而且随着器件特征尺寸越来越小,使得CMOS电路结构中的闩锁效应日益突出。以P阱CMOS反相器和CMOS集成电路的工艺结构为基础,采用可控硅等效电路模型,较为详细地分析了闩锁效应的形成机理,并利用试验证实,通过加深P阱深度,可以明显提升CMOS电路的抗闩锁性能。     

Modeling of N-well device and N-well field resistors

Modeling of both N-well device and N-well field is reported here. A simple model as well as an advanced model have been used to model both types of resistors. The modeling has been carried out using MATLAB 6.5 and equations derived from device physics. Detailed modeling of an N-well field resistor, which is not generally available in the literature, has been carried out in great details. The results of various models applicable to different types of N-well resistors have been compared with operating conditions kept the same. A simulation strategy for circuit design has also been suggested.     

28 nm PMOS器件中Ge注入对NBTI可靠性的影响

研究了28 nm 多晶硅栅工艺中Ge注入对PMOS器件的负偏压温度不稳定性(NBTI)的影响。在N阱中注入Ge,制作了具有SiGe沟道的PMOS量子阱器件。针对不同栅氧厚度和不同应力条件的器件,采用动态测量方法测量了NBTI的退化情况,采用电荷泵方法测量了界面态的变化情况。实验结果表明,由于Ge的注入,PMOS器件中饱和漏电流的退化量降低了43%,同时应力过程中产生的界面态得到减少,有效提高了PMOS器件的NBTI可靠性。     

Fully integrated wideband high-current rectifiers for inductively powered devices

This paper describes the design and implementation of fully integrated rectifiers in BiCMOS and standard CMOS technologies for rectifying an externally generated RF carrier signal in inductively powered wireless devices, such as biomedical implants, radio-frequency identification (RFID) tags, and smartcards to generate an on-chip dc supply. Various full-wave rectifier topologies and low-power circuit design techniques are employed to decrease substrate leakage current and parasitic components, reduce the possibility of latch-up, and improve power transmission efficiency and high-frequency performance of the rectifier block. These circuits are used in wireless neural stimulating microsystems, fabricated in two processes: the University of Michigan's 3-/spl mu/m 1M/2P N-epi BiCMOS, and the AMI 1.5-/spl mu/m 2M/2P N-well standard CMOS. The rectifier areas are 0.12-0.48 mm/sup 2/ in the above processes and they are capable of delivering >25mW from a receiver coil to the implant circuitry. The performance of these integrated rectifiers has been tested and compared, using carrier signals in 0.1-10-MHz range.     

Photo response analysis in CCD image sensors with a VOD structure

Photo response in CCD image sensors with Vertical-Overflow-Drain (VOD) was analyzed in an attempt to discover a way to lessen the photo response rise that accompanies increasing incident light intensity in the saturation region. A photo response analysis based on transistor I-V characteristics revealed that the extent of rise in the saturation region is uniquely determined by the non-ideality factor and temperature. Calculation of the non-ideality factor and its dependence on P-well impurity concentration and layer thickness further revealed that fabrication of P-wells with lower impurity concentrations and thicker layers would be effective in suppressing photo response rise     

A 300 MHz digital double-sideband to single-sideband converter in 1μm CMOS

A 43-tap FIR Hilbert transform digital filter chip is described which implements both a double-sideband (DSB) to single-sideband (SSB) conversion with a decimation-by-2 and the converse operation of a SSB to DSB conversion with an interpolation-by-2. Over 70 dB of image rejection is achieved by the Hilbert transform filter. The 3.57×7.07 mm², 45 000 transistor chip was fabricated in a 1 μm N-well CMOS process and operates at sample rates in excess of 300 MHz     

Small Signal Circuit Model of Double Photodiodes

The transmission delay of photogenerated carriers in a CMOS- process- compatible double photodiode (DPD) is analyzed by using device simulation. The DPD small signal equivalent circuit model which includes transmission delay of photogenerated carriers is given. From analysis on the frequency domain of the circuit model the device has two poles. One has the relationship with junction capacitance and the DPD‘s load, the other with the depth and the doping concentration of the N-well in the DPD. Different depth of the Nwell and different area of the DPDs with bandwidth were compared. The analysis results are important to design the high speed DPDs.     

PMOS晶体管工艺参数变化对SRAM单元翻转恢复效应影响的研究

基于Synopsys公司3D TCAD器件模拟,该文通过改变3种工艺参数,研究65 nm体硅CMOS工艺下PMOS晶体管工艺参数变化对静态随机存储器(Static Random Access Memory, SRAM)存储单元翻转恢复效应的影响。研究结果表明：降低PMOS晶体管的P+深阱掺杂浓度、N阱掺杂浓度或调阈掺杂浓度,有助于减小翻转恢复所需的线性能量传输值(Linear Energy Transfer, LET);通过降低PMOS晶体管的P+深阱掺杂浓度和N阱掺杂浓度,使翻转恢复时间变长。该文研究结论有助于优化SRAM存储单元抗单粒子效应(Single-Event Effect, SEE)设计,并且可以指导体硅CMOS工艺下抗辐射集成电路的研究。     

A parallel structure for CMOS four-quadrant analog multipliers andits application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV_p-p at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 μm single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm     

Low dark current CMOS image sensor pixel with photodiode structure enclosed by P-well

A low dark current CMOS image sensor pixel which can be easily implemented using a standard CMOS technology without any process modification is presented. Dark current is mainly generated from the interface region between the shallow trench isolation (STI) and the active region. The proposed pixel can reduce dark current by separating the STI region from a photodiode, using a simple layout modification to enclose the photodiode junction with the P-well. A test sensor array has been fabricated using 0.18 mum standard CMOS process and its performance characterised. The dark current of the proposed pixel has been measured as 0.93fA/pixel, which is by a factor of two smaller than that of the conventional design