Failure modes and effects analysis for high-power GaN-based light-emitting diodes package technology

In this study, nondestructive test is developed to analyze the structure failure of LED package. The relationship between thermal resistance analysis and LED package failure structure is build with T3Ster thermal transient tester and scanning electron microscope (SEM). The failure LED device with defect in the attaching layer and gap between LED chip and copper are designed advisedly. The failure factors of LED package have been measured with thermal resistance analysis and SEM cross-section images. The thermal dissipation performance of LED with defect in the attaching layer is indicated by thermal resistance analysis combined with SEM cross-section images. The blister in attaching layer results in 4.4 K/W additional thermal resistance. The gap between LED chip and copper also makes high additional thermal resistance with 8.6 K/W. Different failures of LED packages are indicated obviously using thermal transfer analysis. The LED package failure structure such as interface defect between solder and cup-shaped copper is able to forecast without destructive measurement.     

Heat sink performances of GaN/InGaN flip-chip light-emitting diodes fabricated on silicon and AlN submounts

Fabricating flip-chip light emitting diodes (FCLEDs) with two good thermal conductivity materials of silicon and aluminum nitride (AlN) as submount are investigated on its output power and heat sink capacity. It is known that many advantages exist in FCLED structures. In addition to the upward emitting light, the downward propagating light is reflected up by a high reflectance contact, increasing the light extraction. The heat generated in the LED flows directly through the interconnect metal of the submount, improving thermal conduction. Except blue shift at the low current injection region (0–0.3 A), the heat induced bang gap narrowing (red shift) at high current injection region (0.3–0.7 A) is observed with a red shift of 8.92 nm for conventional LED, 4.62 nm for silicon submount FCLED, and only 2.87 nm for AlN submount FCLED. The light intensity of FCLEDs with silicon and AlN submounts exhibits 1.6 and 7 times at an injection current of 0.35 and 0.7 A, respectively, larger than that of conventional LED.     

Thermal characterization of multicolor LED luminaire

The LED based dynamic lighting scheme, require compact and thermally efficient luminaire. This paper presents the thermal investigation on the conceptual design of 36 W multicolor light emitting diode (LED) luminaire. The developed prototype design includes configuration and placement of the multichip LED package, RGBW and single die amber LEDs in a 5 × 3 array on the heat sink. LED configurations with low power input are placed between the LEDs having the high power input. The proposed configuration and placement of LEDs reduces the local heat concentration in the centre region of the heat sink. The temperature of 72 °C at LED chip base plate is reduced to 32.1 °C on the heat sink surface. The numerical results are experimentally validated. The proposed method contributes to a reduction in the size of the luminaire and also enhancement of heat dissipation for improving the longevity of the multicolor based LED luminaire.     

Investigation of silicon-based light emitting diode sub-mounts: Enhanced performance and potential for improved reliability

Aluminum nitride (AlN) and aluminum oxide (Al₂O₃) ceramic light emitting diode (LED) sub-mounts are the most widely used package substrate for recently-developed high-brightness (HB) LED package applications because they exhibit superior thermal conductivity compared to conventional printed circuit board (PCB) package substrates. Nonetheless, the Al₂O₃ ceramic sub-mount exhibits thermal conductivity in an unacceptable range, and manufacturing the AlN ceramic sub-mount is problematic due to high material cost and difficult processing. Wafer-level packaging (WLP) technology has shown noticeable improvements in manufacturing and silicon exhibits outstanding thermal conductivity. Thus silicon might become an alternative package substrate for HB LEDs. This research studied the feasibility of replacing conventional ceramic sub-mounts with WLP LED sub-mounts. The performance features of thermal dissipation, insulation, and high temperature reliability of LED sub-mounts with variable SiO₂ thickness were analyzed and compared to the results obtained from conventional Al₂O₃ and AlN ceramic sub-mounts. Experimental results show that silicon LED sub-mounts lead to better thermal dissipation performance than do Al₂O₃ ceramic sub-mounts, and the results also reveal acceptable insulation performance and high temperature reliability for silicon sub-mounts.     

Simulation of LED based luminaires by using multi-domain compact models of LEDs and compact thermal models of their thermal environment

Fast and accurate prediction of hot lumens of LEDs installed in luminaires is an important step in the design of robust and reliable products. A possible approach to this is to create a multi-domain circuit model of a complete LED chip + package + luminaire system that can be simulated by any Spice-like circuit simulator with electro-thermal capabilities. Many LED chip and LED package models and modeling techniques have been published recently, but compact thermal modeling of luminaires as multi heat-source system was not yet dealt with in the literature. This paper aims to fill this gap be describing a systematic approach for system (luminaire) level analysis aimed at solving the combined thermal, electrical and light output simulation problem consistently by describing a method for creating a compact thermal model of LED luminaries with an approach borrowed from the layout based electro-thermal simulation of analog ICs. The applicability of the described method is demonstrated with a real life example, including the validation of the results with thermal measurements.     

Phase-change immersion cooling high power light emitting diodes and heat transfer improvement

A new cooling method of ethanol direct-contact phase-change immersion cooling was proposed in the thermal management of high power light emitting diodes (LED) and the feasibility of this cooling method was investigated. The heat generated by LED was measured firstly using two types of power systems: DC power and LED driver. Then the heat dissipation performance was evaluated under different experimental conditions. The results indicate that startup process of the cooling system is quick and only 450 s is needed to reach steady-state under heat load of 42.78 W. The minimum thermal resistance of 1.233 °C/W is obtained when liquid filling ratio is 33.14%. The junction temperature of LED under different absolute pressures is much lower than the limited value of 120 °C. Baffle with total height of 140 mm, bottom space height of 20 mm and distance away from substrate surface of LED of 8 mm improves heat transfer performance best due to ethanol self-circulating in the cooling receiver. Overall, the ethanol phase-change immersion cooling is an effective way to make sure high power LED work reliably and high efficiently.     

Thermal characterization of high power LED with ceramic particles filled thermal paste for effective heat dissipation

The next generation packaging materials are expected to possess high heat dissipation capability. Understanding the needs for betterment in the field of thermal management, the present study aims at investigating the package level analysis on a high power LED. In this study, commercially available thermal paste was heavily filled with ceramic particles of aluminium nitride (AlN) and boron nitride (BN) in order to enhance the heat dissipation of the device. Different particle sizes of AlN and BN fillers were incorporated homogenously into the thermal paste and applied as a thermal interface material (TIM) for an effective system level analysis employing thermal transient measurement. It was found that AlN TIM achieve less LED junction temperature by a difference of 2.20 °C compared to BN filled TIM. Furthermore, among D₅₀ = 1170 nm, 813 nm and 758 nm, the AlN at D₅₀ = 1170 nm was found to exhibit the lowest junction temperature of 38.49 °C and the lowest total thermal resistance of 11.33 K/W compared to the other two fillers.     

Lifetime and manufacturability of integrated power electronics

In case of battery electric cars, market data show a traditional exponential gradient of sales figures, known from other technology transitions. The worldwide installed wind and photovoltaic capacity show also an exponential gradient. Even the power density of power electronics is growing exponentially.Power electronics is a prerequisite to enable the exponential growth of power density.Requirements on power electronic packaging technologies are electric performance, thermal performance and robust design. Due to the lack of bond wires, SMD capacitors can be mounted close to semiconductors, resulting in a minimization of parasitic inductance. Thermally, the packaging technology benefits from heat spreading inside the copper leadframe and thin dielectric layers. It obtains a thermal resistance of 0.5 K/W, and there is potential to further reduce the thermal resistance by alternative dielectric material. The thermal resistance can be further reduced to at least 0.42 K/W by the construction of a double side chip cooling.A robust design can be offered by the combination of a chip copper metallization connecting to copper microvias connecting to the top copper layer, which means no difference in coefficients of thermal expansion. On the bottom side, a silver sinter layer offers a reliable connection between chip and leadframe.This paper describes production process optimizations, thermal optimization possibilities, power cycling lifetime measurements and first conductive anodic filament lifetime measurements at 1000 V DC. The outlook onto an integrated 120 A 700 V SiC MOSFET demonstrator is given.     

A study on thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assembly for thin chip-on-board (COB) packages

In this work, thermal cycling (T/C) reliability of anisotropic conductive film (ACF) flip chip assemblies having various chip and substrate thicknesses for thin chip-on-board (COB) packages were investigated. In order to analyze T/C reliability, shear strains of six flip chip assemblies were calculated using Suhir’s model. In addition, correlation of shear strain with die warpage was attempted.The thicknesses of the chips used were 180 μm and 480 μm. The thicknesses of the substrates were 120, 550, and 980 μm. Thus, six combinations of flip chip assemblies were prepared for the T/C reliability test. During the T/C reliability test, the 180 μm thick chip assemblies showed more stable contact resistance changes than the 480 μm thick chip assemblies did for all three substrates. The 550 μm thick substrate assemblies, which had the lowest CTE among three substrates, showed the best T/C reliability performance for a given chip thickness.In order to investigate what the T/C reliability performance results from, die warpages of six assemblies were measured using Twyman–Green interferometry. In addition, shear strains of the flip chip assemblies were calculated using measured material properties of ACF and substrates through Suhir’s 2-D model. T/C reliability of the flip chip assemblies was independent of die warpages; it was, however, in proportion to calculated shear strain. The result was closely related with material properties of the substrates. The T/C reliability of the ACF flip chip assemblies was concluded to be dominatingly dependent on the induced shear strains of ACF layers.     

Experimental study of microrectangular groove structure covered with multi mesh layers on performance of flat plate heat pipe for LED lighting module

The paper presents a novel concept for a coronary-stent-like model to solve the problem of compactness between wick and copper mesh, which can enhance the performance of the hybrid structure flat plate heat pipe (FPHP) of LED lighting modules. The various wick structures combine axial rectangular grooved structures, manufactured in aluminum extraction, and the concept of a coronary-stent-like model, which provides a supportive copper mesh and wick structure. In this study, the performance of FPHP was experimentally measured at different inclination angles and heating areas. The axial rectangular groove structure and copper mesh layer structures have different permeabilities and capillary pumping forces, and combining these two structures could be beneficial for pumping the required operational fluid across the axial groove structure and from the condenser to the evaporator under different inclinations of the flat plate heat pipe. The exterior wall temperature of the FPHP was measured to evaluate the thermal resistance and vapor heat transfer coefficient at the condenser and evaporator for 31 × 31 and 10 × 10 mm² heating areas. The experimental result showed that the FPHP has better performance in both the junction temperature of the LED light module and the uniformity of the substructure temperature. The highest FPHP temperature was decreased by 28%, as compared to a commercial substrate. In addition, a 200 W LED light module, running for 9 h with FPHP, maintained luminance at about 2080 lux due to its low thermal resistance and high capillary force.     

A study on the heat dissipation of high power multi-chip COB LEDs

In this study, the heat dissipation efficiencies of high power multi-chip COB (Chip-on-Board) LEDs with five different chip gaps were compared by assessing their junction temperature (T_j) and thermal resistance (R_th). Junction temperatures were measured using an IR camera and were also simulated by computational fluid dynamics (CFD) software. The effects of heat sinks with different surface areas, heat slugs made of different materials and different injection currents (different wattages) on high power LED junction temperatures are discussed. In addition, the optical characteristics of the LED, such as its lumens and luminous efficiency are evaluated. The experimental results show that a chip with a smaller gap has a higher junction temperature and more thermal resistance, and the junction temperature difference between the LEDs with the smallest and largest chip gaps is 3.12 °C. Optical performance analyses show that the LED with a larger chip gap has higher lumens and higher luminous efficiency. Thus, higher junction temperatures reduce the optical performance of high power LEDs.     

Process optimization of RTA on the characteristics of ITO-coated GaN-based LEDs

We present a detailed study on the optimization of rapid thermal annealing (RTA) on GaN-based light emitting diodes (LEDs). 14 mil × 28 mil GaN-based LED chips are fabricated with indium tin oxide (ITO) layer treated by RTA under various temperatures and times. Through the optical and electrical property analyses of ITO film, it is found that the transmittance and sheet resistance are improved after RTA process due to the better ITO crystallization and bigger grain size, compared with ITO treated by conventional furnace annealing. By employing electroluminescence measurement for the LED chips with RTA treatment, the forward voltage is found to be low as a result of low sheet resistance and contact resistance, and light output power (LOP) is high due to high ITO transmittance and good current density uniformity. Under RTA temperature of 550 °C and time of 3 min, the optimized LOP and forward voltage at 60 mA injection current are 71.2 mW and 2.97 V, respectively. Moreover, the reliability of the chips with RTA is better than those with furnace annealing.     

Optimization and validation of thermal management for a RF front-end SiP based on rigid-flex substrate

This paper mainly presents a new 3D stacking RF System-in-Package (SiP) structure based on rigid-flex substrate for a micro base station, with 33 active chips integrated in a small package of 5cm × 5.5cm × 0.8cm. Total power consumption adds up to 20.1 Watt. To address thermal management and testability difficulties of this RF SiP, a thermal test package is designed with the same package structure and assembly flow, only replacing active chips with thermal test dies (TTDs). Optimization and validation of thermal management for the thermal test package is conducted. Effects of the structure, chip power distribution, and ambient temperature aspects on the thermal performance are studied. Thermal vias designed in the organic substrate provide a direct heat dissipation path from TTDs to the top heatsink, which minimizes junction temperature gap of the top substrate from 31.2 °C to 5.3 °C, and enables junction temperatures of all the chips on the face to face structure to be well below 82 °C. Chip power distribution optimization indicates placing high power RF parts on the top rigid substrate is a reasonable choice. The ambient temperature optimizes with forced air convection and cold-plate cooling method, both of which are effective methods to improve thermal performances especially for this micro base station application where environment temperature may reach more than 75 °C. The thermal management validation is performed with a thermal test vehicle. Junction temperatures are compared between finite-volume-method (FVM) simulation and thermal measurement under the natural convection condition. The accordance of simulation and measurement validates this thermal test method. Junction temperatures of typical RF chips are all below 80 °C, which shows the effectiveness of thermal management of this RF SiP.     

Junction temperature and reliability of high-power flip-chip light emitting diodes

In this work, infrared micro-imaging, emission microscope measurements are performed on the chip surface of flip-chip light emitting diodes (FCLEDs). The temperature deviation on the chip surface increases from 19 to 146 °C when the injection current changes from 20 to 2000 mA. When the structure of FCLED is optimized, the temperature deviation becomes smaller. And the thermal resistance is achieved to as low as 10.4 °C/W. The finite element method calculation based on the model of steady-state current field and temperature field is carried out to investigate the effects of current spreading on thermal performance of FCLED.     

Improvement of thermal management of high-power GaN-based light-emitting diodes

The thermal management of high-power light-emitting-diode (LED) devices employing various die-attach materials is analyzed. Three types of die-attach materials are tested, including silver paste, Sn–3 wt.% Ag–0.5 wt.% Cu (SAC305) solder, and SAC305 solder added with a small amount of carbon nanotubes (CNTs). The analysis of thermal management is performed by comparing the temperatures of the LED chips in use and the total thermal resistances of the LED devices obtained respectively from the thermal infrared images and thermal transient analysis. Due to the high thermal conductivity of CNT, the addition of CNTs into the SAC305 solder reduces the total thermal resistance and chip temperature of the LED device, and the thermal management of the LED devices is improved accordingly.     

带有TSV的硅基大功率LED封装技术研究

介绍了一种带有凹槽和硅通孔(through silicon via,TSV)的硅基制备以及晶圆级白光LED的封装方法。针对硅基大功率LED的封装结构建立了热传导模型,并通过有限元软件模拟分析了这种封装形式的散热效果。模拟结果显示,硅基封装满足LED芯片p-n结的温度要求。实验结合半导体制造工艺,在硅基板上完成了凹槽和通孔的制造,实现了LED芯片的有效封装。热阻测试仪测得硅基的热阻为1.068K/W。实验结果证明,这种方法有效实现了低热阻、低成本、高密度的LED芯片封装,是大功率LED封装发展的重要方向。     

Fluid–solid coupling thermo-mechanical analysis of high power LED package during thermal shock testing

The virtual design by numerical simulation to model various accelerated reliability testing conditions is adopted to validate and improve the reliability of the high power LED package. In this study, the reliability of the high power LED package during thermal shock testing is investigated by fluid–solid coupling thermo-mechanical modeling by considering nonlinear time and temperature dependent material properties. Through fluid–solid coupling transient thermal transfer analysis, it is found that the maximum thermal gradient exceeds 75 K during the rapid cooling process and 91 K during the rapid heating process of the thermal shock testing which is ignored in the traditional isothermal assumption. The calculation results indicate that the equivalent plastic strain range of the bonding wire within the LED package with consideration of the temperature gradient is much higher than that with the isothermal assumption. The assumption of the isothermal condition is not appropriate which will lead to overestimation of the predicted lifetime. The viscoelastic behaviors of the silicone have significant influences on the lifetime prediction of the bonding wire and silicone with low elastic modulus and coefficient of thermal expansion (CTE) can significantly enhance the reliability of the bonding wire under the thermal shock loading. The results in this study could provide a guideline on design for reliability in the high power LED packaging.     

Reliability study of fiber-coupled photodiode module for operation at 4 K

The reliability of a photodiode module intended for operation at 4 K was investigated. Flip-chip bonded photodiodes and an adhesively bonded optical fiber attachment structure were considered. Finite element simulations of the thermomechanical stress were used to evaluate the stresses in different design configurations. Results showed that issues with chip cracking in silicon were eliminated by proper selection of component materials. Photodiode modules survived thermal cycling to 77 K and extended operation in 4 K.     

Study on thermal performance of high power LED employing aluminum filled epoxy composite as thermal interface material

This paper elucidates the thermal behavior of an LED employing metal filled polymer matrix as thermal interface material (TIM) for an enhanced heat dissipation characteristic. Highly thermal conductive aluminum (Al) particles were incorporated in bisphenol A diglycidylether (DGEBA) epoxy matrix to study the effect of filler to polymer ratio on the thermal performance of high power LEDs. The curing behavior of DGEBA was studied by differential scanning calorimetry (DSC) and thermogravimetric analysis (TGA). The dispersion nature of the Al fillers in polymer matrix was verified with Field Emission Scanning Electron Microscope (FESEM). The thermal performance of synthesized Al filled polymer composite as TIM was tested with an LED employing thermal transient measurement technique. Comparing the filler to polymer ratio, the rise in junction temperature for 60 wt% Al filled composite was higher by 11.1 °C than 50 wt% Al filled composite at cured state. Observed also from the structure function analysis that the total thermal resistance was 10.96 K/W higher for 60 wt% Al filled composite compared to 50 wt% Al filled composite. On the other hand, a significant rise of 9.5 °C in the junction temperature between cured and uncured samples of 50 wt% Al filled polymer TIM was observed and hence the importance of curing process of metal filled polymer composite for effective heat dissipation is discussed extensively in this work.     

B-Spline X-Ray Diffraction Imaging — Rapid non-destructive measurement of die warpage in ball grid array packages

Next generation “More than Moore” integrated circuit (IC) technology will rely increasingly on the benefits attributable to advanced packaging (www.itrs.net [1]). In these increasingly heterogeneous systems, the individual semiconductor die is becoming much thinner (25 to 50 μm, typically) and multiple dies can be stacked upon each other. It is difficult to assess non-destructively, non-invasively and in situ the stress or warpage of the semiconductor die inside these chip packages and conventional approaches tend to monitor the warpage of the package rather than the die.This paper comprises an account of a relatively new technique, which we call B-Spline X-Ray Diffraction Imaging (B-XRDI) and its application, in this instance, to the non-destructive mapping of Si semiconductor die lattice misorientation inside wire bonded encapsulated Low-profile Fine-pitch Ball Grid Array (LFPGA) packages. B-XRDI is an x-ray diffraction imaging technique which allows the user to reconstruct from a series of section x-ray topographic images a full profile of the warpage of the silicon semiconductor die inside such a chip package. There is no requirement for pre-treatment or pre-processing of the chip package and we show that synchrotron-based B-XRDI mapping of wafer warpage can be achieved with angular tilt resolutions of the order of 50 μrad ≈ 0.003° in times as short as 9–180 s (worst case X–Y spatial resolution = 100 μm) for a full 8.7 mm × 8.7 mm semiconductor die inside the fully encapsulated LFBGA packages. We confirm the usefulness of the technique by correlating our data with conventional warpage measurements performed by mechanical and interferometric profilometry and finite element modelling (FEM). We suggest that future developments will lead to real-time, or near real-time, mapping of thermomechanical stresses during chip packaging processes, which can run from bare wafer through to a fully encapsulated chip package.