基于分段循环冗余校验的极化码自适应连续取消列表译码算法

针对极化码连续取消列表(SCL)译码算法为获取较好性能而采用较多的保留路径数,导致译码复杂度较高的缺点,自适应SCL译码算法虽然在高信噪比下降低了一定的计算量,却带来了较高的译码延时。根据极化码的顺序译码结构,该文提出了一种分段循环冗余校验(CRC)与自适应选择保留路径数量相结合的SCL译码算法。仿真结果表明,与传统CRC辅助SCL译码算法、自适应SCL译码算法相比,该算法在码率R=0.5时,低信噪比下(–1 dB)复杂度降低了约21.6%,在高信噪比下(3 dB)复杂度降低了约64%,同时获得较好的译码性能。     

一种基于分段CRC码级联Hash极化码的设计

极化码作为一种线性分组码,具有较低的编码复杂度和确定的构造,但当其为中短码长时,性能会有所降低。提出一种基于分段循环冗余校验(cyclic redundancy check,CRC)码级联Hash极化码的设计方法,该方法在原有Hash极化码(Hash-Polar)的基础上,采用CRC分段校验进行双校验,分段CRC码在译码过程中能辅助路径度量,即对译码路径进行修饰,以此提高路径选择的可靠性,提高性能;另外,分段校验是将校验码分散地添加到输入的信息序列中,译码时对于CRC不通过的情况,可提前终止译码路径以省去不必要的译码计算量。最后,译码结束时,Hash校验码对修饰后的L条路径进行校验,选出最佳译码路径。仿真结果表明,所提出的设计方法比CRC辅助的Hash极化码(Hash-CRC-Polar)误码性能更优异。在高斯信道下,当码长为128bit、码率为1/2、误码率为10时,所提出的基于分段CRC校验码的Hash极化码比Hash-CRC-Polar获得了约0.25 dB的增益。     

数字调制下的极化码译码性能分析

数字调制技术是现代通信领域的一个重要环节,对于远距离通信中的噪声累加问题,可以通过脉冲判决再生的方式来消除,因此有效的调制方式对于提高频带利用率以及信号传输的可靠性有着非常重要的意义。在研究了针对极化码而提出的连续删除列表译码原理的基础上,探讨了在常用数字调制下极化码译码性能;通过MATLAB完成多种调制系统下的仿真,并对它们进行比较、分析,以便理解其优缺点及适用场合,实验结果表明上述调制方式以较低的代价在不同程度上改进了极化码的译码性能,为后续的应用研究提供参考。     

数字调制下的极化码译码性能分析

在研究了针对极化码而提出的连续删除列表译码原理的基础上,探讨了在常用数字调制下极化码译码性能。通过Matlab完成多种调制系统下的仿真,并对它们进行比较、分析,以便理解其优缺点及适用场合,实验结果表明,上述调制方式以较低的代价在不同程度上改进了极化码的译码性能,为后续的应用研究提供参考。     

系统极化码的高效低复杂度编译码算法研究

系统极化码能减弱非系统极化码在连续抵消(SC)译码时的误码扩散敏感性,且在相同计算复杂度下拥有更好的误码性能,已被第五代通信系统采用,作为信道编码方式之一。在对系统极化码进行构造时采用经典的巴氏参数界法,编码时采用复杂度低且高效的非迭代编码算法,译码时采用循环校验码(CRC)辅助的基于对数似然比的连续抵消列表算法(LLR-SCL)与再编码结合。仿真结果表明,低信噪比下中等长度的系统极化码的SCL译码性能远优于SC译码;再加以CRC辅助译码后,其性能可得到大幅提升。     

大气弱湍流信道下松弛极化码译码方法

针对自由空间光通信中存在的大气湍流降低通信系统误码性能的问题,提出了基于松弛极化码的分段式极化码-循环冗余校验-串行抵消列表(PC-CRC-SCL)译码方法,并将其用于自由空间光通信系统中,在大气弱湍流强度下进行了仿真分析.仿真结果表明:与完全极化码的分段式CRC-SCL译码方法相比,在误码率为10-4时,基于松弛极化...     

基于预译码的极化码最大似然简化连续消除译码算法

针对极化码译码串行输出造成较大译码时延的问题,该文提出一种基于预译码的最大似然简化连续消除译码算法。首先对译码树节点存储的似然值进行符号提取并分组处理,得到符号向量组;然后比较符号向量组与该节点的某些信息位的取值情况,发现向量组中储存的正负符号分布规律与该节点的中间信息位的取值具有一一对应的关系;在此基础上对组合码中间的1～2 bit进行预译码;最后结合最大似然译码方法估计组合码中的剩余信息位,从而得到最终的译码结果。仿真结果表明：在不影响误码性能的情况下,所提算法与已有的算法相比可有效降低译码时延。

     

极化码序列连续删除译码算法的改进设计

极化码连续删除译码算法性能和传统的LDPC码存在一定差距。序列连续删除算法(SCL)的提出极大地改善译码性能,是极化码推向实际应用中的重要一步。但是该算法复杂度较高,延迟大。改进的序列连续删除(SCL)译码算法是基于改善极化码码长受限的情况,文中描述SCL算法是通过码树上的搜索序列路径来表示译码过程。改进的算法通过减少译码算法在码树上的序列路径来降低时间和空间复杂度。通过仿真表明,改进的算法有效地降低了译码的复杂度同时在性能上也接近最大似然(ML)译码算法。     

循环冗余校验的实现方法

循环冗余校验在数字通信技术中有着广泛的应用。本文讨论了循环冗余校验的代数算法,并据此给出了软硬件的实现方法,供工程技术人员参考。     

Finding cyclic redundancy check polynomials for multilevel systems

This letter describes a technique for finding cyclic redundancy check polynomials for systems for transmission over symmetric channels which encode information in multiple voltage levels, so that the resulting redundancy check gives good error protection and is efficient to implement. The codes which we construct have a Hamming distance of 3 or 4. We discuss a way to reduce burst error in parallel transmissions and some tricks for efficient implementation of the shift register for these polynomials. We illustrate our techniques by discussing a particular example where the number of levels is 9, but they are applicable in general     

Optimum cyclic redundancy codes for noisy channels (Corresp.)

Binary cyclic redundancy codes for feedback communication over noisy digital links are considered. The standard 16-bit ADCCPt polynomial is designed for digital links that already have a low input bit error probability. For file transfer between personal computers over telephone circuits, the quality of the resulting digital circuit may be much lower. This leads to the consideration of 3-byte (24-bit) and 4-byte (32-bit) polynomials. Generator polynomials of a certain class are found that have minimum weight and yet achieve the bound on minimum distance for arbitrary codes. Particular polynomials for 24-bit and 32-bit redundancies are exhibited, of weight and distance 6 in the 24-bit case and weight 10 and distance 8 in the 32-bit case.     

32位CRC校验码的并行算法及硬件实现

通过对CRC校验码原理的分析,研究了一种并行32位CRC算法。该算法采用递推的方法,直接得出计算多位数据后的CRC余数与计算前余数之间的逻辑关系。相对于一般的按位串行计算或者查表并行计算的方法来说,该方法运算速度快且不需要额外的空间存储余数表,十分有利于硬件实现。     

Reliability-based incremental redundancy with convolutional codes

Incremental redundancy, or Hybrid type-II ARQ (HARQ), algorithms use a combination of forward error correction and retransmissions to guarantee reliable packet data communications. In this work, we propose a HARQ algorithm that exploits received packet reliability to improve system performance. Specifically, the receiver uses the average magnitude of the log-likelihood ratios of the information bits as the packet reliability metric, which is then used to determine the sizes of subsequent retransmissions. The proposed retransmission strategy attempts to maximize user throughput while satisfying a maximum packet delay constraint. The performance of our reliability-based HARQ algorithm is evaluated in static and time-varying channels through simulations. Furthermore, analytical results on the relationship between the reliability metric, the code rate and the block error rate are presented.     

极化码的多比特译码算法研究

针对极化码的连续消除列表（successive cancellation list,SCL）译码算法的高时延问题,提出了基于对数似然比的多比特SCL（multi-bit SCL,MSCL）译码算法,可以在一个判决时刻同时译出多个码字比特,在不损失译码性能的前提下,将译码时延由3N-2个时钟降为4N/M-2个时钟,相比于现有的多比特SCL译码算法,MSCL译码算法具有更低的路径度量值计算复杂度。为了降低循环冗余校验（cyclical redundancy check, CRC）辅助的SCL（CRC aided SCL,CA-SCL）译码算法的译码时延以及存储空间,提出了分段CRC辅助的MSCL（segmented CRC-aided MSCL,SCA-MSCL）译码算法,并提出了分段信息码字长度修正算法,来保证在信息位索引集A不变的前提下,实现每一分段结尾处对应的信息位索引能够被M整除。SCA-MSCL算法可以借助多个CRC判决来尽可能早地输出译码码字,从而减少译码器的存储空间以及译码时延。     

基于FPGA的循环不重复码研究

对激光信号进行有效的编码,可以减弱敌方干扰的效果,传递大量的战场信息,从而使军演更加贴近实际战场.文中详细地介绍了循环不重复码的基本编码原理.使用FPGA技术实现了发射编码激光脉冲的功能和接收编码激光脉冲的功能,通过modelsim进行了功能仿真,仿真结果表明发射模块和接收模块能成功发射和接收编码激光脉冲,从而实现战场...     

FIR parity check codes

This paper describes a method for packet synchronization and error detection for use in a synchronous digital communications system. The method relies upon a class of linear block codes that have parity checks that are expressed in terms of a finite-impulse response (FIR) filter. This system is incorporated in the newly established ITU standard of digital cable television standard, J.83 appendix B, which is based on an MPEG 2 transport packet data stream. This technique is also the basis for cable modem downstream transmission defined in the IEEE 802.14 and MCNS standards. The parity check structure is based on a pseudonoise sequence generated by a (binary) primitive polynomial. This structure allows for a computationally efficient implementation of the parity check FIR filter, in a recursive manner, that is none the less self-synchronizing. The FIR parity check codes that are described are characterized as the dual of a CRC-type, shortened cyclic code. The theory and computational structure of these codes are presented here; the J.83R code is used as an example of the general theory     

Optimum cycle redundancy-check codes with 16-bit redundancy

Optimal binary cyclic redundancy-check codes with 16 parity bits (CRC-16 codes) are presented and compared to those in existing standards for minimum-distance, undetected-error probability on binary symmetric channels (BSCs) and properness. The codes in several cases are seen to be superior at block lengths of practical interest when they are used on low-noise BSCs. The optimum minimum distance obtainable by some CRC-16 codes is determined for all block lengths. For several typical low-noise BSCs the minimum undetected error probability achievable with some CRC-16 codes is given for all block lengths     

低密度校验码(LDPG码)

低密度校验码(Low Density Parity Check Codes,LDPC codes)是当前编码理论领域研究最热的信道编码之一.本文首先对信道编码研究历程作了简单回顾,然后介绍了LDPC码的发展历程并全面介绍了其相关理论.对LDPC码的和积译码算法(Sum-Product.Algorithm,SPA)或置信传播算法(Belief Propagation Algorithm,BPA)、基于二分图的随机构造与代数构造、密度进化理论、高斯近似以及EXIT表分析等相关技术理论的发展和原理进行了详尽的阐述.同时本文还给出近年来 LDPC 码最新研究成果并给出一些开放性的研究课题.