Self-aligned SiGe NPN transistors with 285 GHz f/sub MAX/ and 207 GHz f/sub T/ in a manufacturable technology

This paper reports on SiGe NPN HBTs with unity gain cutoff frequency (f_T) of 207 GHz and an f_MAX extrapolated from Mason's unilateral gain of 285 GHz. f_MAX extrapolated from maximum available gain is 194 GHz. Transistors sized 0.12×2.5 μm² have these characteristics at a linear current of 1.0 mA/μm (8.3 mA/μm²). Smaller transistors (0.12×0.5 μm²) have an f_T of 180 GHz at 800 μA current. The devices have a pinched base sheet resistance of 2.5 kΩ/sq. and an open-base breakdown voltage BV_CEO of 1.7 V. The improved performance is a result of a new self-aligned device structure that minimizes parasitic resistance and capacitance without affecting f_T at small lateral dimensions     

DC, RF, and noise characteristics of carbon-doped base InP/InGaAsheterojunction bipolar transistors

The first successful demonstration of high-performance InP/InGaAs heterojunction bipolar transistors utilizing a highly carbon-doped base is reported. The detailed device characteristics including dc, RF, and noise performance have been investigated. For the first time base layers free of hydrogen passivation have been obtained using chemical beam epitaxy. The HBT's showed almost ideal dc characteristics; a gain independent of collector current, a near unity ideality factor, a very small offset-voltage, and a high breakdown voltage. Devices having two 1.5 μm×15 μm emitter fingers exhibited a maximum f_T of 115 GHz and f_max of 52 GHz. The device also exhibited a minimum noise figure of 3.6 dB and associated gain of 13.2 dB at a collector current level of 2 mA where a f_T of 29 GHz and f_max of 23 GHz were measured. The nearly ideal dc characteristics, excellent speed performance, and RF noise performance demonstrate the great potential of the carbon-doped base InP/InGaAs HBT's     

Process and device optimization of an analog complementary bipolarIC technology with 5.5-GHz fT pnp transistors

An analog complementary bipolar IC process has been developed featuring 9.0-GHz f_T npn and 5.5-GHz f_T pnp transistors. Process conditions for emitter, base, and collector of pnp transistors are optimized in order to achieve the best performance tradeoff between current gain, Early voltage, and cutoff frequency. With the optimized process conditions, the H_FE×V_A of pnp transistors is 350 V with f_T of 5.5 GHz and f_max of 8.5 GHz. These high performance pnp transistors have been integrated into an existing 9.0-GHz f_T npn bipolar process without introducing excessive additional process complexity and manufacturing costs. In addition, Schottky diodes, p-channel junction FET's and laser wafer trimmable precision NiCr resistors have been integrated into the process to enhance analog circuit design capability     

High-speed small-scale InGaP/GaAs HBT technology and itsapplication to integrated circuits

We have developed the advanced performance, small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) by using WSi/Ti base electrode and buried SiO₂ in the extrinsic collector. The base-collector capacitance C_BC was further reduced to improve high-frequency performance. Improving the uniformity of the buried SiO ₂, reducing the area of the base electrode, and optimizing the width of the base-contact enabled us to reduce the parasitic capacitance in the buried SiO₂ region by 50% compared to our previous devices. The cutoff frequency f_T of 156 GHz and the maximum oscillation frequency f_max of 255 GHz were obtained at a collector current I_C of 3.5 mA for the HBT with an emitter size S_E of 0.5×4.5 μm², and f_T of 114 GHz and f_max of 230 GHz were obtained at I_C of 0.9 mA for the HBT with S_E of 0.25×1.5 μm². We have also fabricated digital and analog circuits using these HBTs. A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB·Ω with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed, low-power circuit applications     

Sub-20 ps high-speed ECL bipolar transistor with low parasiticarchitecture

Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing f_T values. In this paper, we demonstrate a device with sub-20 ps t_pd values even at f_T=23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce C_CB, 2) a low-concentration collector design to reduce C_CB, 3) NiSi-salicided base and emitter electrodes to reduce R_B, and 4) a shallow base formed by double diffusion technology for relatively high f_T with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V     

Application of selective epitaxial silicon and chemo-mechanicalpolishing to bipolar transistors

Successful demonstration of single-polysilicon bipolar transistors fabricated using selective epitaxial growth (SEG) and chemo-mechanical polishing (CMP) is reported. The pedestal structure made possible by the SEG/CMP process combination results in significantly reduced extrinsic-base collector capacitance. Cut-off frequency (f_T) of devices with emitter stripe width of 1 μm, a base width of 110 nm, and a peak base doping of 3×10¹⁸ cm^-3 have been observed to improve from 16 GHz to 22 GHz when the extrinsic-base collector overlap is decreased from 1 μm to 0.2 μm. Leakage current, often a problem for SEG structures, has been reduced to 27 nA/cm² for the area component, and 10 nA/cm for the edge component, by (1) appropriate post-polish processing, including a high-temperature anneal and sacrificial oxidation, (2) aligning the device sidewalls along the 〈100〉 direction, and (3) the presence of the pedestal structure. Base-emitter junction nonideality in these transistors has also been investigated     

Demonstration of aluminum-free metamorphic InP/In0.53Ga0.47As/InP double heterojunction bipolar transistors on GaAssubstrates

We report, for the first time, the successful fabrication of aluminum-free metamorphic (MM) InP/In_0.53 Ga_0.47 As/InP double heterojunction bipolar transistors (DHBTs) on GaAs substrates with a linearly graded In_xGa_1-xP buffer grown by solid-source molecular beam epitaxy (SSMBE). Devices with 5×5 μm² emitters display a peak current gain of 40 and a common-emitter breakdown voltage (BV_CE0) higher than 9 V, a current gain cut-off frequency (f_T) of 48 GHz and a maximum oscillation frequency (f_max) of 42 GHz. A minimum noise figure of 2.9 dB and associated gain of 19.5 dB were measured at a collector current level of 2.6 mA at 2 GHz. Detailed analysis suggests that the degradation of the base-emitter heterojunction interface and the increase of bulk recombination are the most probable causes for the poorer device performance of current metamorphic HBTs compared with lattice-matched HBTs     

Ultra-high-speed InP/InGaAs heterojunction bipolar transistors

We report on the microwave performance of InP/In_0.53Ga _0.47As heterojunction bipolar transistors (HBT's) utilizing a carbon-doped base grown by chemical beam epitaxy (CBE). The f_T and f_max of the HBT having two 1.5×10 μm² emitter fingers were 175 GHz and 70 GHz, respectively, at I_C=40 mA and V_CE=1.5 V. To our knowledge, the f _T of this device is the highest of any type of bipolar transistors yet reported. These results indicate the great potential of carbon-doped base InP/InGaAs HBT's for high-speed applications     

Small-scaled InGaP/GaAs HBTs with WSi/Ti base electrode and buriedSiO2

This paper describes the fabrication and characteristics of small-scaled InGaP/GaAs HBTs with high-speed as well as low-current operation. To reduce both the emitter size S_E and the base-collector capacitance C_BC simultaneously, the HBTs are fabricated by using WSi/Ti as the base electrode and by burying SiO₂ in the extrinsic base-collector region under the base electrode. WSi/Ti simplifies and facilitates processing to fabricate a small base electrode, and makes it possible to reduce the width of the base contact to less than 0.4 μm without the large increase in the base resistance. The DC current gain of 20 is obtained for an HBT with S _E of 0.3×1.6 μm² due to the suppression of emitter size effect by using InGaP as the emitter material. An HBT with SE of 0.6×4.6 μm² exhibited f_T of 138 GHz and f_max of 275 GHz at I_C of 4 mA; and an HBT with SE of 0.3×1.6 μm² exhibited f_T of 96 GHz and f_max of 197 GHz at I_C of 1 mA. These results indicate the great potential of these HBTs for high-speed and low-power circuit applications     

Demonstration of submicron depletion-mode GaAs MOSFETs withnegligible drain current drift and hysteresis

We successfully fabricated submicron depletion-mode GaAs MOSFETs with negligible hysteresis and drift in drain current using Ga₂ O₃(Gd₂O₃) as the gate oxide. The 0.8-μm gate-length device shows a maximum drain current density of 450 mA/mm and a peak extrinsic transconductance of 130 mS/mm. A short-circuit current gain cutoff frequency (f_T) of 17 GHz and a maximum oscillation frequency (f_max) of 60 GHz were obtained from the 0.8 μm×60 μm device. The absence of drain current drift and hysteresis along with excellent characteristics in the submicron devices is a significant advance toward the manufacture of commercially useful GaAs MOSFETs     

High-linearity high-current-drivabilityGa0.51In0.49P/GaAs MISFET usingGa0.51In0.49P airbridge gate structure grown byGSMBE

A novel structure Ga_0.51In_0.49P/GaAs MISFET with an undoped Ga_0.51In_0.49P layer serving as the airbridge between active region and gate pad was first designed and fabricated. Wide and flat characteristics of g_m and f_max versus drain current or gate voltage were achieved. The device also showed a very high maximum current density (610 mA/mm) and a very high gate-to-drain breakdown voltage (25 V). Parasitic capacitances and leakage currents were minimized by the airbridge gate structure and thus high f_T of 22 GHz and high f_max of 40 GHz for 1 μm gate length devices were attained. To our knowledge, both were the best reported values for 1 μm gate GaAs channel FET's     

Submicron AlInAs/InGaAs HBT with 160 GHz fT at 1 mAcollector current

We have demonstrated a submicron heterojunction bipolar transistor (SHBT) with a unity current gain cutoff frequency (f_t) of 160 GHz at the very low current level of 1 mA. The AlInAs/InGaAs SHBT has a thin collector and uses stepper lithography with 0.1 μm registration accuracy to reduce the parasitic elements that typically limit the performance of small transistors. The same device has 100 GHz f_t at 200 μA. The result substantially improves upon the cutoff frequency of submicron compound semiconductor devices. The technology is appropriate for high speed, low power, high-density circuits     

Small-sized collector-up Ge/GaAs heterojunction bipolar transistorswith high gain, low base resistance, and high fmax

Small-sized collector-up Ge/GaAs HBT's are successfully fabricated and their operation at a high collector current density and at a high frequency is realized for the first time. The current gain of these devices reaches a peak value as large as 200 at a current density 6×10⁴ Acm^-2, and no degradation in the current gain is observed as the collector width is decreased down to 2 μm. The capability of lower voltage operation is also shown. Intrinsic and extrinsic base resistances are as low as 180 Ω/□ and 90 Ω/□, respectively. The calibrated values of f_T and f_max are 25 GHz and 60 GHz, respectively. The larger value of f_max compared with f_T might be attributed to low base resistance and low base-collector capacitance as expected from the collector-up structure     

Heavily carbon-doped InGaP/GaAs HBT's with buried polycrystallineGaAs under the base electrode

This paper describes a new approach to fabricating InGaP/GaAs heterojunction bipolar transistors (HBT's) with a high cutoff frequency (f_T), high maximum oscillation frequency (f_max), and low external collector capacitance (C_bc). To attain a high f_T and f_max, a heavy carbon-doping (1.3×10²⁰ cm^-3) technique was used with a thin (30-nm-thick) GaAs base layer, while for low C_bc, low-temperature gas-source molecular-beam epitaxial growth on SiO₂ -patterned substrates was used to bury high-resistance polycrystalline GaAs under the base electrode. An f_T of 120 GHz and an f_max of 230 GHz were achieved for three parallel 0.7×8.5 μm HBT's with an undoped-collector structure, and an f _T of 170 GHz and an f_max of 160 GHz were obtained for a single 0.9×10 μm HBT with a ballistic-collection-transistor structure. Compared to HBT's without buried poly-GaAs, the maximum stable gain was improved by 1.2 dB in the 0.7×8.5 μm HBT and by 2.3 dB in the 0.9×10 μm HBT due to the reduction in C_bc. These results show the high potential of the proposed HBT's for high-speed digital and broadband-amplifier applications     

0.10 μm graded InGaAs channel InP HEMT with 305 GHzfT and 340 GHz fmax

We report here 305 GHz f_T, 340 GHz f_max, and 1550 mS/mm extrinsic g_m from a 0.10 μm In_xGa _1-xAs/In_0.62Al_0.48As/InP HEMT with x graded from 0.60 to 0.80. This device has the highest f_T yet reported for a 0.10 μm gate length and the highest combination of f _T and f_max reported for any three-terminal device. This performance is achieved by using a graded-channel design which simultaneously increases the effective indium composition of the channel while optimizing channel thickness     

A high-frequency GaInP/GaAs heterojunction bipolar transistor withreduced base-collector capacitance using a selective buriedsub-collector

A C-doped GaInP/GaAs HBT using a selective buried sub-collector has been fabricated by two growth steps. The device was fabricated with minimum overlap of the extrinsic base and the sub-collector region to reduce base-collector capacitance. The experiment shows that the base collector capacitance is reduced to about half of that of an HBT without selective buried sub-collector while the base resistance remains unchanged. A current gain of 35, f_T of 50 GHz and f_max of 140 GHz are obtained with this technology     

High-Current-Gain InP/GaInP/GaAsSb/InP DHBTs With fT = 436 GHz

Combining a pseudomorphically strained (Ga,In)P emitter with a GaAs_0.6Sb_0.4 base effectively eliminates the emitter heterojunction type-II conduction band offset in InP/GaAsSb double heterojunction bipolar transistors (DHBTs). A peak f_T of 436 GHz at J_C = 10 mA/mum², with BV_CEO = 3.8 V, is achieved with 0.6 times 5 mum² InP/GalnP/GaAsSb DHBTs with a 75-nm InP collector. Compared to a binary InP emitter, the (Ga,In)P emitter doubles the DC current gain from 166 to 338 for otherwise identical devices. These are the highest DC current gain and cutoff frequencies to date in uniform base GaAsSb DHBTs. The gain improvement reported here will greatly facilitate device design tradeoffs that are encountered while scaling InP/GaAsSb DHBTs toward higher frequencies by allowing higher base doping levels and smaller emitter geometries.     

Epitaxially-grown GaN junction field effect transistors

Junction field effect transistors (JFETs) are fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition (MOCVD). The dc and microwave characteristics of the device are presented. A junction breakdown voltage of 56 V is obtained corresponding to the theoretical limit of the breakdown field in GaN for the doping levels used. A maximum extrinsic transconductance (g_m ) of 48 mS/mm and a maximum source-drain current of 270 mA/mm are achieved on a 0.8 μm gate JFET device at V_GS=1 V and V_DS=15 V. The intrinsic transconductance, calculated from the measured g_m and the source series resistance, is 81 mS/mm. The f_T and f_max for these devices are 6 GHz and 12 GHz, respectively. These JFET's exhibit a significant current reduction after a high drain bias is applied, which is attributed to a partially depleted channel caused by trapped hot-electrons in the semi-insulating GaN buffer layer. A theoretical model describing the current collapse is presented, and an estimate for the length of the trapped electron region is given     

Pnp HBT with 66 GHz fmax

The total emitter to collector delay for a Pnp AlGaAs/GaAs HBT has been reduced to 4.8 ps by employing a thin base (325 Å) and collector (2300 Å). Simultaneously, a low base sheet resistance of 170 ohms/square was achieved with tellurium doping. A higher collector doping than is typically used permitted operation at collector current densities in excess of 5×10⁴ A/cm². A single emitter (2×4 μm²) and a single base contact device topology has an f_t and f_max of 33 and 66 GHz, respectively     

A 44-GHz-high IP3 InP HBT MMIC amplifier for low DC powermillimeter-wave receiver applications

This paper reports on what is believed to be the highest IP3/P_dc power linearity figure of merit achieved from a monolithic microwave integrated circuit (MMIC) amplifier at millimeter-wave frequencies. The 44 GHz amplifier is based on an InP heterojunction bipolar transistor (HBT) technology with f_T's and f_max's of 70 and 200 GHz, respectively. The 44-GHz amplifier design consists of four prematched 1×l0μm² four-finger (40-μm²) heterojunction bipolar transistor (HBT) cells combined in parallel using a compact λ/8 four-way microstrip combiner. Over a 44-50-GHz frequency band, the amplifier obtains a gain of 5.5-6 dB and a peak gain of 6.8-7.6 dB under optimum gain bias. At a low bias current of 48 mA and a total dc power of 120 mW, the amplifier obtains a peak IP3 of 34 dBm, which corresponds to an IP3/P_dc power ratio of 21:1, a factor of two better than previous state-of-the-art MMIC's reported in this frequency range. By employing a thin, lightly doped HBT collector epitaxy design tailored for lower voltage and higher IP3, a record IP3/P_dc, power ratio of 42.4:1 was also obtained and is believed to be the highest reported for an MMIC amplifier of any technology. The new high-linearity HBT's have strong implications for millimeter-wave receiver as well as low-voltage wireless applications