倒装片可修复底部填充材料的研究现状及发展

有机基板上的倒装芯片一般采用底部填充技术以提高其封装的可靠性.有缺陷的芯片在倒装后难以进行返工替换,使得倒装芯片技术成本提高,限制了此技术的应用.提出新型可修复底部填充材料的开发成为解决这一问题的有效途径.介绍了倒装芯片的可修复底部填充技术和可应用于可修复底部填充材料的技术要求,并综述了国内外对于可修复底部填充材料的研究现状.     

为CSP和BGA而设计的底部填充剂的工艺优势

底部填充剂原本是专为倒装芯片设计的。由于硅质的倒装芯片的热膨胀系数比基板材质低很多，因此，在热循环测试中会产生相对位移，导致机械疲劳从而引起不良焊接。底部填充剂材料通常是环氧树脂，利用毛细作用原理渗透到倒装芯片底部，然后固化。它能有效提高焊点的机械强度，从而提高芯片的使用寿命。     

关于底部填充在倒装芯片应用中空洞缺陷的影响因素

底部填充包封材料起初应用于提高早期氧化铝（Al2O3）基材的倒装芯片的可靠性。在芯片最外围的焊点易疲劳而导致芯片功能失效．相对较小的硅片和基材间的热膨胀差异是芯片在经受热循环时产生这种问题的根源．这样，热循环的温度范围及循环的次数就决定了芯片的使用寿命．在芯片和基板间填充可固化的包封材料，可以很好地把热膨胀差异带来的集中于焊点周围的应力分散到整个芯片所覆盖的范围。 随着引入环氧材料作为倒装芯片的基材，底部填充材料的研发大大地加快了。为了延缓焊点的应力疲劳，较大的基材和芯片硅片材料间的热膨胀差异使得底部填充剂的应用成为必然．而在底部填充材料和芯片接合界面的分层及底部填充剂中的空洞是触发许多芯片产生问题的根本原因之一。本篇将要讨论的是减少底部填充剂中的空洞的一些方法．[编者按]     

底部填充技术的SMT应用研究

如BGA、CSP等倒装芯片的SMT应用越来越普遍,底部填充胶水可以有效提高倒装芯片焊点的机械强度,以避免因热循环应力疲劳或机械冲击力而产生的失效。本文详细描述了底部填充技术的SMT应用细节,包括底部填充胶水介绍、PCB DFM设计、涂胶前准备、涂胶过程和注意事项、涂胶设备介绍等。     

面向窄节距倒装互连的预成型底部填充技术

近年来随着电子产品的小型化发展,窄节距倒装芯片互连已经成为研究热点。传统的倒装芯片组装后底部填充技术(例如底部毛细填充)在用于窄节距互连时易产生孔洞,导致可靠性降低,因此产业界开发了面向窄节距倒装芯片互连的预成型底部填充技术,主要包括非流动底部填充和圆片级底部填充。介绍了这类新型底部填充技术的具体工艺及材料需求,并提出了目前其在大规模量产以及未来更窄节距应用中存在的问题及挑战,总结了目前产业界在提高量产生产效率、提升电互连的可靠性以及开发纳米级高热导率填料等方面提出的解决方案,分析了该技术未来的发展方向。     

倒装芯片放置工艺的设计分析

对倒装芯片不流动底部填充胶进行压迫流动填充,底部填料会对倒装芯片产生流体静态压力,阻碍芯片向下放置。根据牛顿流体挤压流动的静态近似分析估算出底部填料对芯片的作用力,分别计算在两种不同工艺条件下放置压力达到最大时,两种不同规格芯片与基板的间隔距离,比较与芯片凸点高度,然后计算使芯片凸点与基板键合区实现接触所需放置压力的最小保持时间,从正反两个方面讨论关键参数等对倒装芯片工艺设计影响。     

球形焊点三角形排列倒装芯片底部填充的能量法研究

对于具有球形焊点且呈正三角形排列的倒装芯片,由于其待填充的空隙结构复杂,难以通过平均毛细压来建立底部填充的解析模型.因此通过能量变化来分析底部填充过程以避免平均毛细压的计算.首先分析了底部填充过程中表面能的变化、动能的变化和流道壁面对流动的阻力损耗;然后根据能量守恒定律得到了反映底部填充过程的新解析模型;最后用计算流体力学(CFD)软件对底部填充过程进行了三维数值模拟,以此验证了基于能量法的新解析模型.能量法更具有通用性,可用于研究焊点形状和排列方式复杂的倒装芯片底部填充过程.     

助焊剂残留对底部填充粘接强度的影响

随着封装工艺的不断发展,芯片I/O数越来越多,高密度芯片封装必须采用倒装焊的形式。底部填充作为芯片倒装焊封装后的加固工艺,填充胶与倒装焊使用的助焊剂的兼容性对于研究倒装焊电路的长期可靠性至关重要。分析了底部填充胶与助焊剂的兼容性,以及助焊剂的残留对底部填充胶加固效果的影响。若助焊剂清洗不干净,会导致底部填充胶的粘接力下降,影响器件的质量。     

液态点胶新技术

在BGA、CSP以及倒装芯片表面贴装过程中，此类器件的液态底部填充过程非常重要，液态点胶的最新技术值得加以关注。     

底部填充工艺探讨

底部填充工艺是倒装芯片封装过程中的一个必不可少而且很关键的组成部分,底部填充工艺的成败将直接影响到封装的可靠性。本文针对底部填充工艺中需考虑的多个方面,如分配模式、胶水体积计算、硬件选择等,阐述如何改进工艺,增强底部填充的自动生产的能力。     

倒装芯片下填充工艺的新进展(二)

为了增加在有机基板上倒装芯片安装的可靠性,在芯片安装后,通常都要进行下填充。下填充的目的是为了重新分配由于硅芯片和有机衬底间热膨胀系数失配产生的热应力。然而,仅仅依靠填充树脂毛细管流动的传统下填充工艺存在一些缺点。为了克服这些缺点,人们研究出了一些新的材料和开发出了一些新的工艺。     

倒装芯片下填充工艺的新进展(一)

为了增加在有机基板上倒装芯片安装的可靠性,在芯片安装后,通常都要进行下填充。下填充的目的是为了重新分配由于硅芯片和有机衬底间热膨胀系数失配产生的热应力。然而,仅仅依靠填充树脂毛细管流动的传统下填充工艺存在一些缺点。为了克服这些缺点,人们研究出了一些新的材料和开发出了一些新的工艺。     

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法 ,确定了倒装焊 Sn Pb焊点的热循环寿命 .采用粘塑性和粘弹性材料模式描述了 Sn Pb焊料和底充胶的力学行为 ,用有限元方法模拟了 Sn Pb焊点在热循环条件下的应力应变过程 .基于计算的塑性应变范围和实验的热循环寿命 ,确定了倒装焊 Sn Pb焊点热循环失效 Coffin- Manson经验方程的材料参数 .研究表明 ,有底充胶倒装焊 Sn Pb焊点的塑性应变范围比无底充胶时明显减小 ,热循环寿命可提高约 2 0倍 ,充胶后的焊点高度对可靠性的影响变得不明显     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

Yield analysis and process modeling of low cost, high throughputflip chip assembly based on no-flow underfill materials

As a concept to achieve low-cost, high-throughput flip chip on board (FCOB) assembly, a new process has been developed implementing next generation flip chip processing based no-flow fluxing underfill materials. The low-cost, high throughput flip chip process implements large area underfill printing, integrated chip placement and underfill flow and simultaneous solder interconnect reflow and underfill cure. The goals of this study are to demonstrate feasibility of no flow underfill materials and the high throughput flip chip process over a range of flip chip configurations, identify the critical process variables affecting yield, analyze the yield of the high throughput flip chip process, and determine the impact of no-flow underfill materials on key process elements. Reported in this work is the assembly of a series of test vehicles to assess process yield and process defects. The test vehicles are assembled by depositing a controlled mass of underfill material on the chip site, aligning chip to the substrate pads, and placing the chip inducing a compression type underfill flow. The assemblies are reflowed in a commercial reflow furnace in an air atmosphere to simultaneously form the solder interconnects and cure the underfill. A series of designed experiments identify the critical process variables including underfill mass, reflow profile, placement velocity, placement force, and underfill material system. Of particular interest is the fact that the no-flow underfill materials studied exhibit an affinity for unique reflow profiles to minimize process defects     

Adhesion characterization of no-flow underfills used in flip chipassemblies and correlation with reliability

Adhesion is one of the key properties of underfills used in flip chip assemblies. This paper characterizes the adhesion strengths of no-flow underfill materials to various die passivations using the shear test techniques. A novel shear test vehicle with planner underfill layers between the die and substrate is presented. The adhesion strengths and failure modes of the no-flow underfill materials during shear testing correlate well with their thermal shock reliability test results. Underfill adhesion related failures such as delamination and crack are investigated and correlated between flip chip assemblies and shear test vehicle assemblies without solder joint interconnects     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.