A compact pre- and post-stress I-V model for submicrometerburied-channel pMOSFETs

In this paper, we report a new complete and analytical drain current model for pre- and post-stress submicrometer buried-channel (BC) MOSFETs operated in the forward- and reverse-biased modes. The model is valid in all regions of operation, and is developed using the quasi-two-dimensional approach. The hot-carrier-induced electron trapping in the oxide causes the channel shortening effect, which displays different behaviors for the device operated in the forward and reverse modes. It affects the threshold voltage reduction with channel length. This model incorporates the effects of velocity saturation, drain induced barrier lowering, channel length modulation, gate voltage induced mobility degradation, series source and drain resistances, and hot-carrier-induced oxide charges. The damaged channel region due to the fixed oxide charges trapped during hot-carrier injection is treated as a bias- and stress-time-dependent resistance. The resulting degraded BC MOSFET model is applicable for circuit simulation and its accuracy has been checked by the experimental data     

New short-channel n-MOSFET current-voltage model in stronginversion and unified parameter extraction method

A semiempirical strong inversion current-voltage (I-V) model for submicrometer n-channel MOSFETs which is suitable for circuit simulation and rapid process characterization is proposed. The model is based on a more accurate velocity-field relationship in the linear region and finite drain conductance due to the channel length modulation effect in the saturation region. The parameter extraction starts from the experimental determination of the MOSFET saturation current and saturation voltage by differentiating the output characteristics in a unified and unambiguous way. These results are used in order to systematically extract the device and process parameters such as the effective electron saturation velocity and mobility, drain and source series resistances, effective gate length and characteristic length for channel length modulation, and short-channel effects. The values agree well with other independent measurements. The results of experimental studies of wide n-MOSFETs with nominal gate length of 0.8, 1.0, and 1.2 μm fabricated by an n-well CMOS process are reported. The calculated I-V characteristics using the extracted parameters show excellent agreement with the measurement results     

Simulation of the accumulation-punchthrough mode in depletion MOSFETs

An analytical model is developed for a depletion MOSFET with a built-in channel operating in the accumulation-punchthrough mode. The model equations take into account several important effects associated with this mode of operation, including charge sharing between the channel and the source and drain regions. Closed-form expressions are derived for the output I–V characteristics, drain conductance in the linear region, and gate and substrate transconductances in the saturation region. Useful equations for the threshold and saturation voltages are also provided. High accuracy of the model is confirmed by the experimental results.     

High-accuracy physical modeling of submicrometer MOSFET's

When short-channel MOSFET transistor models are compared to experimental data, the uncertainty in some of the physical input variables often requires that some of the input variables be adjusted to fit the data. This uncertainty is increased by a lack of knowledge of process sensitivity information on critical parameters. These uncertainties have been eliminated using a two-dimensional finite-element model of a MOSFET with no free parameters. The model is compared to four self-aligned silicon-gate n-channel MOSFET's with channel lengths of 0.80, 1.83, 2.19, and 8.17 µm. The 0.80, 1.83, and 8.17-µm devices have phosphorus sources and drains. The 2.19-µm device has an arsenic source and drain. These devices span the range of channel lengths from a short-channel device, totally dominated by velocity saturation and source-drain profile shape, to a long-channel device, well characterized by a long-channel model. Using the data obtained from the measurements described in this work, it is possible to model the drain current for all of the transistors studied without adjustable parameters. Transistors with 0.80-µm channel length differ in model input from those with 8.17-µm channel length only in the length of the polysilicon gate. If sufficiently accurate parameters are available, these methods allow the characteristics of submicrometer transistors to be predicted with ±5-percent accuracy. These simulations show that the observed short-channel effects can be accounted for by existing mobility data and a simple empirical model of these data. Triode and saturation effects are dominated by two-dimensional drain field penetration of the channel region. Subthreshold effects are caused by distortion of fields in the entire channel region by the drain field.     

A simple and continuous MOSFET model

A simple CAD model is proposed for the short-channel enhancement-mode MOSFET. The conventional use of drain bias modulation of channel length to describe saturation characteristics has been discarded and replaced by drain bias enhancement of channel velocity. The model possesses continuity of current, transconductance and output conductance throughout the triode, and saturation ranges of operation. It has been tested against experimental transistors and against two-dimensional numerically simulated transistors, and has given satisfactory results in all cases. The model is based on good physics, is easy to understand, is straightforward to use, and is computationally efficient.     

深亚微米SOI栅控混合管(GCHT)的准二维电流解析模型

提出了深亚微米SOIGCHT电流模型.不同于普通MOSFET短沟模型的处理,计及受栅电压及基极电压同时控制的可动电荷的影响,采用准二维分析及抛物线近似,求出沟道长度及漏端电压对源端表面势的影响,较好地反映了电荷共享效应及DIBL效应,并定量计算出与漏电压和栅电压同时相关的动态阈值电压漂移量.模型中同时考虑了速度饱和效应、迁移率下降效应和沟道长度调制效应等.该模型具有清晰的物理意义,从理论上解释了GCHT具有较小的短沟效应及较高的阈值电压稳定性等物理现象.模型计算结果与数值模拟及实验结果吻合良好,较好地描述了短沟GCHT的物理特性.     

A charge-sheet analysis of short-channel enhancement-mode MOSFETs

A charge-sheet analysis of the short-channel MOSFET is presented. The expression achieved for the drain current, which takes into account both the drift and the diffusion components and also mobility degradation effects, holds in the strong-inversion, weak-inversion, and saturation regimes of the device operation, and results in a continuous function of all bias voltages. The model predicts an exponential dependence of the drain current on drain voltage in weak inversion and the threshold dependence on both channel length and drain voltage. Moreover, the proposed approach predicts results which satisfactorily compare with numerical simulations obtained from the two-dimensional analyzer MINIMOS and experimental data.     

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.     

An effective channel length determination method for LDD MOSFETs

We propose a definition of MOSFET effective channel length (L_EFF), that provides a method of determining L_EFF as a constant, and external resistance (R_EXT) virtually as a constant, even for lightly doped drain (LDD) transistors. A unified relationship between this L_EFF and MOSFET drive current (linear and saturation) that is common to a wide range of drain structures was confirmed. Therefore, the L_EFF is useful, not only for compact analytical models, but also as an index of MOSFET performance applicable to both single drain and LDD devices. The dependence of the channel length on the source/drain structure was clarified by introducing the concept of local contribution to channel length. The L_EFF varies, even if the metallurgical channel length is fixed, depending on the design of the source/drain     

带温度补偿的6H-SiC PMOS模拟与分析

提出了一个在较宽温度范围内能精确描述6H-SiC PMOS性能的器件模型。该模型将阈值电压、沟道迁移率、体漏电流、源漏薄层电阻的温度效应等效为相应的补偿电流源,并计入界面态电荷高斯分布模型及体内Poole-Frenkel效应。模拟结果表明,阈值电压是引起高温条件下输出电流变化的主要因素,同时随着温度的升高,由于体内缺陷的存在导致体漏电流所占比例不断增大,逐渐成为Ids的重要组成部分。     

An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI

Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.     

A DC model for asymmetric trapezoidal gate MOSFET's in stronginversion

Asymmetric trapezoidal gate (ATG) MOSFET is an innovative device having a structure of a relatively narrow drain-side width in order to reduce parasitic effects for enhancing device performance. In this paper, we develop a DC model for ATG MOSFET's. We use a charge-based approach to explore the asymmetric feature between source and drain of ATG MOSFET's, and obtain analytic formulae for threshold voltage, body effect, drain current, and channel length modulation effect in linear and saturation regions for both forward and reverse modes of operations. The model provides a physical analysis of the ATG structure, shows good agreement with measurement data, and is useful in circuit simulation with ATG devices     

Effects of the velocity saturated region on MOSFET characteristics

A simple, accurate and universal relationship between MOSFET drain current in saturation, effective channel length, and gate drive has been found. It can be explained by a simple analytical model, whose validity is supported by numerical simulation. The model shows that the length of a velocity saturated region is a crucial parameter for describing MOSFET performance, particularly for short channel devices. The shrinkage of the length deteriorates the merit of channel length scaling     

Analytical drain thermal noise current model valid for deep submicron MOSFETs

In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.     

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I_d-V_ds, I_d-V_gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.     

6H-SiCJFET高温解析模型

MOSFET模型一般使用不同的公式来描述不同的工作区，这使得在各工作区之间的过渡点上，模型的连续性受到限制.本文提出了一种简单有效的方法将各工作区用统一的公式来描述.它保持了原分区描述模型的精度，同时极大地改善了模型的连续性.     

A new long-channel MOSFET model

A new highly accurate long-channel MOSFET model which is valid both in the linear and saturation regions by taking into account two-dimensional effects over the whole channel is presented in this paper. The calculated results are in excellent agreement with the experimental data. Compared with three other long-channel MOSFET models, the double integral model, the charge-sheet model and the single-integral model, our model has some advantages. The results demonstrate that two-dimensional effects are important in the current continuity near the drain end of the channel and cannot be neglected when the MOSFET is operating in saturation.     

An analytic I—V model for lightly doped drain (LDD) MOSFET devices

An analytic I-V model for lightly doped drain (LDD) MOSFET devices is presented. In this model, the n^-region is considered to be a modified buried-channel MOSFET device, and the channel region is considered to be an intrinsic enhancement-mode MOSFET device. Combining the models of these two regions, the drain current in the linear/saturation regions and the saturation voltage can be calculated directly from the terminal voltages. In addition, the parameters used in the channel region can be extracted by a series of least square fittings. According to comparisons between the experimental data measured from the test transistors and the theoretical calculations, the developed I-V model is shown to be valid for wide ranges of channel lengths.     

Threshold and subthreshold characteristics theory for a very small buried-channel mosfet using a majority-carrier distribution model

Simple expressions of threshold and subthreshold characteristics for a very small buried-channel MOSFET is derived from a model of majority-carrier distribution along the channel. The carrier distribution is determined from the Poisson equation for a high-low junction. The basic formula for the subthreshold characteristic is derived from the majority-carrier drift-current equation. The theory is compared with the measured threshold voltages and the measured inverse semilogarithmic slopes of subthreshold current. The theoretical curves are in a reasonable agreement with experimental results. It is shown for a buried-channel MOSFET having a channel length less than 1 μm that the threshold and subthreshold characteristics change abruptly as the channel length is reduced because the majority-carrier concentration increases through the carrier diffusion from the source and drain terminals. The theoretical estimation shows that buried-channel MOSFETs will have the less short-channel effect than surface-channel MOSFETs for a small drain voltage. The theory also predicts that the buried-channel MOSFET can be scaled down in the same way as the surface-channel MOSFET.     

A charge-sheet capacitance model based on drain current modeling

Analytical models of the drain current and the capacitances of a MOSFET are formulated using the charge-sheet approach. Mobility reduction due to velocity saturation and interface scattering of carriers are taken into account. A saturation criterion is developed from the condition of output conductance continuity. The capacitance modeling does not require additional parameters not contained in the DC model. Comparison with experimental data confirms that the theory is useful for analog circuit simulation down to channel lengths of about 1 μm